CN105118409B - V BY ONE coding/decoding systems and method based on FPGA - Google Patents
V BY ONE coding/decoding systems and method based on FPGA Download PDFInfo
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- CN105118409B CN105118409B CN201510512724.9A CN201510512724A CN105118409B CN 105118409 B CN105118409 B CN 105118409B CN 201510512724 A CN201510512724 A CN 201510512724A CN 105118409 B CN105118409 B CN 105118409B
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Abstract
The invention discloses a kind of V BY ONE coding/decoding systems based on FPGA, the signal input part that the signal output part of group bag module passes through the first doubleclocking First Input First Output module connect coding module, the signal input part of the signal output part connection scrambler module of coding module, the signal output part of scrambler module connects the signal input part of descrambling module by deserializer, the signal output part connection of descrambling module unpacks the signal input part of module, unpack the signal input part of the signal output part connection decoder module of module, the signal output part of decoder module connects the signal input part of the second doubleclocking First Input First Output module.The present invention can be such that the volume of liquid crystal test device and power consumption significantly reduces, while integrated level greatly improves.
Description
Technical field
The present invention relates to the technical field of measurement and test of large scale liquid crystal module, and FPGA (Field- are based in particular to one kind
Programmable Gate Array, i.e. field programmable gate array) V-BY-ONE (a kind of high-definition digital display interface) compile
Decode system and method.
Background technology
Lifted with the demand of consumption, liquid crystal module size is increasing, resolution ratio more and more higher, the test of liquid crystal module
The bandwidth more and more higher of signal required for device, it is currently based on traditional LVDS (Low-Voltage Differential
Signaling, Low Voltage Differential Signal) interface test device, be directly to export multigroup low-voltage differential test signal by chip to enter
The detection of row liquid crystal module, following technical problem be present：
1st, low (the most of Low Voltage Differential Signal speed of Low Voltage Differential Signal speed in the test device based on LVDS interface
In below 1Gbps, not more than 1.5Gbps), the transmission cable that high bandwidth needs is various；
2nd, every group of Low Voltage Differential Signal in the test device based on LVDS interface is required to transmit clock, multigroup low voltage difference
Multipath clock corresponding to sub-signal needs, reduces effective bandwidth.
3rd, power consumption during multichannel low-voltage differential signal transmission is big, and electromagnetic interference is serious.
For above-mentioned technical problem, it is (a kind of special that technical staff have developed the V-BY-ONE based on the proprietary chips of ASIC
In the Digital Interface Standard of image transmitting) test device, the device by the low-voltage differential test signal of output by ASIC it is proprietary
Chip is converted into V-BY-ONE signals, and the detection of liquid crystal module is carried out with the V-BY-ONE signals after conversion, during by one section
Between use after, technical staff has found that above-mentioned V-BY-ONE test devices based on the proprietary chips of ASIC have following technology and asked
Topic：
1st, the single-chip of the V-BY-ONE test devices based on the proprietary chips of ASIC supports that passage is few, and multichannel is (i.e. multiple
Chip) when cause PCB (Printed Circuit Board, printed circuit board) area big, power consumption is high.
2nd, the system complex of the V-BY-ONE test devices based on the proprietary chips of ASIC is synchronous difficult；
3rd, the V-BY-ONE test devices based on the proprietary chips of ASIC are when being tested, it is necessary to which Low Voltage Differential Signal is turned
V-BY-ONE signals are changed to, it is necessary to increase corresponding translation interface, add the extra volume of test device；
4th, the speed range of the V-BY-ONE test devices based on the proprietary chips of ASIC is fixed, very flexible, it is impossible to support
High rate data transmission.
The content of the invention
Present invention aim to provide a kind of V-BY-ONE coding/decoding systems and method based on FPGA, the system and
Method can be such that the volume of liquid crystal test device and power consumption significantly reduces, while integrated level greatly improves.
In order to achieve this, the V-BY-ONE coding/decoding systems based on FPGA designed by the present invention, it is characterised in that：Bag
A group bag module, the first doubleclocking First Input First Output module, coding module, scrambler module, deserializer and decoding unit are included,
Wherein, the signal output part of described group of bag module passes through the first doubleclocking First Input First Output module (Double Clock
FIFO, First Input First Output) connect coding module signal input part, the signal output part of coding module connects
The signal input part of scrambler module is connect, the signal output part of scrambler module is defeated by the signal of deserializer connection decoding unit
Enter end.
The decoding unit includes descrambling module, unpacks module, decoder module, the second doubleclocking First Input First Output mould
Block, the signal input part of the descrambling module are connected with deserializer, and the signal output part connection of descrambling module unpacks module
Signal input part, unpack module signal output part connection decoder module signal input part, the signal output of decoder module
The signal input part of the second doubleclocking First Input First Output module of end connection.
A kind of method of V-BY-ONE encoding and decoding, it comprises the following steps：
Step 1：Packaged place by the rule of V-BY-ONE agreements in separation video input signals feeding group bag module 1
Reason, form the packet comprising video data and control data；
Step 2：Packet comprising video data and control data is sent to the first doubleclocking and first enters elder generation by group bag module
Dequeue module carries out clock zone conversion process, and the clock zone comprising video data and the packet of control data is transformed into V-
Clock zone corresponding to BY-ONE signaling interface layers；
Step 3：Packet behind change over clock domain is sent to coding module by the first doubleclocking First Input First Output module,
The packet behind change over clock domain is encoded according to pattern as defined in V-BY-ONE agreements in coding module, forms V-
BY-ONE protocol mode packets；
Step 4：Coding module is disturbed the V-BY-ONE protocol modes packet formed after coding feeding scrambler module
Code processing；
Step 5：V-BY-ONE protocol mode packets after scrambler module handles scrambler are sent by deserializer
Carried out and the corresponding scramble process of above-mentioned scrambler processing to descrambling module；
Step 6：Descrambling module by after scramble process V-BY-ONE protocol modes packet be sent into unpack module carry out with
Unpacking corresponding to above-mentioned group of bag is handled, and is reduced into above-mentioned V-BY-ONE protocol modes packet；
Step 7：Unpack the V-BY-ONE protocol mode packets formed after module handles unpacking and be sent to decoder module
Decoding process corresponding with above-mentioned coding is carried out, obtains the vision signal under V-BY-ONE interface clock domains, the vision signal bag
Video data and control data corresponding to including；
Step 8：Vision signal under above-mentioned V-BY-ONE interface clock domains is sent to the second doubleclocking elder generation by decoder module
Enter first dequeue module and carry out clock zone conversion process, by the vision signal under V-BY-ONE interface clock domains be reduced to it is above-mentioned
Separate separation video output signals corresponding to the clock zone of video input signals.
Beneficial effects of the present invention：
The group bag module that is set in the present invention, the first doubleclocking First Input First Output module, coding module, scrambler module,
Deserializer, descrambling module, module, decoder module and the second doubleclocking First Input First Output module are unpacked using FPGA realities
It is existing, in large scale module test equipment, integrated level is greatly improved, reduces volume, FPGA architecture is advantageous to faster V-BY-
ONE signaling rates.
In addition, the present invention can make full use of the multichannel transceiver that FPGA has, multichannel sheet can be arranged in a FPGA
The V-BY-ONE coding/decoding systems of invention, multichannel V-BY-ONE encoding and decoding processing (the proprietary chips of traditional ASCI can be carried out simultaneously
2 tunnels can only be handled), system complexity is reduced, reduces system power dissipation, structure of the invention is simple, proprietary compared to traditional ASCI
The labyrinth of chip, the present invention are easier to ensure that the synchronization between multichannel V-BY-ONE encoding and decoding processing；
Meanwhile (such as transistor to transistor logic level signal connects the diversity of the invention for taking full advantage of FPGA interface
Mouth, Low Voltage Differential Signal interface, digital display interface and mobile Industry Processor Interface), solve the proprietary chips of proprietary ASCI only
The problem of LVDS signals can be supported, there is provided good flexibility.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention.
Wherein, 1-group bag module, the 2-the first doubleclocking First Input First Output module, 3-coding module, 4-scrambler mould
Block, 5-deserializer, 6-descrambling module, 7-unpacking module, 8-decoder module, the 9-the second doubleclocking FIFO team
Row module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail：
A kind of V-BY-ONE coding/decoding systems based on FPGA, as shown in figure 1, first including group bag module 1, the first doubleclocking
Enter first dequeue module 2, coding module 3, scrambler module 4, deserializer 5, descrambling module 6, unpacking module 7, decoder module
8th, the second doubleclocking First Input First Output module 9, wherein, the signal output part of described group of bag module 1 is first by the first doubleclocking
Enter the signal input part of the first connect coding module 3 of dequeue module 2, the signal output part connection scrambler module 4 of coding module 3
Signal input part, the signal output part of scrambler module 4 connect the signal input part of descrambling module 6 by deserializer 5, descrambling
The signal output part connection of module 6 unpacks the signal input part of module 7, unpacks the signal output part connection decoder module 8 of module 7
Signal input part, the signal output part of decoder module 8 connects the signal input of the second doubleclocking First Input First Output module 9
End.
In above-mentioned technical proposal, the signal input part of described group of bag module 1 is used to access separation video input signals, described
The signal output part of second doubleclocking First Input First Output module 9 is used to export separation video output signals.
In above-mentioned technical proposal, the vision signal of the separation includes video data and control data.
In above-mentioned technical proposal, the vision signal of the separation is provided by figure signal generator or signal decoder module.
In above-mentioned technical proposal, the signal decoder module be transistor to transistor logic level (TTL,
Transistor transistor logic) signal decoder module or Low Voltage Differential Signal decoder module or numerical monitor (DP,
DisplayPort) interface signal decoder module or mobile Industry Processor Interface (MIPI, Mobile Industry
Processor Interface) signal decoder module.
A kind of method that V-BY-ONE encoding and decoding are carried out using said system, it comprises the following steps：
Step 1：Figure signal generator or signal decoder module will separate video input signals, and (transistor to transistor is patrolled
Collect level signal or Low Voltage Differential Signal or digital displaying signal or mobile Industry Processor Interface signal) feeding group bag module 1
The interior rule by V-BY-ONE agreements packages processing, forms the packet comprising video data and control data；
Step 2：Packet comprising video data and control data is sent to the first doubleclocking and first enters elder generation by group bag module 1
Dequeue module 2 carries out clock zone conversion process, and the clock zone comprising video data and the packet of control data is transformed into
Clock zone corresponding to V-BY-ONE signaling interface layers；
Step 3：Packet behind change over clock domain is sent to coding module by the first doubleclocking First Input First Output module 2
3, the packet behind change over clock domain is encoded according to pattern as defined in V-BY-ONE agreements in coding module 3, formed
V-BY-ONE protocol mode packets；
Step 4：The V-BY-ONE protocol modes packet formed after coding is sent into scrambler module 4 and carried out by coding module 3
Scrambler processing；Recovered clock when scrambler is easy to decode, demodulating data with descrambling, it is necessary to be used cooperatively；
Step 5：V-BY-ONE protocol modes packet after scrambler module 4 handles scrambler passes through the (V- of deserializer 5
BY-ONE is serial signal, it is therefore desirable to using deserializer 5) it is sent to the progress of descrambling module 6 and the processing of above-mentioned scrambler
Corresponding scramble process；
Step 6：V-BY-ONE protocol modes packet after scramble process is sent into unpacking module 7 and carried out by descrambling module 6
Unpacking processing corresponding with above-mentioned group of bag, is reduced into above-mentioned V-BY-ONE protocol modes packet；
Step 7：Unpack the V-BY-ONE protocol mode packets formed after module 7 handles unpacking and be sent to decoder module
8 carry out decoding process corresponding with above-mentioned coding, obtain the vision signal under V-BY-ONE interface clock domains, the vision signal bag
Video data and control data corresponding to including；
Step 8：Vision signal under above-mentioned V-BY-ONE interface clock domains is sent to the second doubleclocking elder generation by decoder module 8
Enter first dequeue module 9 and carry out clock zone conversion process, by the vision signal under V-BY-ONE interface clock domains be reduced to it is upper
State separation video output signals (corresponding transistor to transistor logic level corresponding to the clock zone of separation video input signals
Signal or Low Voltage Differential Signal or digital displaying signal or mobile Industry Processor Interface signal).
In above-mentioned steps 3, pattern as defined in the V-BY-ONE agreements is byte digital modeling or color of image depth mode
Or whether enable three dimensional pattern.
Above-mentioned byte digital modeling includes three byte modes, nybble pattern and five byte modes.
Need to use 8B10B scramblers according to the requirement of V-BY-ONE agreements, scrambler processing in the step 4 of above-mentioned technical proposal
Processing.
In above-mentioned technical proposal, the deserializer 5 includes transmitting terminal deserializer and receiving terminal deserializer,
In above-mentioned steps 5：V-BY-ONE packets after scrambler module 4 handles scrambler pass through transmitting terminal deserializer and receiving terminal
Deserializer is sent to descrambling module 6.Above-mentioned transmitting terminal deserializer and receiving terminal deserializer are used to receive and send out
Send the V-BY-ONE vision signals of PCML (a differential standard for being used for very high-speed interfaces) level.
In actual use, the V-BY-ONE coding/decoding systems of the multichannel present invention, figure signal hair can be built in FPGA
The multichannel V-BY-ONE coding/decoding systems into FPGA send separation video input signals to raw device simultaneously；
Furthermore it is also possible to using signal decoder module, by video data distribute module to multichannel V-BY-ONE encoding and decoding
System separates video input signals (transistor to transistor logic level signal or Low Voltage Differential Signal or numeral corresponding to sending
Show signal or mobile Industry Processor Interface signal)；
Both the above application form realizes multichannel V-BY-ONE encoding and decoding processing, improves at V-BY-ONE encoding and decoding
Manage efficiency.
The content that this specification is not described in detail belongs to prior art known to professional and technical personnel in the field.
Claims (9)
- A kind of 1. V-BY-ONE coding/decoding systems based on FPGA, it is characterised in that：Including group bag module (1), first doubleclocking First Input First Output module (2), coding module (3), scrambler module (4), deserializer (5) and decoding unit, wherein, it is described The signal that the signal output part of group bag module (1) passes through the first doubleclocking First Input First Output module (2) connect coding module (3) Input, the signal input part of the signal output part connection scrambler module (4) of coding module (3), the signal of scrambler module (4) are defeated Go out the signal input part that end connects decoding unit by deserializer (5)；The decoding unit includes descrambling module (6), unpacks module (7), decoder module (8), the second doubleclocking FIFO team Row module (9), the signal input part of the descrambling module (6) are connected with deserializer (5), and the signal of descrambling module (6) is defeated Go out the signal input part that end connection unpacks module (7), unpack the signal of the signal output part connection decoder module (8) of module (7) Input, the signal output part of decoder module (8) connect the signal input part of the second doubleclocking First Input First Output module (9).
- 2. the V-BY-ONE coding/decoding systems according to claim 1 based on FPGA, it is characterised in that：Described group of bag module (1) signal input part is used to access separation video input signals, the letter of the second doubleclocking First Input First Output module (9) Number output end is used to export separation video output signals.
- 3. the V-BY-ONE coding/decoding systems according to claim 2 based on FPGA, it is characterised in that：The video letter of separation Number include video data and control data.
- 4. the V-BY-ONE coding/decoding systems according to claim 2 based on FPGA, it is characterised in that：The video letter of separation Number provided by figure signal generator or signal decoder module.
- 5. the V-BY-ONE coding/decoding systems according to claim 4 based on FPGA, it is characterised in that：The signal decoding Module is transistor to transistor logic level signal decoder module or Low Voltage Differential Signal decoder module or digital display interface Signal decoder module or mobile Industry Processor Interface signal decoder module.
- A kind of 6. method of V-BY-ONE encoding and decoding, it is characterised in that it comprises the following steps：Step 1：Packaged processing by the rule of V-BY-ONE agreements in separation video input signals feeding group bag module (1), Form the packet comprising video data and control data；Step 2：Packet comprising video data and control data is sent to the first doubleclocking FIFO by group bag module (1) Queue module (2) carries out clock zone conversion process, and the clock zone comprising video data and the packet of control data is transformed into Clock zone corresponding to V-BY-ONE signaling interface layers；Step 3：Packet behind change over clock domain is sent to coding module by the first doubleclocking First Input First Output module (2) (3), the packet behind change over clock domain is encoded according to pattern as defined in V-BY-ONE agreements in coding module (3), Form V-BY-ONE protocol mode packets；Step 4：The V-BY-ONE protocol modes packet formed after coding is sent into scrambler module (4) and carried out by coding module (3) Scrambler processing；Step 5：V-BY-ONE protocol modes packet after scrambler module (4) handles scrambler is sent out by deserializer (5) Descrambling module (6) is sent to carry out and the corresponding scramble process of above-mentioned scrambler processing；Step 6：V-BY-ONE protocol modes packet after scramble process is sent into by descrambling module (6) unpacks module (7) progress Unpacking processing corresponding with above-mentioned group of bag, is reduced into above-mentioned V-BY-ONE protocol modes packet；Step 7：Unpack the V-BY-ONE protocol mode packets formed after module (7) handles unpacking and be sent to decoder module (8) decoding process corresponding with above-mentioned coding is carried out, obtains the vision signal under V-BY-ONE interface clock domains, the vision signal Including corresponding video data and control data；Step 8：Vision signal under above-mentioned V-BY-ONE interface clock domains is sent to the second doubleclocking and first entered by decoder module (8) First dequeue module (9) carries out clock zone conversion process, by the vision signal under V-BY-ONE interface clock domains be reduced to it is upper State separation video output signals corresponding to the clock zone of separation video input signals.
- 7. the method for V-BY-ONE encoding and decoding according to claim 6, it is characterised in that：In above-mentioned steps 3, the V- Pattern as defined in BY-ONE agreements is byte digital modeling or color of image depth mode or whether enables three dimensional pattern.
- 8. the method for V-BY-ONE encoding and decoding according to claim 7, it is characterised in that：The byte digital modeling includes three Byte mode, nybble pattern and five byte modes.
- 9. the method for V-BY-ONE encoding and decoding according to claim 7, it is characterised in that：The scrambler processing of the step 4 Handled using 8B10B scramblers.
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| CN107358928B (en) * | 2017-08-21 | 2022-12-23 | 武汉精测电子集团股份有限公司 | Ultrahigh resolution graphics signal generator and starting and upgrading method thereof |
| CN109254549A (en) * | 2018-08-31 | 2019-01-22 | 上海集成电路研发中心有限公司 | A kind of FPGA network and its working method |
| CN112637656B (en) * | 2020-12-15 | 2023-02-17 | 海宁奕斯伟集成电路设计有限公司 | Channel configuration method and device, electronic equipment and readable storage medium |
| CN114339107B (en) * | 2022-03-14 | 2022-06-24 | 武汉精立电子技术有限公司 | Method and device for reducing VBO signal rate and test equipment |
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