CN102740128A - Video transmission device with surfing function and implementation method thereof - Google Patents
Video transmission device with surfing function and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a video transmission device with a surfing function and an implementation method of the video transmission device, which can achieve the surfing function of remote display equipment. The video transmission device comprises an RJ45 socket, a PHY (Physical Layer) chip, a data processing module, a data receiving-transmitting module, a crystal oscillator, and a main data interface, wherein the crystal oscillator is connected with the PHY chip and the data processing module; and the main data interface is connected with the data processing module. According to the device and method, the data processing module converts a 100M RGMII (Reduced Gigabit Media Independent Interface) network signal and a video input signal into a high-frequency 2.5-bit network signal and a high-frequency 13.5-bit video signal respectively, and the high-frequency 2.5-bit network signal and the high-frequency 13.5-bit video signal are subjected to hybrid coding based on a certain format so as to form a continuous 16-bit even and odd field data frame; and the 16-bit even and odd field data frame is output through the data receiving-transmitting module; and meanwhile, the data processing module reversely processes the receiving data from the data receiving-transmitting module by decoding, separating and reducing the frequency, so as to complete duplex communication, therefore, the video display and web-surfing function can be achieved, and the performance of the video display control and monitoring system is improved.
Description
Technical field
The present invention relates to the video communication field, particularly a kind of video conveyer and its implementation with function of surfing the Net.
Background technology
At present, display devices such as LED display, liquid crystal-spliced wall, advertisement screen are realized functions such as video transmits, the control of screen body, monitoring passback, signal testing through optical fiber or netting twine.Along with the increase day by day of user's request, display device, particularly advertisement screen require to increase in the increasing demand that far-end can be realized function of surfing the Net or play-over Internet video.
Existing long-distance video shows in the tranmission techniques, if need realize function of surfing the Net at far-end, then needs the single pavement netting twine that local area network (LAN) is extended to the screen body end of display device, in control system, increases equipment for surfing the net or device simultaneously.This mode is complex design not only, and increases the netting twine laying, and cost is quite high.
Thereby prior art is still waiting to improve and improve.
Summary of the invention
Weak point in view of above-mentioned prior art; The object of the present invention is to provide a kind of video conveyer and its implementation with function of surfing the Net; Pass through data processing module; Unification is carried out format conversion and frequency translation with network signal, vision signal, after hybrid coding is handled, generates high-speed serial signals output through SerDes (parallel series and staticizer), and data processing module is carried out reverse decoding, separation and frequency reducing operation to the reception data simultaneously; Complete both-way communication, thus realize that display device is in the online of far-end or play-over the function of Internet video.
In order to achieve the above object, the present invention has taked following technical scheme:
A kind of video conveyer with function of surfing the Net; Be used to realize the function of surfing the Net of display device; It comprises RJ45 socket, PHY chip, data processing module and the data transmit-receive module that connects successively, crystal oscillator that is connected with PHY chip, data processing module and the master data interface that is connected with data processing module;
Said RJ45 socket connects remote network equipment at receiving terminal, connects the network equipment or Internet network interface at transmitting terminal, is used for the control signal or the transmission telecommunication network data of transmitting and displaying equipment;
Said PHY chip is 100,000,000 net PHY, is used for transmitting, receiving network clocking and data, and 100,000,000 net PHY can be embedded in the FPGA;
Said master data interface is used for the vision signal of external connection display equipment at transmitting terminal, is used for external video monitoring signal at receiving terminal;
Said crystal oscillator is used to provide system's reference clock;
Said data transmit-receive module is connected with said data processing module; Be used for that at transmitting terminal signal encoding is sent in the parallel mixing of control end and convert the output of difference serial signal to; Convert the difference serial signal decoding of controlled terminal passback to the parallel reception signal input that mixes; The difference mixed signal decoding that is used for that at receiving terminal transmitting terminal is sent generates the parallel reception signal input that mixes, and signal encoding is sent in the parallel mixing of controlled terminal convert the output of difference serial signal to;
Said data processing module; Be used for converting the 100000000 RGMII network signals of 25MHz into 75MHz RGMII network signal; Then 75MHz RGMII network signal is converted into 2.5 network signals being not less than 150MHz, converts the parallel video signal of 75MHz into be not less than 150MHz 13.5 digital video signals; Again 2.5 network signals and 13.5 digital video signal hybrid codings are constituted 16 continuous digit pair words, strange digital data frame; Converting high-speed serial signals to through said data transmit-receive module again sends; Said data processing module is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously, accomplishes both-way communication, thereby the video of realizing far-end shows and function of surfing the Net.
In the described video conveyer with function of surfing the Net, said data processing module comprises that network data raising frequency module, main data signal generation module, master data send modular converter, data mixing module, phase-locked loop, signal separation module, network data frequency reducing module and master data receiving processing module;
Said phase-locked loop is connected with data transmit-receive module with crystal oscillator, network data raising frequency module, master data transmission modular converter, signal separation module, master data receiving processing module, data mixing module; Be used to produce network data raising frequency module, master data transmission modular converter, signal separation module and required 25MHz, the 75MHz phase shift clock of master data receiving processing module, and produce network data raising frequency module, master data transmission modular converter, data mixing module, data transmit-receive module and the required 150-156.25MHz high frequency serial reference clock of signal separation module;
Said network data raising frequency module is connected with PHY chip, data mixing module; Being used for to be the 6 parallel-by-bit fan-in network signals of 75MHz from the 6 parallel-by-bit fan-in network conversion of signals of the RGMII 25MHz of PHY chip, and the 2.5 parallel-by-bit signals that the 5 parallel-by-bit network signals that will not contain the 75MHz of transmission clock again change 16 bit data bus of high frequency serial reference clock into output to the data mixing module;
Said main data signal generation module sends modular converter with master data interface, master data and is connected; Be used for converting external vision signal into 24 RGB parallel video data and 4 digital video control signals at transmitting terminal and send to master data and send modular converter, then decoding generates the video monitoring image master data and outputs to master data and send modular converter to video monitoring signal at receiving terminal;
Said master data is sent modular converter and is connected with the data mixing module; Be used for 28 RGB parallel video data that are not more than 75MHz at transmitting terminal; Convert the 27 parallel-by-bit video datas of 75MHz into; The 13.5 parallel-by-bit vision signals that change 27 parallel-by-bit vision signals 16 bit data bus of 150-156.25MHz high frequency serial reference clock into again output to the data mixing module, and the 13.5 parallel-by-bits passback master data that the master data that will comprise video monitoring signal equally at receiving terminal converts 16 bit data bus of 150-156.25MHz high frequency serial reference clock into outputs to the data mixing module;
Said data mixing module is connected with data transmit-receive module, is used for 13.5 main data signal and 2.5 100,000,000 network signal hybrid codings with high frequency serial reference clock, and the mixing transmission signal that generates 16 parallel-by-bits is transferred to data transmit-receive module;
Said signal separation module is connected with the master data receiving processing module with network data frequency reducing module; Be used for separating into the reception network signal of 75MHz and the receiving video signals of 75MHz at receiving terminal from the parallel mixed signal of the 150-156.25MHz of data transmit-receive module; And will receive network signal and output in the network data frequency reducing module; Receiving video signals is transferred in the master data receiving processing module; To receive Signal Separation from the parallel mixing of data transmit-receive module at transmitting terminal and become the 100000000 net backhaul signals of 75MHz and the master data return signal of 75MHz, output to network data frequency reducing module and master data receiving processing module respectively;
Said network data frequency reducing module is connected with signal separation module with crystal oscillator, PHY chip, and 6 100,000,000 of the RGMII net signal that is used for 100,000,000 net conversion of signals with 75MHz and is 25MHz outputs to the PHY chip, accomplishes the transmitted in both directions of 100,000,000 nets;
Said master data receiving processing module is connected with signal separation module; Being used in the future at receiving terminal, the isolated transmitting terminal video data of signal separation module carries out format analysis processing; The generation display data stream outputs to corresponding display equipment and realizes long-range demonstration, at transmitting terminal video monitoring signal and the monitor signal that the isolated return signal of signal separation module converts required frequency into is flowed to monitor or other relevant devices.
In the described video conveyer with function of surfing the Net, said data processing module preferably adopts fpga chip to realize.
In the described video conveyer with function of surfing the Net, said data transmit-receive module transceive data adopts optical communication or netting twine communication.
In the described video conveyer with function of surfing the Net, said crystal oscillator produces the reference clock of 25MHz, and is connected with phase-locked loop, network data frequency reducing module in the said data processing module with said PHY chip.
In the described video conveyer with function of surfing the Net; Said master data receiving processing module will be in the time will carrying out format analysis processing from the video data of data transmit-receive module; Comprise and handle HDMI, DVI, HD-SDI, SDI or LED display format coding, generate display data stream.
In the described video conveyer with function of surfing the Net, said data transmit-receive module comprises serializer/de-serializers and optic module.
In the described video conveyer with function of surfing the Net, the preferred model of said serializer/de-serializers is TLK3101.
In the described video conveyer with function of surfing the Net, be integrated with network transformer and LED lamp in the said RJ45 socket.
A kind of method that adopts above-mentioned video conveyer to realize the display device function of surfing the Net, it comprises:
Send the telecommunication network data to data processing module by the RJ45 socket through the PHY chip;
Convert the 100000000 RGMII network signals of 25MHz into 75MHz RGMII network signal through data processing module; Then 75MHz RGMII network signal is converted into 2.5 network signals being not less than 150MHz, converts the parallel video signal of 75MHz into be not less than 150MHz 13.5 digital video signals; Again 2.5 network signals and 13.5 digital video signal hybrid codings are constituted 16 continuous digit pair words, strange digital data frame; Convert high-speed serial signals to through said data transmit-receive module at last and send to a distant place; Data processing module is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously; Constitute duplex signaling, thereby the video of realizing far-end shows and function of surfing the Net.
Compared to prior art; A kind of video conveyer and its implementation provided by the invention with function of surfing the Net; Adopted data processing module to convert 100,000,000 RGMII network signals, video input signals into high-frequency 2.5 network signals, 13.5 digital video signals respectively; And by sending through SerDes behind certain form hybrid coding, data processing module is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously again.A kind of video conveyer and its implementation provided by the invention with function of surfing the Net; Utilize existing video to transmit passage; Need not to lay in addition private network cable; Just can realize the Internet video broadcast or the function of surfing the Net of distal displayed equipment, the network equipment, strengthen video and shown control or monitor system performance, reduce the expenditure of cost.
Description of drawings
Fig. 1 has the structured flowchart of the video conveyer of function of surfing the Net for the present invention.
Fig. 2 has a network data raising frequency module in the video conveyer of function of surfing the Net for the present invention RGMII 25MHz network signal converts the waveform sketch map of 75MHz network signal to.
Fig. 3 has a network data frequency reducing module in the video conveyer of function of surfing the Net for the present invention 75MHz network signal converts the waveform sketch map of RGMII 25MHz network signal to.
Fig. 4 has 16 high frequency serial reference clock blended data frame coding method sketch mapes in the video conveyer of function of surfing the Net for the present invention.
Embodiment
The present invention provides a kind of video conveyer and its implementation with function of surfing the Net, and is clearer, clear and definite for making the object of the invention, technical scheme and effect, below develops simultaneously embodiment to further explain of the present invention with reference to accompanying drawing.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
See also Fig. 1, it is the structured flowchart with video conveyer of function of surfing the Net provided by the invention.As shown in the figure, it comprises RJ45 socket 10, PHY chip 11, data processing module 1 and the data transmit-receive module 19 that connects successively, crystal oscillator 17 that is connected with PHY chip 11, data processing module 1 and the master data interface 13 that is connected with data processing module 1.
Said RJ45 socket 10 is connected with said data processing module 1; Its inner packet includes network transformer and LED light; Be connected with the remote external equipment for surfing the net at receiving terminal (not indicating among the figure), be connected with the network equipment (like main control computer network interface or other Internet network interface), be used for the control signal and transmission telecommunication network data of display device at transmitting terminal (not indicating among the figure); For example; But the control signal of transmitting and displaying equipment (like liquid crystal-spliced wall or LED display) when the RJ45 socket connects the main control computer network interface when connecting the Internet network interface, can realize the online of far-end network equipment.
Said PHY chip 11 is 100,000,000 net PHY, is connected with said RJ45 socket 10, said data processing module 1, is used for transmitting, receiving network clocking and data, and 100,000,000 net PHY can be embedded in the FPGA.
Said master data interface 13 is connected with said data processing module 1, is used for the vision signal of external connection display equipment at transmitting terminal, is used for external video monitoring signal at receiving terminal.
Said crystal oscillator 17 is connected with said PHY chip 11, said data processing module 1, is used to provide system's reference clock.
Said data processing module 1 comprises network data raising frequency module 12, main data signal generation module 14, master data transmission modular converter 15, data mixing module 16, phase-locked loop 18, signal separation module 20, network data frequency reducing module 21 and master data receiving processing module 22; It is used for converting 25MHz RGMII network signal into 75MHz RGMII network signal; Then 75MHz RGMII network signal is converted into 2.5 high frequency network signals being not less than 150MHz, converts the parallel video signal of 75MHz into be not less than 150MHz 13.5 high-frequency video signals; Again 2.5 network signals and 13.5 digital video signals are constituted 16 continuous digit pair words, strange digital data frame by certain form hybrid coding; Converting high-speed serial signals to through said data transmit-receive module 19 again sends; Said data processing module 1 is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously; Realize the transmitted in both directions of video data, control data and network data, thereby the video of realizing far-end shows and function of surfing the Net.
In the present embodiment, the extensive fpga chip able to programme of said data processing module 1 preferred employing is realized.
In the said data processing module 1; Said phase-locked loop 18 is the PLL phase-locked loop; It sends modular converter 15, signal separation module 20, master data receiving processing module 22, data mixing module 16 and data processing module 1 data transmit-receive module 19 in addition with crystal oscillator 17, network data raising frequency module 12, master data and is connected; Said phase-locked loop 18 is input with system's reference clock of 25MHz; The various frequency multiplication phase shift clocks that the generation system is required; Comprise that producing said network data raising frequency module 12, master data sends modular converter 15, signal separation module 20 and master data receiving processing module 22 required 25MHz, 75MHz phase shift clock, and produce said network data raising frequency module 12, master data and send the required 150-156.25MHz high frequency serial reference clock of modular converter 15, data mixing module 16, signal separation module 20 and the data transmit-receive module beyond the data processing module 1 19.
Said data transmit-receive module 19 is connected with data mixing module 16, signal separation module 20 and phase-locked loop 18 in the said data processing module 1; Being used in the future at transmitting terminal (control end), the parallel mixing transmission signal encoding of Self Control end data mixing module 16 converts the output of difference serial signal to; The difference serial signal decoding of controlled terminal passback converted to parallel the mixing receive signal and input to local signal separation module 20; The difference mixed signal decoding that is used for transmitting terminal is sent at receiving terminal (controlled terminal) generates and parallel the mixing receives signal and input to local signal separation module 20, will send signal encoding from the parallel mixing of controlled terminal data mixing module 16 and convert the output of difference serial signal to.Wherein, the communication mode of data transmit-receive module 19 can adopt optical communication, also can adopt high speed netting twine communication pattern, and application model is expanded to family.
Please continue to consult Fig. 1; In the specific implementation, said PHY chip 11 adopts 100,000,000 net PHY chips, and output is connected with network data raising frequency module 12 in the said data processing module 1; Input is connected with network data frequency reducing module 21, is used to transmit network clocking and data; The RGMII pattern of preferred 12 buses of the interface modes of PHY chip 11; Comprise transmission clock TX_CLK, send data TXD [3..0], send control TX_CTL and receive clock RX_CLK, receive data RXD [3..0], receive control RX_CTL, 100,000,000 net PHY chips are supported the transmission of 10MHz net downwards.
Said crystal oscillator 17 and said PHY chip 11 are connected with network data frequency reducing module 21 with phase-locked loop 18 in the said data processing module 1, are used to provide system's reference clock of 25MHz.
Said network data raising frequency module 12 is connected with PHY chip, data mixing module; Be used to receive the 6 parallel-by-bit fan-in network signals of the RGMII 25MHz of PHY chip 11 outputs; And be the 6 parallel-by-bit fan-in network signals of 75MHz with this conversion of signals, the 2.5 parallel-by-bit signals that change the 5 parallel-by-bit network signals (not containing transmission clock) of 75MHz 16 bit data bus of 150-156.25MHz high frequency serial reference clock into again output to data mixing module 16.Please consult Fig. 2 simultaneously, Fig. 2 is that 100,000,000 net 25MHz conversion of signals are the waveform sketch map of 75MHz network signal.As shown in Figure 2; 100,000,000 network 25MHz tranmitting data registers work at RGMII pattern rising edge and trailing edge; 25MHz has shown the clock frequency waveform; 25MHz data has shown 4 states that send the highest frequency serial data " 01010101 ┉ ┉ " of one digit number certificate in the data wire, and its waveform is consistent with the 25MHz clock, only differs the displacement in 1/4 cycle; 75MHz has shown 3 frequency multiplication 75MHz phase shift clocks of 25MHz clock, and promptly the 25MHz clock is in 1 cycle, and 75MHz phase shift clock has corresponding 3 cycles.After sampling to 25MHz data, 75MHz phase shift clock obtains the non-square-wave waveform data of 75MHz data.Wherein, The permission time that the time period that t representes is a 25MHz data rising edge to 75MHz phase shift rising edge clock or 75MHz phase shift rising edge clock to 25MHz data trailing edge; Can adjust to for 3333 nanoseconds synchronously; This size that allows the time is much larger than the requirement of 2 nanoseconds of representative value of network RGMII pattern, so 75MHz data data flow is reliable and stable.
The 6 parallel-by-bit fan-in network signals of the 75MHz that converts to according to the method shown in Fig. 2 waveform; Change the 5 parallel-by-bit network signals of remaining 75MHz that does not contain transmission clock 2.5 parallel-by-bit signals of 16 bit data bus of high frequency serial reference clock into, output to the data mixing module.
Said master data interface 13 is connected with said main data signal generation module 14 in the said data processing module 1, and in the vision signal of transmitting terminal external connection display equipment, this signal can be HDMI, perhaps DVI, perhaps HD-SDI, perhaps SDI digital video; At receiving terminal receiver, video pilot signal or other external equipment signal, for example: ambient temperature, humidity, brightness, smog and voltage monitoring signal etc.The vision signal of external connection display equipment is transferred to main data signal generation module 14 through master data interface 13.
The input of said main data signal generation module 14 is connected with master data interface 13; Output sends modular converter 15 with said master data and is connected; At transmitting terminal is HDMI or DVI or HD-SDI or SDI video decoding chip; To convert 24 RGB parallel video data and 4 digital video control signals into from the external vision signal of master data interface 13 transmission, and be transferred in the master data transmission modular converter 15; At receiving terminal is to the video monitoring signal decoding or to other external equipment signal encoding, and the master data that generates receiving terminal is transferred to master data and sends in the modular converter 15.Wherein, said 4 digital video control signals comprise pixel clock, row signal, field signal and data useful signal.
Said master data is sent modular converter 15 and is adopted fifo structure; It is connected with data mixing module 16 with main data signal generation module 14; In 24 the RGB parallel video data being not more than 75MHz of transmitting terminal (control end) with 14 transmission of main data signal generation module; Totally 27 the parallel video data that conversion of signals is 75MHz that comprise capable signal, field signal and data useful signal; RGB parallel video data shift signal with these 27 75MHz is 13.5 parallel-by-bit vision signals of 16 bit data bus of 150-156.25MHz high frequency serial reference clock again, outputs to data mixing module 16 at last; Then with the master data that comprises video monitoring signal and other external equipment signal of main data signal generation module 14 transmission, 13.5 high-speed parallel passback master datas that convert 16 bit data bus of 150-156.25MHz high frequency serial reference clock into output to data mixing module 16 at receiving terminal (controlled terminal).
Said data mixing module 16 is connected with data transmit-receive module 19; Master data is sent 13.5 parallel-by-bit vision signals of the high frequency serial reference clock that modular converter 15 generates and 2.5 parallel-by-bit signal hybrid codings of network data raising frequency module 12 generations; The mixing transmission signal that generates 16 parallel-by-bits is transferred to data transmit-receive module 19; Wherein, the mixing of said 16 parallel-by-bits transmission signal is made up of 16 continuous even words, strange word high-frequency data frame.
Said data transmit-receive module 19; Preferably by SerDes and optic module combination; Its parallel mixing with 16 transmission of data mixing module is sent signal and is become the high-speed-differential serial signal to output to optic module through 8B/10B (or 16/20B) code conversion; The parallel mixing reception of the 150-156.25MHz signal that will generate from difference mixing reception information via 8B/10B (or 16/20B) decoding of optic module output simultaneously, outputs to signal separation module 20.Wherein, the TLK3101 of the preferred TI of SerDes company perhaps adopts the embedded SerDes of FPGA, perhaps adopts 10,000,000,000 net PHY again.The frequency of high-speed-differential serial signal is 3.125Gpbs or higher.
Please consult Fig. 4 simultaneously; Fig. 4 is 16 high frequency serial reference clock blended data frame coding method sketch mapes; As shown in the figure, 150-156.25MHz high frequency serial reference clock 16 bit data bus that phase-locked loop is produced are divided into even word and strange word, and each adjacent even word constitutes a frame video and mixture of networks data with strange word; Its coding method is: the D0-3 position of even word is red video pixel data R0, R2, R4, R6; The D4-7 position is green video pixel data G0, G2, G4, G6, and the D8-11 position is blue video pixel data B0, B2, B4, B6, and the D12-15 position is video line signal Hs, video data useful signal Dn, network data Txd0 and Txd2; The D0-3 position of strange word is red video pixel data R1, R3, R5, R7; The D4-7 position is green video pixel data G1, G3, G5, G7; The D8-11 position is blue video pixel data B1, B3, B5, B7, and the D12-15 position is video field signal Vs, network data transmit control signal Txctl, network data Txd1 and Txd3.Above-mentioned digital frame structure is except that the clock of video and network signal, and complete whole valid data and the control signal that has comprised video and network is as for the clock signal of video and network signal, by the SerDes and the clock phase-locked loop synchronized generation of receiving terminal.
Wherein, 8 bit data bus that 16 bit data bus can adopt frequency ratio 150-156.25MHz to double, minimum frame of video will be made up of 4 bytes this moment, but still be 32bit.Wherein, it is more high-order that this Frame mixed method can be generalized to RGB from the RGB24 position, and just transmitted frequency is brought up to necessary high frequency and got final product for example 10Gbps transmission.
Said signal separation module 20 is connected with master data receiving processing module 22 with network data frequency reducing module 21; At receiving terminal the parallel mixed signal of the 150-156.25MHz of data transmit-receive module 19 transmission is separated into the reception network signal of 75MHz and the receiving video signals of 75MHz; And will receive network signal and be transferred in the network data frequency reducing module 21, receiving video signals is transferred in the master data receiving processing module 22; At transmitting terminal the parallel mixed signal of the 150-156.25MHz of data transmit-receive module 19 transmission is separated into the 100000000 net backhaul signals of 75MHz and the master data return signal of 75MHz; And with 100,000,000 the net backhaul signals be transferred in the network data frequency reducing module 21, the master data return signal is transferred in the master data receiving processing module 22.
Said network data frequency reducing module 21 is connected with crystal oscillator 17, PHY chip 11 and signal separation module 20, and the 75MHz 100,000,000 net conversion of signals that are used for that signal separation module 20 is told are that 6 100,000,000 nets of the RGMII signal of 25MHz outputs to PHY chip 11.Please consult Fig. 3 simultaneously, Fig. 3 is the waveform sketch map that the 75MHz network signal converts RGMII 25MHz network signal to.As shown in the figure; 75MHz data shows is by the signal separation module 20 isolated non-square-wave waveform of mixed signal that will walk abreast, and is example with " 01010101 ┉ ┉ ", is the basis with the 75MHz clock; The 75MHz clock in per 3 cycles forms the 25MHz clock in corresponding 1 cycle; The 25MHz clock is sampled to 75MHz data again, thereby recovers the standard 25MHz data waveform that meets 100,000,000 network signals, has realized the communication of 100,000,000 networks in view of the above.
Said master data receiving processing module 22 is connected with signal separation module 20; At receiving terminal signal separation module 20 isolated transmitting terminal video datas are carried out format analysis processing; Comprise HDMI or DVI or HD-SDI or SDI or LED display format coding, the generation display data stream outputs to corresponding display equipment and realizes long-range demonstration; Video monitoring signal, monitor signal and other signal that converts signal separation module 20 isolated receiving terminal return signals into required frequency at transmitting terminal outputs to that (not shown) goes on foot processing once in corresponding network device or the miscellaneous equipment.The said network equipment or miscellaneous equipment can be video monitoring demonstration, various signal monitoring module and control answer signal processing module etc.
Based on the above-mentioned video conveyer with function of surfing the Net, the embodiment of the invention is corresponding to provide a kind of method that adopts above-mentioned video conveyer to realize the display device function of surfing the Net, and it comprises:
The first step, send the telecommunication network data to data processing module through the PHY chip by the RJ45 socket;
Second step, convert the 100000000 RGMII network signals of 25MHz into 75MHz RGMII network signal through data processing module; Then 75MHz RGMII network signal is converted into 2.5 high frequency network signals being not less than 150MHz, converts the parallel video signal of 75MHz into be not less than 150MHz 13.5 high-frequency video signals; Again 2.5 high frequency network signals and 13.5 high-frequency video signals are constituted 16 continuous digit pair words, strange digital data frame by certain form hybrid coding; Converting high-speed serial signals to through said data transmit-receive module again sends; Said data processing module is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously; Accomplish both-way communication, thereby the video of realizing far-end shows and function of surfing the Net.
Wherein, the concrete part of data processing module is described in detail at preceding text with the function of each part, is not giving unnecessary details here.
In sum; A kind of video conveyer and its implementation provided by the invention with function of surfing the Net; Send network data to data processing module through RJ45 socket, PHY chip; Data processing module converts 25MHz RGMII network signal into 75MHz RGMII network signal again; Then this 75MHz RGMII network signal is converted into 2.5 high frequency network signals, converts the parallel video signal of 75MHz into 13.5 high-frequency video signals; Then 2.5 high frequency network signals and 13.5 high-frequency video signal hybrid codings are constituted 16 digit pair words, strange word high-frequency data frame, by data transmit-receive module 16 parallel-by-bits are mixed the transmission conversion of signals at last and become the high-speed-differential serial signal to send.Data processing module also comprises decoding, separation and the frequency reducing reverse operating function that the data transceiver module is received data; Need not to lay in addition private network cable like this; Utilize intrinsic video communication link, just can accomplish the two-way simultaneous transmission of video data and network data, just can realize the function of surfing the Net or the Internet video broadcast of video communications system far-end; Improve video control and monitor system performance simultaneously, and significantly reduced the expenditure of cost.
It is understandable that, concerning those of ordinary skills, can be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, and all these changes or replacement all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. video conveyer with function of surfing the Net; Be used to realize the function of surfing the Net of distal displayed equipment; It is characterized in that; Comprise the RJ45 socket, PHY chip, data processing module and the data transmit-receive module that connect successively, crystal oscillator that is connected with PHY chip, data processing module and the master data interface that is connected with data processing module;
Said RJ45 socket connects remote network equipment at receiving terminal, connects the network equipment or Internet network interface at transmitting terminal, is used for the control signal or the transmission telecommunication network data of transmitting and displaying equipment;
Said PHY chip is used for transmitting, receiving network clocking and data;
Said master data interface is used for the vision signal of external connection display equipment at transmitting terminal, at the external video monitoring signal of receiving terminal or other monitor signal;
Said crystal oscillator is used to provide system's reference clock;
Said data transmit-receive module is connected with said data processing module; Be used for that at transmitting terminal signal encoding is sent in the parallel mixing of control end and convert the output of difference serial signal to; Convert the difference serial signal decoding of controlled terminal passback to the parallel reception signal input that mixes; The difference mixed signal decoding that is used for that at receiving terminal transmitting terminal is sent generates the parallel reception signal input that mixes, and signal encoding is sent in the parallel mixing of controlled terminal convert the output of difference serial signal to;
Said data processing module; Be used for converting 100,000,000 RGMII network signals, video input signals into high-frequency 2.5 network signals, 13.5 digital video signals respectively; And continuous 16 digit pair words, the strange digital data frame of hybrid coding formation, sending through data transmit-receive module again, data processing module is carried out decoding, separation and the frequency reducing reverse operating that data transmit-receive module receives data simultaneously; Accomplish duplex signaling, realize that the video of far-end shows and function of surfing the Net.
2. the video conveyer with function of surfing the Net according to claim 1; It is characterized in that said data processing module comprises network data raising frequency module, main data signal generation module, master data transmission modular converter, data mixing module, phase-locked loop, signal separation module, network data frequency reducing module and master data receiving processing module;
Said phase-locked loop is connected with data transmit-receive module with crystal oscillator, network data raising frequency module, master data transmission modular converter, signal separation module, master data receiving processing module, data mixing module; Be used to produce network data raising frequency module, master data transmission modular converter, signal separation module and the required phase shift clock of master data receiving processing module, and produce network data raising frequency module, master data transmission modular converter, data mixing module, data transmit-receive module and the required high frequency serial reference clock of signal separation module;
Said network data raising frequency module is connected with PHY chip, data mixing module; Being used for to be the 6 parallel-by-bit fan-in network signals of 75MHz from the 6 parallel-by-bit fan-in network conversion of signals of the RGMII 25MHz of PHY chip, and the 2.5 parallel-by-bit signals that the 5 parallel-by-bit network signals that will not contain the 75MHz of transmission clock again change 16 bit data bus of 150-156.25MHz high frequency serial reference clock into output to the data mixing module;
Said main data signal generation module sends modular converter with master data interface, master data and is connected; Be used for converting external vision signal into 24 RGB parallel video data and 4 digital video control signals at transmitting terminal and send to master data and send modular converter, then decoding generates the video monitoring image master data and outputs to master data and send modular converter to video monitoring signal at receiving terminal;
Said master data is sent modular converter and is connected with the data mixing module; Be used for 28 RGB parallel video data that are not more than 75MHz at transmitting terminal; Convert the 27 parallel-by-bit video datas of 75MHz into; The 13.5 parallel-by-bit vision signals that change the RGB parallel video signal of 27 75MHz 16 bit data bus of 150-156.25MHz high frequency serial reference clock into again output to the data mixing module, and the 13.5 parallel-by-bits passback master data that the master data that then will comprise video monitoring signal at receiving terminal converts 16 bit data bus of 150-156.25MHz high frequency serial reference clock into outputs to the data mixing module;
Said data mixing module is connected with data transmit-receive module, is used for 13.5 main data signal and 2.5 100,000,000 network signal hybrid codings with high frequency serial reference clock, and the mixing transmission signal that generates 16 parallel-by-bits is transferred to data transmit-receive module;
Said signal separation module is connected with the master data receiving processing module with network data frequency reducing module; Be used for separating into the reception network signal of 75MHz and the receiving video signals of 75MHz at receiving terminal from the parallel mixed signal of the 150-156.25MHz of data transmit-receive module; And will receive network signal and output in the network data frequency reducing module; Receiving video signals is transferred in the master data receiving processing module; To receive Signal Separation from the parallel mixing of data transmit-receive module at transmitting terminal and become the 100000000 net backhaul signals of 75MHz and the master data return signal of 75MHz, output to network data frequency reducing module and master data receiving processing module respectively;
Said network data frequency reducing module is connected with signal separation module with crystal oscillator, PHY chip, and 6 100,000,000 of the RGMII net signal that is used for 100,000,000 net conversion of signals with 75MHz and is 25MHz outputs to the PHY chip, accomplishes the transmitted in both directions of 100,000,000 nets;
Said master data receiving processing module is connected with signal separation module; Be used for the isolated transmitting terminal video data of signal separation module is carried out format analysis processing at receiving terminal; The generation display data stream outputs to corresponding display equipment and realizes long-range demonstration, at transmitting terminal video monitoring signal and the monitor signal that the isolated return signal of signal separation module converts required frequency into is flowed to monitor.
3. the video conveyer with function of surfing the Net according to claim 1 and 2 is characterized in that, said data processing module adopts fpga chip.
4. the video conveyer with function of surfing the Net according to claim 1 and 2 is characterized in that, adopts optical communication or netting twine communication during said data transmit-receive module transceive data.
5. the video conveyer with function of surfing the Net according to claim 1 and 2 is characterized in that, said crystal oscillator produces the reference clock of 25MHz, and is connected with phase-locked loop, network data frequency reducing module in the said data processing module with said PHY chip.
6. the video conveyer with function of surfing the Net according to claim 2; It is characterized in that; Said master data receiving processing module will be in the time will carrying out format analysis processing from the video data of data transmit-receive module; Comprise and handle HDMI, DVI, HD-SDI, SDI or LED display format coding, generate display data stream.
7. the video conveyer with function of surfing the Net according to claim 2 is characterized in that said data transmit-receive module comprises serializer/de-serializers and optic module.
8. the video conveyer with function of surfing the Net according to claim 7 is characterized in that the model of said serializer/de-serializers is TLK3101.
9. the video conveyer with function of surfing the Net according to claim 1 is characterized in that, is integrated with network transformer and LED lamp in the said RJ45 socket.
10. a method that adopts the said video conveyer of claim 1 to realize the display device function of surfing the Net is characterized in that, comprising:
Send the telecommunication network data to data processing module by the RJ45 socket through the PHY chip;
Convert the 100000000 RGMII network signals of 25MHz into 75MHz RGMII network signal through data processing module; Then 75MHz RGMII network signal is converted into 2.5 high frequency network signals being not less than 150MHz, converts the parallel video signal of 75MHz into be not less than 150MHz 13.5 high-frequency video signals; Again 2.5 high frequency network signals and 13.5 high-frequency video signal hybrid codings are constituted 16 continuous digit pair words, strange digital data frame; Converting high-speed serial signals to through said data transmit-receive module again sends; Said data processing module is carried out decoding, separation and the frequency reducing reverse operating that receives data simultaneously; Constitute duplex signaling, thereby the video of realizing far-end shows and function of surfing the Net.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103037222A (en) * | 2012-12-04 | 2013-04-10 | 中国北方车辆研究所 | Compression transmission device and method of parallel digital video signal |
| CN103269422A (en) * | 2013-04-26 | 2013-08-28 | 广州德浩科视电子科技有限公司 | Video signal transmission equipment and video signal transmission method |
| CN108206921A (en) * | 2018-01-12 | 2018-06-26 | 山东超越数控电子股份有限公司 | A kind of HDMI distance transmission systems and its method of work based on FPGA |
| CN109413397A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201576432U (en) * | 2009-12-03 | 2010-09-08 | 康佳集团股份有限公司 | Multi-media display control unit |
| US7822879B2 (en) * | 2008-05-27 | 2010-10-26 | Valens Semiconductor Ltd. | Methods for address assignment |
| CN102025421A (en) * | 2010-11-24 | 2011-04-20 | 天津欧迈通信技术有限公司 | Gigabit broadband isolation pseudo-synchronous digital hierarchical (PDH) optical transmitter and receiver |
| CN102254513A (en) * | 2011-07-14 | 2011-11-23 | 康佳集团股份有限公司 | Multifunctional control system for light-emitting diode (LED) display screen |
-
2012
- 2012-06-12 CN CN201210191335.7A patent/CN102740128B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7822879B2 (en) * | 2008-05-27 | 2010-10-26 | Valens Semiconductor Ltd. | Methods for address assignment |
| CN201576432U (en) * | 2009-12-03 | 2010-09-08 | 康佳集团股份有限公司 | Multi-media display control unit |
| CN102025421A (en) * | 2010-11-24 | 2011-04-20 | 天津欧迈通信技术有限公司 | Gigabit broadband isolation pseudo-synchronous digital hierarchical (PDH) optical transmitter and receiver |
| CN102254513A (en) * | 2011-07-14 | 2011-11-23 | 康佳集团股份有限公司 | Multifunctional control system for light-emitting diode (LED) display screen |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103037222A (en) * | 2012-12-04 | 2013-04-10 | 中国北方车辆研究所 | Compression transmission device and method of parallel digital video signal |
| CN103269422A (en) * | 2013-04-26 | 2013-08-28 | 广州德浩科视电子科技有限公司 | Video signal transmission equipment and video signal transmission method |
| CN108206921A (en) * | 2018-01-12 | 2018-06-26 | 山东超越数控电子股份有限公司 | A kind of HDMI distance transmission systems and its method of work based on FPGA |
| CN109413397A (en) * | 2018-12-05 | 2019-03-01 | 中航光电科技股份有限公司 | A kind of low delay resolution ratio adaptive video optical fiber transmission coding/decoding method |
| CN109413397B (en) * | 2018-12-05 | 2020-09-22 | 中航光电科技股份有限公司 | Low-delay resolution self-adaptive video optical fiber transmission coding and decoding method |
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