The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of video with function of surfing the Net
Conveyer and its implementation, it is unified that network signal, vision signal are entered into row format conversion and frequency by data processing module
Rate converts, and passes through SerDes after blended coded treatment(Parallel series and staticizer)High-speed serial signals output is generated,
Data processing module is simultaneously aobvious so as to realize to receiving data execution inversely decoding, separation and frequency redution operation, complete both-way communication
Show that equipment plays the function of Internet video in the online of distal end or directly.
In order to achieve the above object, this invention takes following technical scheme:
A kind of video transmission device with function of surfing the Net, for realizing the function of surfing the Net of display device, it is included successively
RJ45 sockets, PHY chip, data processing module and the data transmit-receive module of connection, are connected with PHY chip, data processing module
Crystal oscillator and the master data interface that is connected with data processing module;
The RJ45 sockets connect remote network equipment in receiving terminal, and the network equipment or Internet are connected in transmitting terminal
Network interface, for transmitting the control signal or transmission remote network data of display device;
The PHY chip is 100,000,000 net PHY, and for transmitting, receiving network clocking and data, 100,000,000 net PHY can be embedded in
In FPGA;
The master data interface is used for the vision signal of external connection display equipment in transmitting terminal, is used for external video in receiving terminal
Monitoring signal;
The crystal oscillator is used to provide system reference clock;
The data transmit-receive module is connected with the data processing module, is used in transmitting terminal by the parallel mixing of control terminal
Send Signal coding and be converted into differential serial signals output, the differential serial signals decoding of controlled terminal passback is converted into parallel mixed
Reception signal input is closed, in the parallel mixing reception signal of differential serial signals decoding generation that receiving terminal is used to send transmitting terminal
Input, the parallel mixing of controlled terminal is sent into Signal coding and is converted into differential serial signals output;
The data processing module, for 25MHz 100,000,000 RGMII network signals to be converted into 75MHz RGMII networks
Signal, 75MHz RGMII network signals are then converted into 2.5 network signals not less than 150MHz, by the parallel of 75MHz
Vision signal is converted to the 13.5 digital video signals not less than 150MHz, then by 2.5 network signals and 13.5 digital video signals
Hybrid coding forms continuous 16 even words, strange digital data frame, then is converted into high speed serialization by the data transmit-receive module and believes
Number send, the data processing module performs decoding, separation and the frequency reducing reverse operating for receiving data simultaneously, completes two-way
Communication, so as to realize that the video of distal end is shown and function of surfing the Net.
In the described video transmission device with function of surfing the Net, the data processing module includes network data raising frequency mould
Block, main data signal generation module, master data send modular converter, data mixing module, phaselocked loop, signal separation module, net
Network data frequency reducing module and master data receiving processing module;
The phaselocked loop sends modular converter, signal separation module, master with crystal oscillator, network data raising frequency module, master data
Data receiver processing module, data mixing module connect with data transmit-receive module, for producing network data raising frequency module, main number
According to 25MHz, 75MHz phase shifting clock sent needed for modular converter, signal separation module and master data receiving processing module, and
Produce network data raising frequency module, master data sends modular converter, data mixing module, data transmit-receive module and Signal separator mould
The serial reference clock of 150-156.25MHz high frequencies needed for block;
The network data raising frequency module is connected with PHY chip, data mixing module, for by from PHY chip
RGMII 25MHz 6 parallel-by-bits input network signal is converted to 75MHz 6 parallel-by-bits input network signal, then will be free of transmission
The 75MHz of clock 5 parallel-by-bit network signals are changed into the 2.5 parallel-by-bits letter of 16 bit data bus of the serial reference clock of high frequency
Number it is output to data mixing module;
The main data signal generation module sends modular converter and is connected with master data interface, master data, is used in transmitting terminal
In external vision signal being converted into 24 RGB parallel videos data and 4 digital video control signals are sent to master data and sent and turn
Block is changed the mold, generation video monitoring image master data is then decoded to video monitoring signal in receiving terminal is output to master data transmission conversion
Module;
The master data sends modular converter and is connected with data mixing module, is used in transmitting terminal by no more than 75MHz's
28 RGB parallel video data, 75MHz 27 parallel-by-bit video datas are converted to, then 27 parallel-by-bit vision signals are changed into
13.5 parallel-by-bit vision signals of 16 bit data bus of the serial reference clock of 150-156.25MHz high frequencies are output to data mixing
Module, when the master data comprising video monitoring signal is equally converted to the serial benchmark of 150-156.25MHz high frequencies by receiving terminal
The 13.5 parallel-by-bits passback master data of 16 bit data bus of clock is output to data mixing module;
The data mixing module is connected with data transmit-receive module, for by 13.5 main numbers of the serial reference clock of high frequency
It is believed that number with 2.5 100,000,000 network signal hybrid codings, generation 16 parallel-by-bits mixing send signal be transferred to data transmit-receive mould
Block;
The signal separation module is connected with network data frequency reducing module and master data receiving processing module, is used in receiving terminal
In the parallel mixed signals of 150-156.25MHz from data transmit-receive module are separated into 75MHz reception network signal and
75MHz reception vision signal, and be output to network signal is received in network data frequency reducing module, vision signal will be received and passed
In the defeated receiving processing module to master data, the parallel mixing reception signal from data transmit-receive module is separated into transmitting terminal
75MHz 100,000,000 net backhaul signals and 75MHz master data return signal, are respectively outputted to network data frequency reducing module and main number
According to receiving processing module;
The network data frequency reducing module is connected with crystal oscillator, PHY chip and signal separation module, for by the hundred of 75MHz
Million net signals are converted to 25MHz 6 100,000,000 net signal outputs of RGMII to PHY chip, complete 100,000,000 transmitted in both directions netted;
The master data receiving processing module is connected with signal separation module, is used for signal separation module in future in receiving terminal
The transmitting terminal video data isolated carries out format analysis processing, and generation display data stream is output to corresponding display device and realized remotely
It has been shown that, video monitoring signal and the monitoring of required frequency are converted in the return signal that transmitting terminal isolates signal separation module
Signal is conveyed to monitor or other relevant equipment.
In the described video transmission device with function of surfing the Net, the data processing module is preferably real using fpga chip
It is existing.
In the described video transmission device with function of surfing the Net, the data transmit-receive module transceiving data uses optic communication
Or netting twine communication.
In the described video transmission device with function of surfing the Net, the crystal oscillator produces 25MHz reference clock, and with institute
PHY chip is stated to connect with the phaselocked loop in the data processing module, network data frequency reducing module.
In the described video transmission device with function of surfing the Net, the master data receiving processing module will come from data
When the video data of transceiver module carries out format analysis processing, including processing HDMI, DVI, HD-SDI, SDI or LED display format are compiled
Code, generate display data stream.
In the described video transmission device with function of surfing the Net, the data transmit-receive module includes serializer/de-serializers
And optic module.
In the described video transmission device with function of surfing the Net, the preferred model of the serializer/de-serializers
TLK3101。
In the described video transmission device with function of surfing the Net, be integrated with the RJ45 sockets network transformer and
LED.
A kind of method that display device function of surfing the Net is realized using above-mentioned video transmission device, it includes:
Data processing module to is sent remote network data by PHY chip by RJ45 sockets;
25MHz 100,000,000 RGMII network signals are converted to by 75MHz RGMII network signals by data processing module,
Then 75MHz RGMII network signals are converted into 2.5 network signals, the parallel video by 75MHz not less than 150MHz
Signal is converted to the 13.5 digital video signals not less than 150MHz, then 2.5 network signals are mixed with 13.5 digital video signals
Coding forms continuous 16 even words, strange digital data frame, and high-speed serial signals are converted into finally by the data transmit-receive module
A distant place is sent to, data processing module performs decoding, separation and the frequency reducing reverse operating for receiving data simultaneously, and it is logical to form duplex
News, so as to realize that the video of distal end is shown and function of surfing the Net.
Compared to prior art, a kind of video transmission device and its realization side with function of surfing the Net provided by the invention
Method, employ data processing module and 100,000,000 RGMII network signals, video input signals are respectively converted into high-frequency 2.5
Network signal, 13.5 digital video signals, and by being sent again by SerDes after certain form hybrid coding, data processing module
Decoding, separation and the frequency reducing reverse operating for receiving data are performed simultaneously.A kind of video with function of surfing the Net provided by the invention
Conveyer and its implementation, using existing video Transfer pipe, without laying private network cable in addition, it can be achieved with distal end
Display device, the Internet video of the network equipment plays or function of surfing the Net, enhances the performance of video display control or monitoring system,
Reduce the expenditure of cost.
Embodiment
The present invention provides a kind of video transmission device and its implementation with function of surfing the Net, to make the mesh of the present invention
, technical scheme and effect it is clearer, clear and definite, the present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.
It should be appreciated that specific embodiment described herein is not intended to limit the present invention only to explain the present invention.
Referring to Fig. 1, it is the structured flowchart of the video transmission device provided by the invention with function of surfing the Net.As schemed
Show, it includes RJ45 sockets 10, PHY chip 11, data processing module 1 and the data transmit-receive module 19 being sequentially connected, with PHY cores
Piece 11, the crystal oscillator 17 that data processing module 1 connects and the master data interface 13 being connected with data processing module 1.
The RJ45 sockets 10 are connected with the data processing module 1, and it is internal including network transformer and LED instructions
Lamp, in receiving terminal(Do not indicated in figure)It is connected with remote external equipment for surfing the net, in transmitting terminal(Do not indicated in figure)With the network equipment
(Such as main control computer network interface or other Internet network interfaces)Connection, control signal and transmission for display device
Remote network data, for example, display device can be transmitted when RJ45 sockets connect main control computer network interface(It is such as liquid crystal-spliced
Wall or LED display)Control signal, when connecting Internet network interface, can be achieved remote network devices online.
The PHY chip 11 is 100,000,000 net PHY, is connected, is used for the RJ45 sockets 10, the data processing module 1
Transmission, network clocking and data are received, 100,000,000 net PHY can be embedded in FPGA.
The master data interface 13 is connected with the data processing module 1, is used for regarding for external connection display equipment in transmitting terminal
Frequency signal, it is used for external video monitoring signal in receiving terminal.
The crystal oscillator 17 is connected with the PHY chip 11, the data processing module 1, for providing system reference clock.
The data processing module 1 includes network data raising frequency module 12, main data signal generation module 14, master data hair
Send modular converter 15, data mixing module 16, phaselocked loop 18, signal separation module 20, network data frequency reducing module 21 and main number
According to receiving processing module 22;It is used to 25MHz RGMII network signals being converted to 75MHz RGMII network signals, then will
75MHz RGMII network signals are converted to 2.5 high frequency network signals not less than 150MHz, the parallel video letter by 75MHz
13.5 high-frequency video signals not less than 150MHz number are converted to, then 2.5 network signals and 13.5 digital video signals are pressed
Certain form hybrid coding forms continuous 16 even words, strange digital data frame, then is changed by the data transmit-receive module 19
Sent into high-speed serial signals, decoding, separation and the frequency reducing that the data processing module 1 performs reception data simultaneously are reverse
Operation, the transmitted in both directions of video data, control data and network data is realized, so as to realize that the video of distal end shows and surfed the Net work(
Energy.
In the present embodiment, the data processing module 1 is preferably realized using programmable fpga chip on a large scale.
In the data processing module 1, the phaselocked loop 18 is PLL phaselocked loops, itself and crystal oscillator 17, network data raising frequency mould
Block 12, master data send modular converter 15, signal separation module 20, master data receiving processing module 22, data mixing module 16
Connected with the data transmit-receive module 19 beyond data processing module 1, the phaselocked loop 18 is using 25MHz system reference clock to be defeated
Enter, the various frequency multiplication phase shifting clocks needed for generation system, including produce the network data raising frequency module 12, master data transmission turn
Change the mold 25MHz, 75MHz phase shifting clock needed for block 15, signal separation module 20 and master data receiving processing module 22, and production
The raw network data raising frequency module 12, master data send modular converter 15, data mixing module 16, the and of signal separation module 20
The serial reference clock of 150-156.25MHz high frequencies needed for data transmit-receive module 19 beyond data processing module 1.
The data transmit-receive module 19 and the data mixing module 16 in the data processing module 1, signal separation module
20 and phaselocked loop 18 connect, in transmitting terminal(Control terminal)For the parallel mixing from control end data mixing module 16 to be sent
Signal coding is converted into differential serial signals output, and the differential serial signals decoding of controlled terminal passback is converted into parallel mixing connects
The collection of letters number inputs to local signal separation module 20, in receiving terminal(Controlled terminal)For the differential serial signals for sending transmitting terminal
The parallel mixing reception signal of decoding generation inputs to local signal separation module 20, by from controlled terminal data mixing module 16
Parallel mixing sends Signal coding and is converted into differential serial signals output.Wherein, the communication mode of data transmit-receive module 19 can be with
Using optic communication, high speed netting twine communication pattern can also be used, application model is expanded into family.
Please continue to refer to Fig. 1, in the specific implementation, the PHY chip 11 uses 100,000,000 net PHY chips, output with it is described
Network data raising frequency module 12 in data processing module 1 is connected, and input is connected with network data frequency reducing module 21, for transmitting
Network clocking and data;The RGMII patterns of the interface modes of PHY chip 11 preferably 12 BITBUS networks, including transmission clock TX_CLK,
Data TXD [3..0] is sent, control TX_CTL is sent and receives clock RX_CLK, receive data RXD [3..0], receive control
RX_CTL, 100,000,000 net PHY chips support downwards 10MHz net transmission.
Phaselocked loop 18 and network data of the crystal oscillator 17 with the PHY chip 11 and in the data processing module 1 drop
Frequency module 21 connects, for providing 25MHz system reference clock.
The network data raising frequency module 12 is connected with PHY chip, data mixing module, defeated for receiving PHY chip 11
The RGMII 25MHz gone out 6 parallel-by-bits input network signal, and convert the signal into 75MHz 6 parallel-by-bits input network letter
Number, then the 5 parallel-by-bit network signals by 75MHz(Without transmission clock)When being changed into the serial benchmark of 150-156.25MHz high frequencies
2.5 parallel-by-bit signal outputs of 16 bit data bus of clock are to data mixing module 16.Please refer to Fig. 2, Fig. 2 is 100,000,000 nets
25MHz signals are converted to the waveform diagram of 75MHz network signals.As shown in Fig. 2 100,000,000 network 25MHz tranmitting data registers exist
RGMII patterns rising edge and trailing edge work, and 25MHz shows clock frequency waveform, and 25MHz data show 4 transmissions
In data wire a data highest frequency serial data " 01010101 ┉ ┉ " state, its waveform is consistent with 25MHz clocks,
Only differ the displacement in 1/4 cycle;75MHz shows 3 frequency multiplication 75MHz phase shifting clocks of 25MHz clocks, i.e. 1,25MHz clocks
In cycle, 75MHz phase shifting clocks have 3 corresponding cycles.75MHz phase shifting clocks obtain after being sampled to 25MHz data
75MHz data non-square-wave waveform data.Wherein, the period that t is represented is 25MHz data rising edges to during 75MHz phase shifts
Clock rising edge or 75MHz phase shifting clocks rising edge to 25MHz data trailing edges the permission time, can synchronous adjustment received to 3333
Second, this allows the size of time much larger than the requirement of the nanosecond of network RGMII patterns representative value 2, therefore 75MHz data data
Stream is reliable and stable.
According to the method migration shown in Fig. 2 waveforms into 75MHz 6 parallel-by-bits input network signal, will be free of transmission when
Remaining 75MHz of clock 5 parallel-by-bit network signals are changed into 2.5 of 16 bit data bus of the serial reference clock of high frequency simultaneously
Row signal, it is output to data mixing module.
The master data interface 13 is connected with the main data signal generation module 14 in the data processing module 1,
In the vision signal of transmitting terminal external connection display equipment, the signal can be HDMI, either DVI or HD-SDI, or SDI numbers
Word video;Video monitoring signal or other external equipment signals are received in receiving terminal, such as:Environment temperature, humidity, brightness, cigarette
Mist and voltage monitoring signal etc..The vision signal of external connection display equipment is transferred to main data signal by master data interface 13 and generated
Module 14.
The input of the main data signal generation module 14 is connected with master data interface 13, output end and the master data
Send modular converter 15 to connect, be HDMI or DVI or HD-SDI or SDI video decoding chips in transmitting terminal, will be connect from master data
The external vision signals of the transmission of mouth 13 are converted to 24 RGB parallel videos data and 4 digital video control signals, and are transferred to main number
According in transmission modular converter 15;It is video monitoring signal to be decoded or to other external equipment Signal codings, generation in receiving terminal
The master data transfer of receiving terminal is sent in modular converter 15 to master data.Wherein, when the 4 digital video control signal includes pixel
Clock, row signal, field signal and data valid signal.
The master data sends modular converter 15 and uses fifo structure, and it is mixed with main data signal generation module 14 and data
Matched moulds block 16 connects, in transmitting terminal(Control terminal)24 RGB no more than 75MHz that main data signal generation module 14 is transmitted
Parallel video data, totally 27 signals including row signal, field signal and data valid signal are converted to the parallel of 75MHz
Video data, then by the RGB parallel videos data shift signal of 27 75MHz be the serial benchmark of 150-156.25MHz high frequencies
13.5 parallel-by-bit vision signals of 16 bit data bus of clock, are finally output to data mixing module 16;In receiving terminal(It is controlled
End)The master data comprising video monitoring signal and other external equipment signals that then main data signal generation module 14 is transmitted,
The 13.5 high-speed parallels passback master data for being converted to 16 bit data bus of the serial reference clock of 150-156.25MHz high frequencies is defeated
Go out to data mixing module 16.
The data mixing module 16 is connected with data transmit-receive module 19, the height that master data transmission modular converter 15 is generated
13.5 parallel-by-bit vision signals of the serial reference clock of frequency mix with the 2.5 parallel-by-bit signals that network data raising frequency module 12 generates
Coding, the mixing of 16 parallel-by-bits of generation send signal and are transferred to data transmit-receive module 19, wherein, the mixing hair of 16 parallel-by-bit
The number of delivering letters is made up of 16 continuous even words, strange word high-frequency data frames.
The data transmit-receive module 19, is preferably combined by SerDes with optic module, and it transmits data mixing module 16
Parallel mixing send signal pass through 8B/10B(Or 16/20B)Code conversion is into high-speed differential serial signal output to optical fiber mode
Block, meanwhile, the difference exported from optic module is mixed into receive information and passes through 8B/10B(Or 16/20B)Decoding generation
150-156.25MHz mixes reception signal and is output to signal separation module 20 parallel.Wherein, SerDes preferred TI companies
TLK3101, or the SerDes embedded using FPGA, then or using 10,000,000,000 net PHY.The frequency of high-speed differential serial signal is
It is 3.125Gpbs or higher.
Please refer to Fig. 4, Fig. 4 is the serial reference clock blended data frame coding method schematic diagram of 16 high frequencies, is such as schemed
It is shown, the serial bit data bus of reference clock 16 of 150-156.25MHz high frequencies caused by phaselocked loop is divided into even word and strange word,
Each adjacent even word and strange word form a frame video and mixture of networks data, its coding method are:The D0-3 positions of even word are red
Color video pixel data R0, R2, R4, R6, D4-7 positions are green video pixel data G0, G2, G4, G6, and D8-11 positions are that blueness regards
Frequency pixel data B0, B2, B4, B6, D12-15 positions are video line signal Hs, video data useful signal Dn, network data Txd0
And Txd2;The D0-3 positions of strange word are red video pixel data R1, R3, R5, R7, D4-7 positions be green video pixel data G1,
G3, G5, G7, D8-11 positions are blue video pixel data B1, B3, B5, B7, and D12-15 positions are video field signal Vs, network data
Send control signal Txctl, network data Txd1 and Txd3.Above-mentioned digital frame structure in addition to the clock of video and network signal,
The complete whole valid data and control signal for including video and network, as the clock signal of video and network signal, by
The SerDes and clock phase-locked loop of receiving terminal are synchronously produced.
Wherein, 16 bit data bus can use frequency than 8 bit data bus that 150-156.25MHz doubles, now
Minimum frame of video will be made up of 4 bytes, but still be 32bit.Wherein, the data frame mixed method can be generalized to from RGB24 positions
RGB is more high-order, simply transmits frequency and brings up to necessary high frequency, such as 10Gbps transmission.
The signal separation module 20 is connected with network data frequency reducing module 21 and master data receiving processing module 22, is being connect
The parallel mixed signals of 150-156.25MHz that receiving end transmits data transmit-receive module 19 are separated into 75MHz reception network signal
With 75MHz reception vision signal, and by receive network signal be transferred in network data frequency reducing module 21, by receive video letter
Number it is transferred in master data receiving processing module 22;In the 150-156.25MHz that transmitting terminal transmits data transmit-receive module 19 simultaneously
Row mixed signal is separated into 75MHz 100,000,000 net backhaul signals and 75MHz master data return signal, and 100,000,000 net loopbacks are believed
Number it is transferred in network data frequency reducing module 21, master data return signal is transferred in master data receiving processing module 22.
The network data frequency reducing module 21 is connected with crystal oscillator 17, PHY chip 11 and signal separation module 20, for that will believe
The net signals of 75MHz 100,000,000 that number separation module 20 separates are converted to 25MHz 6 100,000,000 net signal outputs of RGMII to PHY cores
Piece 11.Please refer to Fig. 3, Fig. 3 is the waveform diagram that 75MHz network signals are converted into RGMII 25MHz network signals.Such as
Shown in figure, the non-square-wave waveform for being isolated parallel mixed signal by signal separation module 20 is shown in 75MHz data, with
" exemplified by 01010101 ┉ ┉ ", based on 75MHz clocks, the 75MHz clocks in every 3 cycles form 1 corresponding cycle
25MHz clocks, 25MHz clocks again to 75MHz data sample, so as to recover the standard 25MHz for meeting 100,000,000 network signals
Data waveforms, the communication of 100,000,000 networks is realized accordingly.
The master data receiving processing module 22 is connected with signal separation module 20, in receiving terminal by signal separation module 20
The transmitting terminal video data isolated carries out format analysis processing, including HDMI or DVI or HD-SDI or SDI or LED display formats are compiled
Code, generation display data stream are output to corresponding display device and realize long-range display;Signal separation module 20 is divided in transmitting terminal
Video monitoring signal, monitoring signals and the other signals that the receiving terminal return signal separated out is converted to required frequency are output to accordingly
The network equipment or miscellaneous equipment in(Not shown in figure)Carry out step processing.The network equipment or miscellaneous equipment can be
Video monitoring is shown, various signal monitoring modules and control answer signal processing module etc..
Based on the above-mentioned video transmission device with function of surfing the Net, the embodiment of the present invention accordingly provides a kind of using above-mentioned
The method that video transmission device realizes display device function of surfing the Net, it includes:
The first step, by RJ45 sockets data processing module to is sent remote network data by PHY chip;
Second step, 25MHz 100,000,000 RGMII network signals are converted to by 75MHz RGMII nets by data processing module
Network signal, 75MHz RGMII network signals are then converted into 2.5 high frequency network signals not less than 150MHz, by 75MHz
Parallel video signal be converted to 13.5 high-frequency video signals not less than 150MHz, then by 2.5 high frequency network signals with
13.5 high-frequency video signals form continuous 16 even words, strange digital data frame by certain form hybrid coding, then pass through institute
State data transmit-receive module and be converted into high-speed serial signals and send, the data processing module performs the solution for receiving data simultaneously
Code, separation and frequency reducing reverse operating, complete both-way communication, so as to realize that the video of distal end is shown and function of surfing the Net.
Wherein, the function of the concrete composition part of data processing module and each part has been carried out retouching in detail above
State, do not repeating herein.
In summary, a kind of video transmission device and its implementation with function of surfing the Net provided by the invention, pass through
RJ45 sockets, PHY chip send network data to data processing module, and data processing module is again by 25MHz RGMII networks
Signal is converted to 75MHz RGMII network signals, and the 75MHz RGMII network signals then are converted into 2.5 high frequency networks
Signal, 75MHz parallel video signal is converted to 13.5 high-frequency video signals, then by 2.5 high frequency network signals with
13.5 high-frequency video signal hybrid codings form 16 even words, strange word high-frequency data frame, finally by data transmit-receive module by 16
Parallel-by-bit mixing transmission signal is converted into high-speed differential serial signal and sent.Data processing module is also included to data transmit-receive
Module receives decoding, separation and the frequency reducing reverse operating function of data, so private network cable need not be laid in addition, using intrinsic
Video communication link, so that it may complete video data and the duplex simultaneous transmission of network data, it is remote to can be achieved with video communications system
The function of surfing the Net or Internet video at end play, while improve the performance of video control and monitoring system, and greatly reduce
The expenditure of cost.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and its hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.