CN104917988A - V-BY-ONE interface high-speed image acquisition card - Google Patents

Abstract

The invention relates to a V-BY-ONE interface high-speed image acquisition card. A V-BY-ONE signal of a board to be detected on a liquid crystal television production line is acquired in real time and converted into a BMP image, under the control of a reading-writing control module, the BMP image is transmitted to a computer for caching through a DDR2 bus, and the cached content is read through software for acquiring V-BY-ONE image data displayed on a liquid crystal screen and converting the V-BY-ONE image data into the BMP image, thereby realizing automatic measurement and control use. The V-BY-ONE interface high-speed image acquisition card can be widely applied to the industrial liquid crystal television production line, replaces a traditional detection technology of manually detecting images with a method of acquiring contrast images through the computer, greatly improves efficiency, and reduces labor cost.

Description

V-by-One interface high speed image acquisition board

Technical field

The present invention relates to the video signal collective technology in LCD TV field, be specifically related to the V-by-One signals collecting of a kind of just liquid crystal television mainboard or the output of liquid crystal display mainboard and convert data bitmap to and by PCIE X4 interface, picture number pick be uploaded to the video image acquisition device of computer for analyzing and processing.

Background technology

Along with the progress of science and technology, the development in epoch, the arrival of digital times, digitlization LCD TV spreads to huge numbers of families, and the output of LCD TV is also in a kind of geometric explosive growth of this few year's harvest.

The raising of output certainly will require that production firm constantly expands the scale of production, enhance productivity, increase labour to drop into, especially in recent years, domestic labor cost increased year by year fast, so also certainly will bring the increase greatly of production cost, and existing digital lcd TV commercially, brand is various, feature richness, dog-eat-dog, forces down price all one after another to exchange larger market between each manufacturer.The reduction of price and the growth of production cost, just bring great contradiction, therefore needing a kind of method can enhance productivity, and reduces labour and drops into, reduce production cost.

In addition conventional television is produced the detection before dispatching from the factory and is adopted artificial naked eyes identification, due to the sense of responsibility of each employee, and discrimination standard all exists very big-difference, therefore there is very large subjectivity and fluctuation in testing result, and the standardization for product quality forms very large obstacle.

Therefore, be badly in need of a kind of LCD TV automatic test equipment of high efficient and reliable, solve this contradiction, in order to reduce labour cost, raise labour efficiency.And the key of LCD TV automatic test equipment is, gathers V-BY-ONE signal and convert picture signal to and be supplied to Computer Analysis.Have not yet to see in order to realize V-BY-ONE being gathered and converting the equipment of BMP bitmap transmissions to computer to.

Summary of the invention

The present invention aims to provide a kind of V-BY-ONE picture signal Collect conversion device, in order to realize will being presented at the V-BY-ONE image data acquiring in LCD screen and converting BMP image transmitting to industrial computer, uses for realizing automatic measure control.

To achieve these goals, basic ideas of the present invention are: by the V-BY-ONE signal collected, be stored in FIFO, and when being filled with a frame, data are sent on computer PCI bus by sending engine by triggered interrupts.Its technical scheme adopted is:

It is a kind of for the picture signal collection of the V-BY-ONE signaling interface on liquid crystal display television core board is changed into the device of BMP picture uploading to computer, this image collecting device comprises: V-BY-ONE signal acquisition module, and the input of described V-BY-ONE acquisition module is provided with V-BY-ONE differential signal input mouth; Described V-BY-ONE differential signal input mouth is connected on described V-BY-ONE signaling interface; The output of described V-BY-ONE signal acquisition module is provided with a video data transmission port; Described video data transmission port is connected on one end of DDR2 reading-writing port, data cell fifo is connected with at the other end of described DDR2 reading-writing port, the other end of described data cell fifo is connected on the input of PCIE data sending engine, the output of described PCIE data sending engine is connected on computer PCI E X4 interface, described data cell fifo, under the control in DDR2SDRAM Read-write Catrol module, is sent data in computer PCI E bus by described PCIE data sending engine.Data are written in calculator memory with BMP form by described PCIE bus, and the BMP image in described calculator memory is employed program and reads and process.

Tool of the present invention has the following advantages:

1, PCIe4X interface, message transmission rate 2000MB/s;

2, JEIDA, VESA form is supported, 8Bit (4 pairs of data wires), 10Bit (5 pairs of data wires) data bit are dark, the V-BY-ONE signals collecting of single group, two groups, four groups (maximum 24 pairs of data wires, 4 pairs of clock lines) data formats; Support 3840*2160, the V-BY-ONE video image acquisition of the highest support 120Hz frame frequency; Support the V-BY-ONE video image acquisition of 1366*768, frame frequency 60Hz;

3, support the collection of 3D four-way (four groups) road the highest 120Hz V-BY-ONE video image, support polarization type 3D and shutter 3D, and according to 3D synchronizing signal, right and left eyes is separately stored;

There is field frequency (VFQ), total line number (VTT), effectively line number (VDE), row total pixel number (HTT), row valid pixel (HDE) isoparametric test function;

4, under 3840*2160,120Hz frame frequency, continuous acquisition 16 two field pictures can be uploaded; The highest support 3840*2160 form, under 120Hz frame frequency (non-3D pattern), continuous acquisition uploads 16 two field pictures.

Accompanying drawing explanation

Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a application's part, does not form and not only limit of the present invention, in the accompanying drawings:

Fig. 1 is structure chart of the present invention.

Fig. 2 is optimum configurations flow chart of the present invention.

Fig. 3 is data acquisition flow figure of the present invention.

Fig. 4 is transfer of data flow process figure of the present invention.

Embodiment

Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Shown in Figure 1, the novel V-BY-ONE picture signal Collect conversion device that the present invention proposes, comprise V-BY-ONE signal acquisition module, DDR2 SDRAM Read-write Catrol module, data FIFO, system control register, PCIE data sending engine, PCIE data receiver engine and PCIE data DMA transmission engine, V-BY-ONE acquisition module adopts the SerDes of FPGA to unstring module, the view data of 7:1 V-BY-ONE bus is converted to parallel data, be saved in DDR2SDRAM, DDR2 SDRAM Read-write Catrol module is divided into read port and write port.The data of the CMOS macro cell that unstrings are carried out buffer memory by write port, are written in outside DDR2, read port reads data from outside DDR2, for PCIe port transmission to calculator memory, data FIFO is used for the transfer of data of synchronous friction speed intermodule, system control register controls the operating state of each module, comprise the signal format to V-BY-ONE acquisition module, start and stop controlling, to the read/write address of DDR2 SDRAM Read-write Catrol module, data length etc., stop controlling to the startup of PCIE data DMA transmission engine, the control etc. of the calculator memory address be written into, PCIe data receiver engine accepts is from the control command of computer, and carry out action by command request, result is sent to computer by PCIe data sending engine, PCIE data DMA transmission engine completes the transmission of big data quantity, the data of outside DDR2 internal memory are read out by DDR2SDRAM read port, the internal memory of computer is written to by PCIe bus.

Shown in Figure 2, the optimum configurations flow process of this novel V-BY-ONE picture signal Collect conversion device.In system non-reset state and PCIe bus link is normal time, accept the control command of engine accepts from computer, and by parameter read-in to control register.

Shown in Figure 3, describe the data acquisition flow of this novel V-BY-ONE picture signal Collect conversion device.Gather after the collection start bit in system control register is set to and start.In the buffer circle of the DDR2SDRAM that the data collected store by system, after the slow frame of data, progressively increase in the address of buffer circle, and data write next buffer circle, and each buffer circle stores the data of a frame.

Shown in Figure 4, illustrate the flow process that this novel V-BY-ONE picture signal Collect conversion device writes data into calculator memory.Data upload adopts dma mode to carry out, and seldom take the cpu resource of computer, transmission speed is fast.First computer carries out Memory Allocation, the memory address write capture card control register then will be assigned to; Simultaneous computer reads the address of current buffer, calculates the address of the buffer circle needing the image place be read, and address is written to the control register of capture card; Then computer starts DMA transmission by sending out control command to capture card; Capture card reads data and is written in the internal memory of computer from DDR2SDRAM, until complete.

Claims (3)

1.V-by-One interface high speed image acquisition board, is characterized in that:

Described V-BY-ONE signal acquisition module, DDR2SDRAM Read-write Catrol module, data FIFO, system control register, PCIE data sending engine, PCIE data receiver engine and PCIE data DMA transmission engine, the input of described V-BY-ONE acquisition module is provided with V-BY-ONE differential signal input mouth; Described V-BY-ONE differential signal input mouth is connected on described V-BY-ONE signaling interface; The output of described V-BY-ONE signal acquisition module is provided with a video data transmission port; Described video data transmission port is connected on one end of DDR2 reading-writing port, data cell fifo is connected with at the other end of described DDR2 reading-writing port, the other end of described data cell fifo is connected on the input of PCIE data sending engine, the output of described PCIE data sending engine is connected on computer PCI E X4 interface, described data cell fifo, under the control in DDR2SDRAM Read-write Catrol module, is sent data in computer PCI E bus by described PCIE data sending engine.Data are written in calculator memory with BMP form by described PCIE bus, and the BMP image in described calculator memory is employed program and reads and process.

2. V-BY-ONE image collecting device according to claim 1, is characterized in that: V-BY-ONE acquisition module adopts the SerDes of FPGA to unstring module.

3. V-BY-ONE image collecting device according to claim 1, is characterized in that:

1) interface definition is: PCIe4X interface, message transmission rate 2000MB/s.

2) support that V-BY-ONE form has:

A JEIDA form;

B VESA form.

3) support that V-BY-ONE signals collecting data bit has deeply:

A8Bit (4 pairs of data wires);

B10Bit (5 pairs of data wires);

4) support that display mode has:

A3840*2160, the V-BY-ONE video image acquisition of the highest support 120Hz frame frequency;

B1920*1080, the V-BY-ONE video image acquisition of the highest support 120Hz frame frequency;

C supports 1366*768, the V-BY-ONE video image acquisition of frame frequency 60Hz;

D supports the collection of 3D four-way (four groups) road the highest 120Hz V-BY-ONE video image;

E supports polarization type 3D and shutter 3D, and is separately stored by right and left eyes according to 3D synchronizing signal.

5) support function has:

A whole figure collecting test function;

B3D frame interlocks, line interlacing synchronism detection function;

C has field frequency (VFQ) test function;

The total line number of d (VTT) test function;

The effective line number of e (VDE) test function;

The capable total pixel number of f (HTT) test function;

The capable valid pixel of g (HDE) test function.

6) performance index are:

A continuous acquisition under 3840*2160,120Hz frame frequency uploads 16 two field pictures;

B the highest support 3840*2160 form, under 120Hz frame frequency (non-3D pattern), continuous acquisition uploads 16 two field pictures.