CN206865570U - Video processor - Google Patents
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- CN206865570U CN206865570U CN201720582840.2U CN201720582840U CN206865570U CN 206865570 U CN206865570 U CN 206865570U CN 201720582840 U CN201720582840 U CN 201720582840U CN 206865570 U CN206865570 U CN 206865570U
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Abstract
The utility model embodiment discloses a kind of video processor, including multi-channel video input interface, the first PLD, video-frequency signal converter, the second PLD, multi-channel video output interface, microcontroller and clock generator.The utility model embodiment can support multichannel input and the multiple-channel output of vision signal.
Description
Technical field
It the utility model is related to technical field of video processing, more particularly to a kind of video processor.
Background technology
As the improvement of people's living standards, various media informations are mostly with the picture of fineness and abundant video information
Facility is provided for user.Under such demand, increasing interactive information occupies substantial amounts of display picture space
More convenient information resources are provided.But as the change of the physical size of display is big, the limit that desktop is shown also is challenged
The visual experience of people.Have multi input, the video processor of multi output significant therefore, design is a kind of.
Utility model content
Embodiment of the present utility model provides a kind of video processor, and the input of vision signal multichannel and multichannel are supported to realize
The technique effect of output.
On the one hand, there is provided a kind of video processor, including：Multi-channel video input interface, the first PLD,
Video-frequency signal converter, the second PLD, multi-channel video output interface, microcontroller and clock generator；It is described
Multi-channel video input interface is connected to the multichannel of first PLD by respective signaling conversion circuit respectively
The parallel input interface of TTL signal, the video-frequency signal converter connect the multichannel TTL signal of first PLD
The multichannel LVDS signal input interfaces of parallel output interface and second PLD, the multi-channel video output connect
Mouth connects the output of second PLD, first PLD and second FPGA
Device connects the clock generator, and the microcontroller connects first PLD, the vision signal turns
Parallel operation and second PLD.
In one embodiment of the present utility model, the multi-channel video input interface includes SDI interfaces；At the video
Reason device includes cable balanced device, cable drive and SDI ring outgoing interfaces；The cable balanced device be connected to the SDI interfaces and
Between the signaling conversion circuit being connected with the SDI, the line driver be connected to the SDI rings outgoing interface and with institute
State between the connected signaling conversion circuit of SDI interfaces.
In one embodiment of the present utility model, the multi-channel video input interface includes digital visual interface；It is described
Video processor includes digital video ring outgoing interface, and the digital video ring outgoing interface is connected to and the digital visual interface
The connected signaling conversion circuit, the digital visual interface are selected from DVI interface and/or SDI interfaces.
In one embodiment of the present utility model, the video processor also includes：At least first input subcard all the way
Spare interface, it is connected to described first by signaling conversion circuit per the first input subcard spare interface all the way and programmable patrols
Collect the parallel input interface of TTL signal all the way of device.
In one embodiment of the present utility model, the video processor also includes：At least second input subcard all the way
Spare interface, it is the parallel input interface of TTL signal per the second input subcard spare interface all the way and is connected to described first
The parallel input interface of TTL signal all the way of PLD.
In one embodiment of the present utility model, the video processor also includes：Genlock signal input interface,
Signal extracting circuit and genlock hoop outgoing interface；The signal extracting circuit is connected to the genlock signal input
Between interface and second PLD, the genlock hoop outgoing interface connects the genlock signal
Node between input interface and the signal extracting circuit.
In one embodiment of the present utility model, the video processor also includes：Video premonitoring spare interface all the way
And the video encoder being connected between first PLD and the video premonitoring spare interface；Described second
PLD connects first PLD by 8 input/output expansion interfaces.
In one embodiment of the present utility model, the multi-channel video output interface connects second FPGA
The TTL signal parallel output interface and serializer/de-serializers interface of device.
In one embodiment of the present utility model, the multi-channel video output interface includes：Single channel DVI interface and double
Passage DVI interface, the two-way TTL signal parallel output interface of second PLD is connected respectively.
In one embodiment of the present utility model, the multi-channel video output interface includes：DP interfaces and SDI interfaces,
The serializer/de-serializers interface of second PLD is connected respectively.
In one embodiment of the present utility model, the video processor also includes：At least output subcard is reserved all the way
Interface, it is parallel per the TTL signal all the way that the output subcard spare interface is connected to second PLD all the way
Output interface or all the way LVDS signal output interfaces.
In one embodiment of the present utility model, the video processor also includes：Network interface, USB interface and liquid crystal display
Interface, the network interface connect the microcontroller by PHY chip, described in the USB interface connects with the LCD Interface
Microcontroller.
Above-mentioned technical proposal has the following advantages that or beneficial effect：With PLD and video-frequency signal converter
For core, synchronously preferably being handled for vision signal is may be such that using the interior synchronous mode of video-frequency signal converter, and
Multichannel is set to input multichannel input and the multiple-channel output that can support vision signal with output interface.
Brief description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme of the utility model embodiment
The accompanying drawing used is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present utility model
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the structural representation of the video processor in the utility model first embodiment；
Fig. 2 is the structural representation of the video processor in the utility model second embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belong to the scope of the utility model protection.
First embodiment
As shown in figure 1, a kind of video processor 10 provided in the utility model first embodiment, including：Multi-channel video
Input interface 11, PLD 12, video-frequency signal converter 13, PLD 14, multi-channel video output connect
Mouth 15, microcontroller 16 and clock generator 17.
Multi-channel video input interface 11 is, for example, digital visual interface, analog video interface or its combination, and it passes through respectively
Respective signaling conversion circuit is connected to the multichannel TTL (Transistor-Transistor of PLD 12
Logic, transistor-transistor logic level) signal parallel input interface, and signaling conversion circuit typically comprises video decoding
Device and if video input interface is furnished with corresponding video ring outgoing interface, then signaling conversion circuit will also include video distributor example
Such as one-in-and-two-out distributor.
PLD 12 is mainly used in receiving and handles incoming video signal and output multi-channel such as four road TTL
Signal is handled for rear-class video signal adapter 13, and it is, for example, that FPGA (Field Programmable Gate Array, shows
Field programmable gate array) device.
Video-frequency signal converter 13 connects the multichannel TTL signal parallel output interface of PLD 12 and may be programmed
Multichannel LVDS (Low Voltage Differential Signaling, Low Voltage Differential Signal) signal input of logical device 14
Interface.Video-frequency signal converter 13 is mainly used in receiving and handles the TTL format videos of the output of prime PLD 12
Signal is simultaneously processed, and the signal after processing is output into rear class PLD 14 with LVDS signal formats.
PLD 14 is mainly used in receiving the video for the LVDS forms that prime video-frequency signal converter 13 is sent out
Signal simultaneously processes and exported corresponding vision signal and go to show to different output interfaces, and it is, for example, FPGA device.
Multi-channel video output interface 15 connects the output of PLD 14, and it is typically with digital visual interface
Such as DVI interface, DP interfaces and/or SDI interfaces etc..
Microcontroller 16 connects PLD 12, video-frequency signal converter 13 and PLD 14.This
In embodiment, microcontroller 16 is mainly used in loading and configuration of programmable logic devices 12 and PLD 14, passes through
Communication interface and PERCOM peripheral communication and finishing man-machine interaction interface etc., it is, for example, MCU, as MCU based on ARM kernels etc..
Clock generator 17 is connected with PLD 12 and PLD 14, such as programmable
Logical device 12 and 14 provides the clock signal such as system clock needed for work.
In summary, the present embodiment is core with PLD 12,14 and video-frequency signal converter 13, is used
The interior synchronous mode of video-frequency signal converter 14 may be such that synchronously preferably being handled for vision signal, and set multichannel defeated
Multichannel input and the multiple-channel output of vision signal can be supported with output interface by entering.
Second embodiment
As shown in Fig. 2 a kind of video processor 20 provided in the utility model second embodiment, including：Multi-channel video
Input interface such as HDMI 211, SDI interfaces 212a, USB interface 213, DIV interfaces 214, SDI ring outgoing interface 212b, line
Cable balanced device (Equalizer) 212c, cable drive (Cable Driver) 212d, DVI ring outgoing interface 214b, it is programmable to patrol
Collect device 22, video-frequency signal converter 23, PLD 24, multi-channel video output interface such as binary channels DVI interface
251st, single channel DVI interface 252, DP interfaces 253 and SDI interfaces 254, microcontroller 26, clock generator 27, signal conversion electricity
Road 281,282,283,284 and 285, input subcard spare interface 29, input subcard spare interface 30, genlock
(Genlock) signal input interface 31a, genlock hoop outgoing interface 31b, signal extracting circuit 32, video encoder
33a, video premonitoring spare interface 33b, output daughter board spare interface 34, liquid crystal display (LCD) interface 35, USB interface 36, network interface
37a and PHY chip 37b.
Wherein, (High Definition Multimedia Interface, digital high-definition multimedia connect HDMI
Mouthful) the parallel input interface of TTL signal all the way that connects PLD 22 by signaling conversion circuit 281 is (such as corresponding
(48+4) bars cabling)；HDMI is, for example, HDMI1.4 interfaces, and signaling conversion circuit 281 is for example comprising HDMI video solution
Code chip.SDI interfaces (Serial Digital Interface, digital component serial line interface) 212a is furnished with SDI ring outgoing interfaces
For 212b, SDI interface 212a by cable balanced device 212c connections signaling conversion circuit 282, SDI ring outgoing interfaces 212b passes through cable
Driver 212d connections signaling conversion circuit 282, signaling conversion circuit 282 connect the letters of TTL all the way of PLD 22
Number parallel input interface (such as corresponding (20+4) bars cabling) and for example including one-in-and-two-out video distributor and SDI videos
Decoder；SDI interfaces 212a in the present embodiment can be with two-way.VGA (Video Graphics Array, Video Graphics Array)
Interface 213 by signaling conversion circuit 283 connect PLD 22 the parallel input interface of TTL signal all the way (such as
Corresponding (24+4) bars cabling), signaling conversion circuit 283 is for example including VGA decoding chips.(digital video connects DVI interface
Mouthful, Digital Video Interface) 214a equipped with DVI rings outgoing interface 214b, DVI interface 214a pass through signal conversion electricity
Road 284 connects the parallel input interface of TTL signal all the way (such as corresponding (24+4) bars cabling) of PLD 22,
DVI ring outgoing interface 214b connections signaling conversion circuit 284, and signaling conversion circuit 284 for example solves including video distributor and DVI
Code chip.Input the TTL signal all the way that subcard spare interface 29 connects PLD 22 by signaling conversion circuit 285
Parallel input interface (such as corresponding (24+4) bars cabling) and the input subcard of video interface is carried suitable for grafting；Input
Card spare interface 30 connects the parallel input interface of TTL signal all the way of PLD 22, and it is for example originally as TTL signal
Parallel input interface and the input subcard that video interface and video decoding chip are carried suitable for grafting；Input subcard spare interface 29
It is two-way that can be with input subcard premonitoring interface 30, and input subcard spare interface in four tunnels is used as Function Extension altogether.
PLD 22 also passes through video encoder 33a connection video premonitoring spare interface 33b, video herein
Premonitoring spare interface 33b can be connected with video interface such as DVI or HDMI.The programmable logic device of the present embodiment
Part 22FPGA1 is mainly used in：A) receive and handle incoming video signal；B) independent control exports pre-monitoring frequency signal all the way, with
The real-time status of monitoring site；And c) the parallel TTL signal in output multi-channel such as four tunnels is (for example right per TTL signal parallel all the way
Answer (24+4) bars cabling)) handled for rear-class video signal adapter 23.
Video-frequency signal converter 23 connects the multichannel TTL signal parallel output interface of PLD 22 and may be programmed
The multichannel LVDS signal input interfaces of logical device 24.The video-frequency signal converter 23 of the present embodiment is mainly used in：A) receive simultaneously
The vision signal of the output of processing prime PLD 22 simultaneously processes；And b) by the signal after processing with LVDS signals
Form is output to rear class PLD 24.
PLD 24 by 8 input/output (I/O) expansion interfaces connect PLDs 22 and
Genlock signal input interface 31a is connected by signal extracting circuit 32.The PLD 24 of the present embodiment is main
For：A) receive the vision signal for the LVDS forms that prime video-frequency signal converter 23 is sent out and process；B) receive from synchronization
The signal such as clock signal, horizontal synchronization that separation is extracted in the genlock signal of lockin signal input interface 31a inputs are believed
Number, vertical synchronizing signal and output enable signal etc. and make the synchronization of vision signal to prime；C) by 8 signals of extension with
PLD 22 is communicated；And d) export corresponding vision signal and go to show to different output interfaces.It is in addition, same
Step lockin signal ring outgoing interface 31b is connected to the node between synchronous lockin signal input interface 31a and signal extracting circuit 32.
Binary channels DVI interface 251 for example connects the one of PLD 24 by DVI video encoders (not shown)
Road TTL signal parallel output interface (such as corresponding (24+4) bars cabling), single channel DVI interface 252 is for example regarded by DVI
The parallel output of the TTL signal all the way interface (such as corresponding (24+4) of frequency encoder (not shown) connection PLD 24
Bars cabling).DP (DisplayPort) interface 253 connects the (serializers/solution of SerDes all the way of PLD 24
String device) interface.SDI interfaces 254 connect the SerDes interfaces all the way of PLD 24, and SDI interfaces 254 can be two
Road.The parallel output of the TTL signal all the way interface of the connection PLD 24 of output daughter board spare interface 34 or all the way LVDS
Signal output interface, and it can be two-way to export daughter board spare interface 34；Furthermore export daughter board spare interface 34 as function to expand
Exhibition is used, and it can export subcard with grafting, and exports subcard with existing DVI interface 251,252 to can be configured to DVI dual links defeated
Go out, can easily realize that bigger resolution ratio is shown, the deformation of image tensionless winkler foundation, display effect are clearly fine and smooth.
Microcontroller 26 connect PLD 22, video-frequency signal converter 23 and PLD 24 and
Liquid crystal display (LCD) interface 35 and USB interface 36 are connected, and passes through PHY chip 37b connection network interfaces 37a；USB interface 36 herein
With network interface 37a as microcontroller 26 and the interface of PERCOM peripheral communication.The microcontroller 26 of the present embodiment is mainly used in：A) loading and
Configuration of programmable logic devices 22 and PLD 24；And b) by USB, PHY and PERCOM peripheral communication and complete people
Machine interactive interface etc..
Clock generator 27 is connected with PLD 22 and PLD 24, such as programmable
Logical device 22 and 24 provides the clock signal such as system clock needed for work.
In summary, the present embodiment is core with PLD 22,24 and video-frequency signal converter 23, is used
The interior synchronous mode of video-frequency signal converter 24 may be such that synchronously preferably being handled for vision signal, and set multichannel defeated
Multichannel input and the multiple-channel output of vision signal can be supported with output interface by entering.Furthermore expansion module is drawn in the form of subcard
Go out, it is more convenient to patch.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be with
Realize by another way.For example, device embodiment described above is only schematical, for example, the unit
Division, only a kind of division of logic function, can there is other dividing mode, such as multichannel unit or component when actually realizing
Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.It is another, it is shown or
The mutual coupling discussed or direct-coupling or communication connection can be the indirect couplings by some interfaces, device or unit
Close or communicate to connect, can be electrical, mechanical or other forms.
The unit illustrated as separating component can be or may not be physically separate, show as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multichannel
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
Finally it should be noted that：Above example is only to illustrate the technical solution of the utility model, rather than its limitations；
Although the utility model is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：
It can still modify to the technical scheme described in foregoing embodiments, or which part technical characteristic is carried out etc.
With replacement；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the utility model technology
The spirit and scope of scheme.
Claims (12)
- A kind of 1. video processor, it is characterised in that including：Multi-channel video input interface, the first PLD, video Signal adapter, the second PLD, multi-channel video output interface, microcontroller and clock generator；The multi-channel video input interface is connected to first programmable logic device by respective signaling conversion circuit respectively The parallel input interface of multichannel TTL signal of part, the video-frequency signal converter connect the more of first PLD The multichannel LVDS signal input interfaces of road TTL signal parallel output interface and second PLD, the multichannel Video output interface connects the output of second PLD, first PLD and described second PLD connects the clock generator, and the microcontroller connects first PLD, described Video-frequency signal converter and second PLD.
- 2. video processor according to claim 1, it is characterised in that the multi-channel video input interface connects including SDI Mouthful；The video processor includes cable balanced device, cable drive and SDI ring outgoing interfaces；The cable balanced device is connected to Between the SDI interfaces and the signaling conversion circuit being connected with the SDI, the cable drive is connected to the SDI Between ring outgoing interface and the signaling conversion circuit being connected with the SDI interfaces.
- 3. video processor according to claim 1, it is characterised in that the multi-channel video input interface regards including numeral Frequency interface；The video processor includes digital video ring outgoing interface, and the digital video ring outgoing interface be connected to it is described The connected signaling conversion circuit of digital visual interface, the digital visual interface are selected from DVI interface and/or SDI interfaces.
- 4. video processor according to claim 1, it is characterised in that including：At least the first input subcard is reserved all the way Interface, first programmable logic device is connected to by signaling conversion circuit per the first input subcard spare interface all the way The parallel input interface of TTL signal all the way of part.
- 5. the video processor according to claim 1 or 4, it is characterised in that including：At least the second input subcard is pre- all the way Stay interface, be per the second input subcard spare interface all the way the parallel input interface of TTL signal and be connected to described first can The parallel input interface of TTL signal all the way of programmed logic device.
- 6. video processor according to claim 1, it is characterised in that including：Genlock signal input interface, signal Extract circuit and genlock hoop outgoing interface；The signal extracting circuit is connected to the genlock signal input interface Between second PLD, the genlock hoop outgoing interface connects the genlock signal input Node between interface and the signal extracting circuit.
- 7. video processor according to claim 1, it is characterised in that including：Video premonitoring spare interface and company all the way The video encoder being connected between first PLD and the video premonitoring spare interface；Described second can compile Journey logical device connects first PLD by 8 input/output expansion interfaces.
- 8. video processor according to claim 1, it is characterised in that multi-channel video output interface connection described the The TTL signal parallel output interface and serializer/de-serializers interface of two PLDs.
- 9. video processor according to claim 8, it is characterised in that the multi-channel video output interface includes：Single-pass Road DVI interface and binary channels DVI interface, the two-way TTL signal parallel output of second PLD is connected respectively Interface.
- 10. video processor according to claim 8, it is characterised in that the multi-channel video output interface includes：DP connects Mouth and SDI interfaces, the serializer/de-serializers interface of second PLD is connected respectively.
- 11. video processor according to claim 1, it is characterised in that also include：At least output subcard is reserved all the way connects Mouthful, it is defeated parallel per the TTL signal all the way that the output subcard spare interface is connected to second PLD all the way Outgoing interface or all the way LVDS signal output interfaces.
- 12. video processor according to claim 1, it is characterised in that also include：Network interface, USB interface and liquid crystal display connect Mouthful, the network interface connects the microcontroller by PHY chip, and the USB interface connects described micro- with the LCD Interface Controller.
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| CN201720582840.2U CN206865570U (en) | 2017-05-22 | 2017-05-22 | Video processor |
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|---|---|---|---|
| CN201720582840.2U CN206865570U (en) | 2017-05-22 | 2017-05-22 | Video processor |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108922095A (en) * | 2018-07-12 | 2018-11-30 | 江苏慧学堂系统工程有限公司 | A kind of computer based community security system and method |
| CN111081184A (en) * | 2018-10-19 | 2020-04-28 | 西安诺瓦星云科技股份有限公司 | Display screen controller, display system, core board and display box |
| CN111355905A (en) * | 2018-12-21 | 2020-06-30 | 西安诺瓦星云科技股份有限公司 | Signal distributor |
| CN112995431A (en) * | 2019-12-17 | 2021-06-18 | 瑞昱半导体股份有限公司 | Display port to high-definition multimedia interface converter and signal conversion method |
| CN113132552A (en) * | 2019-12-31 | 2021-07-16 | 成都鼎桥通信技术有限公司 | Video stream processing method and device |
| CN114071216A (en) * | 2020-07-30 | 2022-02-18 | 北京嗨动视觉科技有限公司 | Video processing apparatus and video processing method |
| CN114422654A (en) * | 2021-12-23 | 2022-04-29 | 西安诺瓦星云科技股份有限公司 | SDI output method, device, video processing equipment and readable storage medium |
-
2017
- 2017-05-22 CN CN201720582840.2U patent/CN206865570U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108922095A (en) * | 2018-07-12 | 2018-11-30 | 江苏慧学堂系统工程有限公司 | A kind of computer based community security system and method |
| CN111081184A (en) * | 2018-10-19 | 2020-04-28 | 西安诺瓦星云科技股份有限公司 | Display screen controller, display system, core board and display box |
| CN111355905A (en) * | 2018-12-21 | 2020-06-30 | 西安诺瓦星云科技股份有限公司 | Signal distributor |
| CN112995431A (en) * | 2019-12-17 | 2021-06-18 | 瑞昱半导体股份有限公司 | Display port to high-definition multimedia interface converter and signal conversion method |
| CN113132552A (en) * | 2019-12-31 | 2021-07-16 | 成都鼎桥通信技术有限公司 | Video stream processing method and device |
| CN114071216A (en) * | 2020-07-30 | 2022-02-18 | 北京嗨动视觉科技有限公司 | Video processing apparatus and video processing method |
| CN114422654A (en) * | 2021-12-23 | 2022-04-29 | 西安诺瓦星云科技股份有限公司 | SDI output method, device, video processing equipment and readable storage medium |
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Address after: 710075 DEF101, Zero One Square, Xi'an Software Park, No. 72 Zhangbajie Science and Technology Second Road, Xi'an High-tech Zone, Shaanxi Province Patentee after: Xi'an Nova Nebula Technology Co., Ltd. Address before: 710075 Qinfengge D District 401, Xi'an Software Park, 68 Science and Technology Second Road, Xi'an High-tech Zone, Shaanxi Province Patentee before: Xian Novastar Electronic Technology Co., Ltd. |