CN109819191A - A kind of MIPI C-PHY signal generator and its signal generating method - Google Patents
A kind of MIPI C-PHY signal generator and its signal generating method Download PDFInfo
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- CN109819191A CN109819191A CN201910043126.XA CN201910043126A CN109819191A CN 109819191 A CN109819191 A CN 109819191A CN 201910043126 A CN201910043126 A CN 201910043126A CN 109819191 A CN109819191 A CN 109819191A
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Abstract
The invention belongs to field of display technology, disclose a kind of MIPI C-PHY signal generator and its signal generating method, signal generator includes fpga chip, MIPI C-PHY bridging chip, and fpga chip includes embedded processor Nios II, network data controller, DDR read-write controller, image data turns RGB block, RGB turns MCU data processing module；It is controlled by the embedded processor Nios II of fpga chip, is exported after image data is converted to rgb interface signal or MCU interface signal, rgb interface signal or MCU interface signal are converted to by MIPI C-PHY interface signal by MIPI C-PHY bridging chip.The present invention can support whole display patterns of MIPI C-PHY interface display module.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of MIPI C-PHY signal generator and its signal generation sides
Method.
Background technique
MIPI D-PHY is widely used in the part that processor is connect with display screen, camera.With camera, display screen
Pixel and frame frequency increase, the data transmission bauds of MIPI D-PHY before can no longer meet current needs, now most
New MIPI C-PHY standard has been released.
Compared to MIPI D-PHY, MIPI C-PHY supports higher resolution ratio and refreshing frequency, LCD, OLED Mo Zu producer
Research and development schedule is put on using MIPI C-PHY as next-generation, some producer's samples have come out, this is also accelerated
MIPI C-PHY interface display module detection device demand.
Summary of the invention
The purpose of the application is to provide a kind of MIPI C-PHY signal generator and its signal generating method.
The embodiment of the present application provides a kind of MIPI C-PHY signal generator, comprising: fpga chip, MIPI C-PHY bridge joint
Chip；
The fpga chip includes embedded processor Nios II, network data controller, DDR read-write controller, picture number
According to turn RGB block, RGB turns MCU data processing module；
The embedded processor Nios II turn respectively with the network data controller, described image data RGB block,
The RGB turns the connection of MCU data processing module；The network data controller, the DDR read-write controller, described image number
According to turn RGB block, the RGB turns MCU data processing module and is sequentially connected；The RGB turn MCU data processing module with it is described
The connection of MIPI C-PHY bridging chip.
Preferably, the fpga chip further include: SPI module；The embedded processor Nios II and the SPI module
Connection, the SPI module are connect with the MIPI C-PHY bridging chip.
Preferably, described image data turn RGB block and include: timing generation module, image data conversion module；When described
Sequence generation module is connect with described image data conversion module.
Preferably, the MIPI C-PHY signal generator further includes memory DDR3；The memory DDR3 and institute
State the DDR read-write controller connection in fpga chip.
Preferably, the MIPI C-PHY signal generator further includes the end PC；In the end PC and the fpga chip
Network data controller connection.
On the other hand, the embodiment of the present application provides a kind of signal generating method of MIPI C-PHY signal generator, passes through
The embedded processor Nios II of fpga chip is controlled, and image data is converted to rgb interface signal or MCU interface signal
After export；By MIPI C-PHY bridging chip by the rgb interface signal or the MCU interface from the fpga chip
Signal is converted to MIPI C-PHY interface signal.
Preferably, it is communicated by the network data controller of the fpga chip with the end PC；Pass through the fpga chip
The embedded processor Nios II control DDR read-write controller stores the image data that the end PC is sent to memory
In DDR3；
When point screen, electricity order will be opened by the end PC and be sent to the embedded processor Nios II, the inline processed
Device Nios II controls the DDR read-write controller and reads described image data；The embedded processor Nios II is to picture number
It is configured according to RGB block is turned, by described image data conversion at rgb interface signal；The embedded processor Nios II couple
RGB turns MCU data processing module and is configured, and under Command mode, the rgb interface signal is converted to MCU interface letter
Number, under Video mode, forward the rgb interface signal；The embedded processor Nios II by the rgb interface signal or
The MCU interface signal is exported to the MIPI C-PHY bridging chip；The MIPI C-PHY bridging chip meets the RGB
Message number or the MCU interface signal are converted to MIPI C-PHY interface signal.
Preferably, under Video mode, the embedded processor Nios II control SPI module exports SPI signal to institute
State MIPI C-PHY bridging chip.
Preferably, it includes timing generation module and image data conversion module that described image data, which turn RGB block,；When described
Sequence generation module generates rgb interface timing according to the time sequence parameter that the embedded processor Nios II is issued；Described image data
The timing that conversion module is generated according to the timing generation module, the described image that will be read from the DDR read-write controller
Data resolve into rgb image data, and export rgb interface signal.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
In the embodiment of the present application, a kind of MIPI C-PHY signal generator provided uses the inline processed of fpga chip
Device Nios II is controlled, and does signal conversion using MIPI C-PHY bridging chip.Fpga chip include network data controller,
DDR read-write controller, image data turn RGB block, RGB turns MCU data processing module, pass through the above-mentioned module in fpga chip
By image data final output be the identifiable rgb interface signal of MIPI C-PHY bridging chip or MCU interface signal, then
Rgb interface signal or MCU interface signal are converted into MIPI C-PHY interface signal by MIPI C-PHY bridging chip, for tool
There is the display module of MIPI C-PHY interface to show.The present invention supports whole display moulds of MIPI C-PHY interface display module
Formula, can support OTP/MTP/Gamma function, and the MIPI C-PHY interface signal of MIPI C-PHY bridging chip output can be supported most
High 6Lane, every lane highest support 2.85Gbps, maximum can support image resolution ratio 24bit 4096*2160@60Hz.
Detailed description of the invention
It, below will be to needed in embodiment description in order to illustrate more clearly of the technical solution in the present embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is one embodiment of the present of invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of block schematic illustration of MIPI C-PHY signal generator provided in an embodiment of the present invention.
Specific embodiment
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
Technical solution is stated to be described in detail.
A kind of MIPI C-PHY signal generator proposed by the present invention, using the embedded processor Nios II of fpga chip
It controls, MIPI C-PHY bridging chip does signal conversion.Fpga chip include network data controller, DDR read-write controller,
Image data turns RGB block, RGB turns MCU data processing module, SPI module, and final output is that MIPI C-PHY bridging chip can
The rgb interface signal or MCU interface signal of identification switch to MIPI C-PHY interface signal by MIPI C-PHY bridging chip,
It is shown for the display module with MIPI C-PHY interface.
Realize that the system block diagram of the signal generator of MIPI C-PHY interface is as shown in Figure 1 based on fpga chip.The end PC is logical
It crosses Ethernet (Eth) communication interface to communicate with network data controller (i.e. Net Data Controller in Fig. 1), then
DDR read-write controller (i.e. DDR Read Write in Fig. 1 is controlled by the embedded processor Nios II of fpga chip
Controller) data such as picture, mould group initial code initial code, timing timing that the end PC is sent are stored in
In memory DDR (i.e. DDR3 in Fig. 1).
When point screen, the end PC issues the embedded processor Nios II, embedded processor Nios of fpga chip by electricity order is opened
II controls DDR read-write controller by internal bus and reads picture, mould group initial code initial code, timing timing
Etc. data, and to image data turn RGB block (i.e. Data Conversation module in Fig. 1) configuration, complete image data
It is converted into rgb signal；Then configuration RGB turns MCU data processing module (i.e. RGB to MCU in Fig. 1), embedded processor
Nios II is arranged to configure and whether start RGB and turn MCU according to the different mode of Video, Command, therefore in Command mould
RGB image interface is completed under formula and turns MCU interface signal, and rgb interface signal is then forwarded under Video mode；According to different mode,
Embedded processor Nios II control rgb interface signal or MCU interface signal are exported to MIPI C-PHY bridging chip, MIPI C-
Rgb interface signal or MCU interface signal are switched to MIPI C-PHY interface signal by PHY bridging chip.Further, since Video mould
The needs of formula, embedded processor Nios II also need to control SPI module and export SPI signal to MIPI C-PHY bridging chip.
1, memory DDR3
DDR3 is for mould group initial code initial code, timing timing, picture needed for storing mould group point screen
Etc. data.
2, DDR read-write controller DDR Read Write Controller
DDR read-write controller is the multiport dma controller that a logic is realized, it can be adjusted according to read-write length dynamic
The burst-length of DDR is read and write, to reach maximum DDR bandwidth.Under the control of embedded processor Nios II, DDR Read-write Catrol
The end PC can be write direct DDR by the data that Ethernet is sent by device, can also by data from DDR reading after give it is embedded from
Reason device Nios II or image data turn RGB block.
3, embedded processor Nios II
Nios II in figure signal generator is FPGA embedded processor, its main function is as follows:
1) it is communicated with the end PC
Figure signal generator is communicated by ports such as Ethernets with the end PC, realizes picture, initial code initial
The downloadings of data such as code, timing timing and the transmitting-receiving of control command.
2) DDR read-write controller is controlled
Nios II can control the picture that DDR read-write controller issues the end PC, initial code initial code,
Storage is into DDR after DDR read-write controller is written in the data such as timing timing.
Nios II can also pass through initial code initial code in DDR read-write controller reading DDR, timing
The data such as timing.
3) configuration image data turns RGB block Data Conversation
The image data that DDR is read needs Nios II configuration relevant parameter just to can be converted rgb interface signal, parameter
It include: the parameters such as timing timing, image movement, RGB replacement data.
4) configuration RGB turns MCU data processing module RGB to MCU
MCU interface signal includes order and viewdata signal, and wherein command signal is derived from Nios II, Nios II
The interactive command of processing and bridging chip.It is issued including initial code initial code, Pgamma is adjusted, RGB and MCU believe
Number output selection etc. functions.
5) SPI module SPI Controller is configured
Video mode needs SPI to handle the interactive command with bridging chip, before the mould group of read-write SPI interface, needs
SPI module is configured, working frequency, operating mode, bit number including spi bus etc..Nios II is according to mould group
These parameters realize the configuration to SPI module by Avalon bus, export SPI signal.
6) point screen cuts figure
After the completion of the initialization of mould group, Nios II can size according to every width figure and address, control DDR read-write controller
It interprets blueprints from DDR, realize the point diagram of mould group and cuts figure.
4, image data turns RGB block Data Conversation
Image data turns the RGB that RGB block mainly needs the DDR data conversion read at MIPI C-PHY bridging chip
Interface data.It includes timing generation module and image data conversion module that image data, which turns RGB block,.
1) timing generation module
Timing generation module generates rgb interface timing according to the timing Timing parameter that Nios II is issued.
2) image data conversion module
The DDR image data read is resolved into RGB figure by the timing that image data conversion is generated according to timing generation module
As data, rgb interface signal is exported.
5, RGB turns MCU data processing module RGB To MCU
RGB turns MCU data processing module and rgb interface signal is mainly converted into the MCU interface needed under COMMAND mode
The control information of Nios II is additionally converted into MCU interface signal by signal.RGB turns MCU data processing module in Command
Rgb interface signal is converted into MCU interface signal under mode, rgb interface signal is forwarded under video mode.
A kind of MIPI C-PHY signal generator and its signal generating method provided in an embodiment of the present invention include at least such as
Lower technical effect:
1, rgb interface signal or MCU interface signal can be exported as needed by turning MCU data processing module by RGB, branch
Two kinds of display patterns needed for holding MIPI C-PHY interface display module, in conjunction with compression and non-compressed mode, the present invention is supported
All four kinds of display patterns of MIPI C-PHY interface display module: the compression of Video and non-compressed mode, the pressure of Command
Contracting and non-compressed mode.
2, Nios II and PC communication interaction, Row control, can support OTP/MTP/Gamma function.
3, FPGA can support highest to image data high speed processing, the MIPI C-PHY interface signal of bridging chip output
6Lane, every lane highest support 2.85Gbps, maximum can support image resolution ratio 24bit4096*2160@60Hz.
It should be noted last that the above specific embodiment is only used to illustrate the technical scheme of the present invention and not to limit it,
Although being described the invention in detail referring to example, those skilled in the art should understand that, it can be to the present invention
Technical solution be modified or replaced equivalently, without departing from the spirit and scope of the technical solution of the present invention, should all cover
In the scope of the claims of the present invention.
Claims (9)
1. a kind of MIPIC-PHY signal generator characterized by comprising fpga chip, MIPIC-PHY bridging chip；
The fpga chip includes embedded processor NiosII, network data controller, DDR read-write controller, image data turn
RGB block, RGB turn MCU data processing module；
The embedded processor NiosII turns RGB block, described with the network data controller, described image data respectively
RGB turns the connection of MCU data processing module；The network data controller, the DDR read-write controller, described image data turn
RGB block, the RGB turn MCU data processing module and are sequentially connected；The RGB turns MCU data processing module and the MIPIC-
The connection of PHY bridging chip.
2. MIPIC-PHY signal generator according to claim 1, which is characterized in that the fpga chip further include:
SPI module；The embedded processor NiosII is connect with the SPI module, and the SPI module and the MIPIC-PHY are bridged
Chip connection.
3. MIPIC-PHY signal generator according to claim 1, which is characterized in that described image data turn RGB block
Include: timing generation module, image data conversion module；The timing generation module and described image data conversion module connect
It connects.
4. MIPIC-PHY signal generator according to claim 1, which is characterized in that further include memory DDR3；It is described
Memory DDR3 is connect with the DDR read-write controller in the fpga chip.
5. MIPIC-PHY signal generator according to claim 1, which is characterized in that further include the end PC；The end PC with
Network data controller connection in the fpga chip.
6. a kind of signal generating method of MIPIC-PHY signal generator as described in claim 1, which is characterized in that pass through
The embedded processor NiosII of fpga chip is controlled, after image data is converted to rgb interface signal or MCU interface signal
Output；By MIPIC-PHY bridging chip by from the fpga chip the rgb interface signal or the MCU interface believe
Number be converted to MIPIC-PHY interface signal.
7. the signal generating method of MIPIC-PHY signal generator according to claim 6, passes through the fpga chip
Network data controller is communicated with the end PC；DDR read-write control is controlled by the embedded processor NiosII of the fpga chip
Device processed stores the image data that the end PC is sent into memory DDR3；
When point screen, electricity order will be opened by the end PC and be sent to the embedded processor NiosII, the embedded processor
NiosII controls the DDR read-write controller and reads described image data；The embedded processor NiosII turns image data
RGB block is configured, by described image data conversion at rgb interface signal；The embedded processor NiosII turns RGB
MCU data processing module is configured, and under Command mode, the rgb interface signal is converted to MCU interface signal,
Under Video mode, the rgb interface signal is forwarded；The embedded processor NiosII is by the rgb interface signal or described
MCU interface signal is exported to the MIPIC-PHY bridging chip；The MIPIC-PHY bridging chip is by the rgb interface signal
Or the MCU interface signal is converted to MIPIC-PHY interface signal.
8. the signal generating method of MIPIC-PHY signal generator according to claim 7, which is characterized in that in Video
Under mode, the embedded processor NiosII control SPI module exports SPI signal to the MIPIC-PHY bridging chip.
9. the signal generating method of MIPIC-PHY signal generator according to claim 7, which is characterized in that its feature
It is, it includes timing generation module and image data conversion module that described image data, which turn RGB block,；The timing generation module
Rgb interface timing is generated according to the time sequence parameter that the embedded processor NiosII is issued；Described image data conversion module root
According to the timing that the timing generation module generates, the described image data read from the DDR read-write controller are resolved into
Rgb image data, and export rgb interface signal.
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