CN114286034A - MIPI resistor network system and method - Google Patents
MIPI resistor network system and method Download PDFInfo
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- CN114286034A CN114286034A CN202111594458.0A CN202111594458A CN114286034A CN 114286034 A CN114286034 A CN 114286034A CN 202111594458 A CN202111594458 A CN 202111594458A CN 114286034 A CN114286034 A CN 114286034A
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Abstract
The invention provides an MIPI resistance network system and a method, the system comprises an MIPI control chip and a register, the MIPI control chip is provided with an integrated circuit bus interface, the MIPI control chip is used for receiving an MIPI signal sent by a camera and detecting the working mode of the camera; the register is used for configuring the register in a first configuration state through an integrated circuit bus interface when the working mode is a low-voltage mode so as to modulate the impedance resistor matched with the MIPI resistor network system into a first impedance resistor; or in a high-speed mode, the configuration register of the MIPI control chip is in a second configuration state so as to modulate the impedance resistor matched with the MIPI resistor network system into a second impedance resistor, and the second impedance resistor is larger than the first impedance resistor. The system can enable the MIPI resistor network to be stably switched between a low-voltage mode and a high-speed mode, and stability of data transmission is guaranteed.
Description
Technical Field
The invention relates to the technical field of MIPI circuits, in particular to an MIPI resistor network system and a MIPI resistor network method.
Background
Mipi (mobile Industry Processor interface), an open standard and specification established for mobile application processors, is now widely used in many fields such as mobile phones and semiconductors.
In the existing MIPI resistor network, a majority of resistors are used in parallel, the internal MIPI physical layer supports two operating modes of HS (high speed) and LP (low power), and a low-voltage differential signal is used in the HS mode and a single-ended signal is used in the LP mode.
However, in the process of converting the LP mode into the HS mode of the existing MIPI resistor network, the internal high level thereof can only be pulled to a half-high state, so that the CPU may misjudge the current operating mode, thereby affecting the mode conversion and causing data transmission failure.
Disclosure of Invention
Based on this, the present invention provides an MIPI resistor network system and method, so as to solve the problem that in the process of converting the LP mode into the HS mode of the MIPI resistor network in the prior art, the internal high level can only be pulled to a half-high state, so that the CPU may misjudge the current operating mode.
The invention provides an MIPI resistance network system, which comprises an MIPI control chip and a register, wherein the MIPI control chip is provided with an integrated circuit bus interface and is used for receiving an MIPI signal sent by a camera and detecting the working mode of the camera according to the MIPI signal sent by the camera;
the register is used for:
when the MIPI control chip detects that the working mode of the camera is a low-voltage mode, the MIPI control chip configures the register to be in a first configuration state through the integrated circuit bus interface so as to modulate an impedance resistor matched with the MIPI resistor network system into a first impedance resistor; or
When the MIPI control chip detects that the working mode of the camera is a high-speed mode, the MIPI control chip configures the register to be in a second configuration state through the integrated circuit bus interface so as to modulate an impedance resistor matched with the MIPI resistor network system into a second impedance resistor, wherein the second impedance resistor is larger than the first impedance resistor.
The invention has the beneficial effects that: the MIPI control chip can receive MIPI signals sent by the camera and accurately detect whether the current camera is in a low-voltage mode or a high-speed mode according to the current MIPI signals, meanwhile, the MIPI control chip can correspond to the working state of the configuration register and correspondingly modulate impedance resistance in the system into corresponding resistance values, so that the MIPI resistance network can be stably switched between the low-voltage mode and the high-speed mode, the phenomenon that the internal high level of the MIPI control chip can only be pulled to a half-high state is avoided, and the stability of data transmission is guaranteed.
Preferably, the MIPI control chip is electrically connected to the register through the integrated circuit bus interface, and the integrated circuit bus interface includes a control line port and a data line port.
Preferably, the data line port is electrically connected with a first pull-up resistor, the control line port is electrically connected with a second pull-up resistor, the first pull-up resistor is connected with the second pull-up resistor in parallel, and the input ends of the first pull-up resistor and the second pull-up resistor are externally connected with a power supply.
Preferably, the camera comprises a camera module and a connector, one end of the connector is electrically connected with the camera module, and the other end of the connector is electrically connected with the connector, wherein the camera module is arranged on the camera module;
the camera module is electrically connected with the connector through a video data transmission port and a data clock port.
Preferably, a PCLK connection port of the camera module is electrically connected to a first resistor, a clock input signal port of the connector is electrically connected to a second resistor, and a ground connection port and a power connection port of the connector are both electrically connected to a first capacitor.
Preferably, the MIPI control chip includes a filtering module, one end of the filtering module is grounded, and the other end of the filtering module is connected with the power supply and the power supply connection port of the MIPI control chip.
Preferably, the filtering module includes a plurality of second capacitors connected in parallel, one end of each of the plurality of second capacitors is grounded, and the other end of each of the plurality of second capacitors is connected to the power supply and the power connection port of the MIPI control chip.
Preferably, the MIPI control chip is electrically connected with a third resistor, and an output end of the third resistor is grounded.
Preferably, the camera reset connection port of the MIPI control chip and the integrated circuit reset connection port are both connected with a fourth resistor.
A second aspect of the present invention is to provide an MIPI resistive network transmission method applied to the MIPI resistive network system described above, the method including:
the MIPI control chip receives an MIPI signal sent by the camera and detects the running mode of the camera according to the MIPI signal;
when the MIPI control chip detects that the running mode of the camera is the low-voltage mode, the MIPI control chip configures the register to be in the first configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the first impedance resistor;
and when the MIPI control chip detects that the running mode of the camera is the high-speed mode, the MIPI control chip configures the register to be in the second configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the second impedance resistor.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of a MIPI control chip in a MIPI resistive network system according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a register in an MIPI resistor network system according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a camera module in an MIPI resistor network system according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a connector in an MIPI resistive network system according to a first embodiment of the present invention;
fig. 5 is a schematic structural diagram of a control circuit of a MIPI control chip in the MIPI resistive network system according to the first embodiment of the present invention;
fig. 6 is a flowchart of an MIPI resistive network transmission method according to a second embodiment of the present invention.
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 to 5, a MIPI resistive network system according to a first embodiment of the present invention is shown, and the MIPI resistive network system is mainly applied in the technical field of MIPI resistive networks, and is specifically used for switching the working mode in the MIPI resistive network to ensure stable data transmission.
Specifically, in this embodiment, the MIPI resistive network system includes a MIPI control chip 10 and a register 20, where the MIPI control chip 10 is provided with an integrated circuit bus interface, and the MIPI control chip 10 is configured to receive an MIPI signal sent by a camera and detect a working mode of the camera according to the MIPI signal sent by the camera;
the register 20 is used for:
when the MIPI control chip 10 detects that the working mode of the camera is a low-voltage mode, the MIPI control chip 10 configures the register 20 in a first configuration state through the integrated circuit bus interface, so as to modulate an impedance resistor matched with the MIPI resistor network system into a first impedance resistor; or
When the MIPI control chip 10 detects that the working mode of the camera is a high-speed mode, the MIPI control chip 10 configures the register 20 in a second configuration state through the integrated circuit bus interface to modulate an impedance resistor matched with the MIPI resistor network system into a second impedance resistor, where the second impedance resistor is greater than the first impedance resistor.
It should be noted that, in this embodiment, the MIPI control chip 10 is electrically connected to the register 20 through the integrated circuit bus interface, specifically, the essence of the integrated circuit bus interface is an IIC interface, the IIC interface includes a control line port 11 and a data line port 12, wherein the essence of the control line port 11 is an SCL connection port, and the essence of the data line port 12 is an SDA connection port. When the integrated circuit bus interface is used, the signal connection between the MIPI control chip 10 and the register 20 can be established through the integrated circuit bus interface, and the signal transmission between the MIPI control chip 10 and the register 20 is realized, so that the MIPI control chip 10 controls the register 20.
Further, in the present embodiment, the data line port 12, i.e. the SDA connection port 12, is electrically connected to a first pull-up resistor 13, and correspondingly, the control line port 11, i.e. the SCL connection port 11, is electrically connected to a second pull-up resistor 14, wherein the first pull-up resistor 13 is connected in parallel with the second pull-up resistor 14, and the input terminals of the first pull-up resistor 13 and the second pull-up resistor 14 are externally connected to a power supply. In this embodiment, the SDA connection port 12 is connected to the first pull-up resistor 13, and the SCL connection port 11 is connected to the second pull-up resistor 14, so that in use, the MIPI control chip 10 can adjust the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 through the SDA connection port 12 and the SCL connection port 11, respectively, and simultaneously change the operating logic of the register 20, thereby meeting the level standards of the camera in different operating modes.
Specifically, in this embodiment, it should be noted that, when the MIPI control chip 10 detects that the camera is in the low-voltage mode, the single-ended signal HSUL _12 is used, which has a larger noise tolerance compared to the conventional TTL signal, and the input impedance of the single-ended signal is much larger than that of the TTL signal.
Further, when the MIPI control chip 10 detects that the camera is in the high-speed mode, the differential LVDS level standard is adopted. Those skilled in the art will appreciate that the most basic LVDS devices are LVDS drivers and receivers. The LVDS driver is composed of a current source driving a pair of differential lines, and the current is typically 3.5 mA. The LVDS receiver has a high input impedance, so most of the current output by the driver flows through a 100 ohm matched resistor and produces a voltage of about 350mV at the input of the LVDS receiver. When the LVDS driver flips, it changes the direction of the current flowing through the resistor, thus producing valid logic "1" and logic "0" states.
Specifically, the transmission process when the camera that this embodiment provided gets into low pressure mode does: LP-11 → LP-10 → LP-00 → LP-01 → LP-00 → Entry Code → LPD (10 MHz);
the transmission process when exiting the low voltage mode is as follows: LP-10 → LP-11;
the transmission process for entering the high-speed mode is as follows: LP-11 → LP-01 → LP-00 → SoT (00011101) → HSD (80 Mbps. about.1 Gbps);
procedure for exiting high speed mode: EoT → LP-11.
Further, in this embodiment, it should be further noted that the MIPI control chip 10 includes a MIPI CSI-2Rx Subsystem and an AXI Interconnect, and in an actual working process, the MIPI control chip 10 receives a MIPI signal sent by the camera through the MIPI CSI-2Rx Subsystem and transmits the MIPI signal to the AXI Interconnect, so as to detect whether the camera is currently in a low-voltage mode or a high-speed mode.
Specifically, in this embodiment, the camera may be an image camera, and the camera transmits image data received by the camera to the FPGA for processing through the MIPI _ LAN0_ P/MIPI _ LAN0_, MIPI _ LAN1_ P/MIPI _ LAN1_ PN, and MIPI _ CLK _ P/MIPI _ CLK _ N connection ports, that is, to the MIPI control chip 10 for processing.
Specifically, in this embodiment, if the MIPI control chip 10 detects that the camera is in the low-voltage mode, the MIPI control chip 10 can configure the register 20 to be in the first configuration state through the configured integrated circuit bus interfaces, i.e. the SCL connection port 11 and the SDA connection port 12, specifically, the MIPI control chip 10 can transmit a configuration protocol preset and programmed in its interior to the register 20 through the SCL connection port 11 and the SDA connection port 12, so as to make the register 20 be in the first configuration state, i.e. configure the register 20 to be in the 111100 state, and at the same time, modulate the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 from 150 Ω to 4.5K Ω -4.8K Ω, preferably, in this embodiment, modulate the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 to 4.7K Ω, therefore, the levels of the LP _ P connection port and the LP _ N connection port at the two ends of the MIPI control chip 10 are not affected, and the mutual interference is avoided. In this embodiment, it is preferable that the register 20 of this embodiment has a model number TPL0401C for convenience of implementation.
Furthermore, in this embodiment, when the MIPI control chip 10 detects that the camera is in the high-speed mode, the MIPI control chip 10 can transmit a configuration protocol programmed in advance therein to the register 20 through the SCL connection port 11 and the SDA connection port 12, so as to enable the register 20 to be in the second configuration state, that is, the register 20 is configured in the 10 state, and at the same time, the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 are adjusted from 4.7K Ω to 150 Ω, so that the levels of the LP _ P connection port and the LP _ N connection port at the two ends of the MIPI control chip 10 are not affected, and the mutual interference is avoided, so as to meet the LVDS level standard of the camera in the high-speed mode.
Further, in this embodiment, as shown in fig. 5, it should be noted that when the MIPI control chip 10 receives the MIPI signal sent by the camera through the MIPI CSI-2Rx Subsystem, the MIPI control chip 10 configures the operating state of the register 20 through the control circuit shown in fig. 5, that is, the register 20 is modulated into the first configuration state and the second configuration state, so that the levels of the LP _ P connection port and the LP _ N connection port at the two ends of the MIPI control chip 10 are not affected, and the mutual interference is avoided, so as to meet the LVDS level standard of the camera in the high-speed mode and the low-voltage mode.
In addition, in this embodiment, as shown in fig. 3 to 4, it should be further noted that the camera includes a camera module 30 and a connector 40, in implementation, one end of the connector 40 is electrically connected to the camera module 30, and the other end is electrically connected to the connector 40;
the camera module 30 is electrically connected to the connector 40 through a video data transmission port and a data clock port, and specifically, in the present embodiment, the camera module 30 is electrically connected to the connector 40 through a MIPI _ LAN0_ P/MIPI _ LAN0_ PN connection port, a MIPI _ LAN1_ P/MIPI _ LAN1_ PN connection port, and a MIPI _ CLK _ P/MIPI _ CLK _ N connection port.
As shown in fig. 3, the PCLK connection port 31 of the camera module 30 is electrically connected to a first resistor 32, and the clock input signal port of the connector 40, i.e., the CAM _ CLK connection port 41, is electrically connected to a second resistor 42, and the ground connection ports of the connector 40, i.e., the GND _6 connection port, the GND _5 connection port, and the power connection port, i.e., the VDD connection port, are electrically connected to a first capacitor 43.
In the present embodiment, the first resistor 32 is provided in the camera module 30, whereby the PCLK connection port 31 of the camera module 30 can be protected from overvoltage, and the second resistor 42 is provided in the connector 40, whereby the CAM _ CLK connection port 41 of the connector 40 can be protected from overvoltage.
In addition, in the present embodiment, the connection port 15 of the MIPI control chip 10IO _ L6N _ T0_ VREF _12 is electrically connected to the third resistor 16, and the output terminal of the third resistor 16 is grounded. In use, the third resistor 16 is used to protect the voltage received by the IO _ L6N _ T0_ VREF _12 connection port 15 from being within the tolerance range, and functions as a reference voltage.
Further, as shown in fig. 1, the MIPI controller chip 10 includes a filter module 17, and in implementation, one end of the filter module 17 is grounded, and the other end is connected to the power supply and the VCCO _12 connection port 18 of the MIPI controller chip 10.
Specifically, the filtering module 17 includes a plurality of second capacitors 171 connected in parallel, one end of each of the plurality of second capacitors 171 is grounded, and the other end is connected to the power supply and the VCCO _12 connection port 18 of the MIPI control chip 10. During the use, this filtering module 17 can be effectual plays the filtering action to the voltage that MIPI control chip 10 received to make MIPI control chip 10 can continuously be in normal operating condition.
In addition, in this embodiment, the camera reset connection port of the MIPI control chip 10, that is, the IO _ L16N _ T2_12 connection port, the IO _ L21P _ T3_ DQS _12 connection port, and the integrated circuit reset connection port, that is, the IO _ L21N _ T3_ DQS _12 connection port are all connected with the fourth resistor 19, and in use, the fourth resistor 19 is used to perform a function of debugging a camera.
When the MIPI resistor network is used, the MIPI control chip 10 is electrically connected with the register 20 through the integrated circuit bus interface, the MIPI control chip 10 can receive MIPI signals sent by a camera, and the current camera is accurately detected to be in a low-voltage mode or a high-speed mode according to the current MIPI signals, meanwhile, the MIPI control chip 10 can correspondingly configure the working state of the register 20 and correspondingly modulate the impedance resistor in the system into a corresponding resistance value, so that the MIPI resistor network can be stably switched between the low-voltage mode and the high-speed mode, the phenomenon that the high level in the MIPI resistor network can only be pulled to be in a half-high state is avoided, and the stability of data transmission is guaranteed.
It should be noted that the implementation process described above is only for illustrating the applicability of the present application, but this does not represent that the MIPI resistor network system of the present application has only the above-mentioned implementation procedure, and on the contrary, the MIPI resistor network system of the present application can be incorporated into the feasible implementation scheme of the present application as long as the implementation of the present application can be achieved.
The MIPI resistance network system in the embodiment of the invention can enable the camera to be stably switched between the low-voltage mode and the high-speed mode, avoids the phenomenon that the internal high level of the camera can only be pulled to a half-high state, and ensures the stability of data transmission.
Referring to fig. 5, a second embodiment of the present invention provides a MIPI resistive network transmission method applied to the MIPI resistive network system provided in the first embodiment, where the method is applied to the MIPI resistive network system, and specifically, the method includes the following steps:
step S10, the MIPI control chip 10 receives the MIPI signal sent by the camera, and detects the operation mode of the camera according to the MIPI signal;
specifically, in this step, the MIPI control chip 10 includes an MIPI CSI-2Rx Subsystem and an AXI Interconnect, and in an actual working process, the MIPI control chip 10 receives an MIPI signal sent by the camera through the MIPI CSI-2Rx Subsystem and transmits the MIPI signal to the AXI Interconnect, so as to detect whether the camera is currently in a low-voltage mode or a high-speed mode.
Step S20, when the MIPI control chip 10 detects that the operation mode of the camera is the low voltage mode, the MIPI control chip 10 configures the register 20 in the first configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the first impedance resistor;
further, in this step, the MIPI control chip 10 can configure the register 20 in the first configuration state through the configured integrated circuit bus interfaces, i.e. the SCL connection port 11 and the SDA connection port 12, specifically, the MIPI control chip 10 can transmit a configuration protocol preset and programmed in its interior to the register 20 through the SCL connection port 11 and the SDA connection port 12, so as to enable the register 20 to be in the first configuration state, i.e. the register 20 is configured in the 111100 state, and at the same time, the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 are modulated from 150 Ω to 4.5K Ω -4.8K Ω, preferably, in this embodiment, the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 are modulated to 4.7K Ω, so that the levels of the LP _ P connection port and the LP _ N connection port at both ends of the MIPI control chip 10 are not affected by each other, mutual interference is avoided.
Step S30, when the MIPI control chip 10 detects that the operation mode of the camera is the high-speed mode, the MIPI control chip 10 configures the register 20 in the second configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the second impedance resistor.
Finally, in this step, the MIPI control chip 10 can transmit the configuration protocol pre-programmed therein to the register 20 through the SCL connection port 11 and the SDA connection port 12, so that the register 20 is in the second configuration state, that is, the register 20 is configured in the 10 state, and at the same time, the resistance values of the first pull-up resistor 13 and the second pull-up resistor 14 are adjusted from 4.7K Ω to 150 Ω, so that the levels of the LP _ P connection port and the LP _ N connection port at both ends of the MIPI control chip 10 are not affected, and the mutual interference is avoided, so as to meet the level standard of the LVDS of the camera in the high speed mode.
By the method, the camera can be stably switched between the low-voltage mode and the high-speed mode, and the phenomenon that the high level can only be pulled to a half-high state is eliminated.
In summary, the MIPI resistor network system and method provided in the embodiments of the present invention electrically connect the MIPI control chip 10 and the register 20 together through the integrated circuit bus interface, the MIPI control chip 10 can receive the MIPI signal sent by the camera, and accurately detect that the current camera is in the low-voltage mode or the high-speed mode according to the current MIPI signal, and meanwhile, the MIPI control chip 10 can configure the working state of the register 20 correspondingly, and modulate the impedance resistor in the system into a corresponding resistance value correspondingly, so that the MIPI resistor network can be switched between the low-voltage mode and the high-speed mode stably, the phenomenon that the internal high level of the MIPI resistor network can only be pulled to the half-high state is avoided, and the stability of data transmission is ensured.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
It is obvious that the drawings in the following description are only examples or embodiments of the present application, and that it is also possible for a person skilled in the art to apply the present application to other similar contexts on the basis of these drawings without inventive effort. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An MIPI resistance network system is characterized by comprising an MIPI control chip and a register, wherein the MIPI control chip is provided with an integrated circuit bus interface and is used for receiving an MIPI signal sent by a camera and detecting the working mode of the camera according to the MIPI signal sent by the camera;
the register is used for:
when the MIPI control chip detects that the working mode of the camera is a low-voltage mode, the MIPI control chip configures the register to be in a first configuration state through the integrated circuit bus interface so as to modulate an impedance resistor matched with the MIPI resistor network system into a first impedance resistor; or
When the MIPI control chip detects that the working mode of the camera is a high-speed mode, the MIPI control chip configures the register to be in a second configuration state through the integrated circuit bus interface so as to modulate an impedance resistor matched with the MIPI resistor network system into a second impedance resistor, wherein the second impedance resistor is larger than the first impedance resistor.
2. The MIPI resistive network system of claim 1, wherein: the MIPI control chip is electrically connected with the register through the integrated circuit bus interface, and the integrated circuit bus interface comprises a control line port and a data line port.
3. The MIPI resistive network system of claim 2, wherein: the data line port is electrically connected with a first pull-up resistor, the control line port is electrically connected with a second pull-up resistor, the first pull-up resistor is connected with the second pull-up resistor in parallel, and the input ends of the first pull-up resistor and the second pull-up resistor are externally connected with a power supply.
4. The MIPI resistive network system of claim 1, wherein: the camera comprises a camera module and a connector, wherein one end of the connector is electrically connected with the camera module, and the other end of the connector is electrically connected with the connector;
the camera module is electrically connected with the connector through a video data transmission port and a data clock port.
5. The MIPI resistive network system of claim 4, wherein: the PCLK connection port electric connection of camera module has first resistance, the clock input signal port electric connection of connector has the second resistance, just the equal electric connection of ground connection port and the power connection port of connector has first electric capacity.
6. The MIPI resistive network system of claim 1, wherein: the MIPI control chip comprises a filtering module, one end of the filtering module is grounded, and the other end of the filtering module is connected with a power supply and a power supply connection port of the MIPI control chip.
7. The MIPI resistive network system of claim 6, wherein: the filter module comprises a plurality of second capacitors connected in parallel, one end of each second capacitor is grounded, and the other end of each second capacitor is connected with the power supply and the power supply connection port of the MIPI control chip.
8. The MIPI resistive network system of claim 1, wherein: the MIPI control chip is electrically connected with a third resistor, and the output end of the third resistor is grounded.
9. The MIPI resistive network system of claim 1, wherein: and a camera reset connecting port of the MIPI control chip and an integrated circuit reset connecting port are both connected with a fourth resistor.
10. A MIPI resistive network transmission method applied to the MIPI resistive network system of claim 1, the method comprising:
the MIPI control chip receives an MIPI signal sent by the camera and detects the running mode of the camera according to the MIPI signal;
when the MIPI control chip detects that the running mode of the camera is the low-voltage mode, the MIPI control chip configures the register to be in the first configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the first impedance resistor;
and when the MIPI control chip detects that the running mode of the camera is the high-speed mode, the MIPI control chip configures the register to be in the second configuration state through the integrated circuit bus interface, and modulates the impedance resistor matched with the MIPI resistor network system into the second impedance resistor.
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| US20140085353A1 (en) * | 2011-06-17 | 2014-03-27 | Sharp Kabushiki Kaisha | Semiconductor integrated device, display device, and debugging method for semiconductor integrated device |
| US20150130822A1 (en) * | 2013-11-13 | 2015-05-14 | Jae Chul Lee | Timing controller, display system including the same, and method of use thereof |
| US20180005597A1 (en) * | 2016-06-30 | 2018-01-04 | Aruna Kumar | Edp mipi dsi combination architecture |
| CN108292990A (en) * | 2015-12-11 | 2018-07-17 | 索尼公司 | Communication system and communication means |
| WO2020239109A1 (en) * | 2019-05-29 | 2020-12-03 | 深圳市紫光同创电子有限公司 | Mipi d-phy transmission circuit and device |
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2021
- 2021-12-23 CN CN202111594458.0A patent/CN114286034A/en active Pending
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|---|---|---|---|---|
| US20050253622A1 (en) * | 2004-05-13 | 2005-11-17 | International Business Machines Corporation | Circuit for generating a tracking reference voltage |
| US20090153219A1 (en) * | 2007-12-17 | 2009-06-18 | Charles Qingle Wu | Replica bias circuit for high speed low voltage common mode driver |
| US20140085353A1 (en) * | 2011-06-17 | 2014-03-27 | Sharp Kabushiki Kaisha | Semiconductor integrated device, display device, and debugging method for semiconductor integrated device |
| US20150130822A1 (en) * | 2013-11-13 | 2015-05-14 | Jae Chul Lee | Timing controller, display system including the same, and method of use thereof |
| CN108292990A (en) * | 2015-12-11 | 2018-07-17 | 索尼公司 | Communication system and communication means |
| US20180005597A1 (en) * | 2016-06-30 | 2018-01-04 | Aruna Kumar | Edp mipi dsi combination architecture |
| WO2020239109A1 (en) * | 2019-05-29 | 2020-12-03 | 深圳市紫光同创电子有限公司 | Mipi d-phy transmission circuit and device |
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