CN116561034A - FPGA interface circuit and method for realizing MIPI output interface and data transmission system - Google Patents

FPGA interface circuit and method for realizing MIPI output interface and data transmission system Download PDF

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Publication number
CN116561034A
CN116561034A CN202310639303.7A CN202310639303A CN116561034A CN 116561034 A CN116561034 A CN 116561034A CN 202310639303 A CN202310639303 A CN 202310639303A CN 116561034 A CN116561034 A CN 116561034A
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interface
resistor
pin
pull
fpga
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王磊
贾红
韦嶔
张红荣
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Wuxi Zhiduojing Microelectronics Co ltd
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Wuxi Zhiduojing Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses an FPGA interface circuit for realizing MIPI output interface, a method and a data transmission system, wherein the interface circuit comprises: the voltage division resistor comprises an FPGA, two voltage division resistor units, two first pull-down resistor units and two second pull-down resistor units; one end of the voltage dividing resistor unit is connected with a first I/O interface of the FPGA, the other end of the voltage dividing resistor unit is connected with a first pin corresponding to a third I/O interface of the FPGA, one end of the first pull-down resistor unit and one end of the second pull-down resistor unit are both connected with the first pin, and the other end of the first pull-down resistor unit and one end of the second pull-down resistor unit are both connected with a ground end; one end of the other voltage dividing resistor unit is connected with a second I/O interface of the FPGA, the other end of the other voltage dividing resistor unit is connected with a second pin corresponding to a fourth I/O interface of the FPGA, one end of the other first pull-down resistor unit and one end of the other second pull-down resistor unit are both connected with the second pin, and the other end of the other first pull-down resistor unit and the other end of the other second pull-down resistor unit are both connected with a ground end; by configuring the first I/O interface and the second I/O interface as lvcmosd differential output interfaces or as single-ended lvcmos output interfaces, signals conforming to MIPI high-speed or low-speed modes are output.

Description

FPGA interface circuit and method for realizing MIPI output interface and data transmission system
Technical Field
The invention belongs to the technical field of FPGA, and particularly relates to an FPGA interface circuit for realizing an MIPI output interface, a method and a data transmission system.
Background
MIPI (Mobile industry processor interface) is an open standard and specification established by MIPI alliance for mobile application processors, is a mainstream high-speed image transmission mode at present, and is mainly applied to data transmission between an image sensor and a processor (CSI interface) and between the processor and a display (DSI interface). The CSI interface and the DSI interface adopt a physical layer link named as D-PHY for transmission, and the interfaces are standardized, so that the design flexibility is improved, and meanwhile, the cost, the design complexity, the power consumption and the EMI are reduced. The D-PHY includes: HS-TX, LP-TX, HS-RX, LP-RX. The MIPI interface uses two signals for transmission, and the MIPI interface transmission MODEs are divided into two types, i.e., a high-speed transmission MODE (HS MODE) and a low-power transmission MODE (LP MODE). When the MIPI is transmitted at high speed, the two paths of signals are equivalent to a high-speed differential interface, and can transmit low-voltage differential signals up to 500 Mhz. When MIPI carries out low-power transmission, the two paths of signals are equivalent to LVCMOS12 standard interfaces, and the low-speed signals with the amplitude of 1.2v are transmitted.
At present, for the communication between the FPGA and the MIPI interface, two modes are generally adopted, one mode adopts a bridge chip such as MC20001, MC20901 and the like of Meticom company, and the other mode realizes that the output signal of the FPGA is converted into the MIPI interface signal through an off-chip resistor network, such as Lattice, xilinx manufacturer.
However, no matter the resistor network is built off-chip or the bridge chip is adopted to realize the MIPI interface, the cost is inevitably increased, and the problem that the FPGA is compatible with the MIPI interface cannot be solved.
Disclosure of Invention
In order to solve the problems in the related art, the invention provides an FPGA interface circuit, a method and a data transmission system for realizing an MIPI output interface. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides an FPGA interface circuit for realizing an MIPI output interface, which comprises:
the voltage division resistor comprises an FPGA, two voltage division resistor units, two first pull-down resistor units and two second pull-down resistor units; one end of a voltage dividing resistor unit is connected with a first I/O interface of the FPGA, the other end of the voltage dividing resistor unit is connected with a first pin corresponding to a third I/O interface of the FPGA, one end of a first pull-down resistor unit and one end of a second pull-down resistor unit are both connected with the first pin, and the other end of the first pull-down resistor unit and one end of the second pull-down resistor unit are both connected with a ground end; one end of the other voltage dividing resistor unit is connected with a second I/O interface of the FPGA, the other end of the other voltage dividing resistor unit is connected with a second pin corresponding to a fourth I/O interface of the FPGA, one end of the other first pull-down resistor unit and one end of the other second pull-down resistor unit are both connected with the second pin, and the other end of the other first pull-down resistor unit and the other end of the other second pull-down resistor unit are both connected with a ground end;
when the first I/O interface and the second I/O interface are configured as an lvcmos d differential output interface and the lvcmos d differential output interface, the two voltage dividing resistor units and the two first pull-down resistor units are enabled, outputting high-speed differential signals conforming to an MIPI high-speed transmission mode through the first pin and the second pin;
when the first I/O interface and the second I/O interface are configured to be single-ended lvcmos output interfaces and the single-ended lvcmos output interfaces, the two voltage dividing resistor units and the two second pull-down resistor units are enabled, independent low-speed signals conforming to an MIPI low-speed transmission mode are output through the first pin and the second pin.
In some embodiments, each voltage dividing resistance unit includes: the first switch is connected with the first resistor in series, one end of the first switch, which is not connected with the first resistor, is connected with a corresponding I/O interface, and one end of the first resistor, which is not connected with the first switch, is connected with a corresponding pin.
In some embodiments, each first pull-down resistance unit includes: a second switch and a second resistor; the second switch is connected in series with the second resistor, one end of the second switch, which is not connected with the second resistor, is connected with a ground terminal, and one end of the second switch, which is not connected with the second resistor, is connected with a corresponding I/O interface.
In some embodiments, each of the second pull-down resistance units includes: a third switch and a third resistor; the third switch is connected in series with the third resistor, one end of the third switch, which is not connected with the third resistor, is connected with a ground terminal, and one end of the third switch, which is not connected with the third resistor, is connected with a corresponding pin.
In some embodiments, the first resistance, the second resistance, and the third resistance are calculated as:
R 1 ＝5R 2 ＝R 3 ；
wherein R is 1 Represents a first resistance, R 2 Represents a second resistance, R 3 Representing a third resistance; v (V) com The common mode voltage of the LVCMOS differential interface is represented, and the unit is V; i load The differential output driving current required by the MIPI protocol is expressed as mA, and r represents the internal resistance of a single-path I/O of the lvcmos differential output interface; r is R 1 、R 2 、R 3 And r are all in Ω.
In some embodiments, the first resistor and the second resistor are used for dividing voltage when outputting the high-speed differential signal; the first resistor and the third resistor are used for dividing voltage when the low-speed signal is output.
In some embodiments, the first I/O interface corresponds to a third pin and the second I/O interface corresponds to a fourth pin; when the two pull-down resistor units, the two first pull-down resistor units and the two second pull-down resistor units are turned off, the first I/O interface is further used for outputting a first I/O signal through the third pin, the second I/O interface is further used for outputting a second I/O signal through the fourth pin, the third I/O interface is used for outputting a third I/O signal through the first pin, and the fourth I/O interface is used for outputting a fourth I/O signal through the second pin.
In some embodiments, the first pin and the second pin belong to the same QUAD of the FPGA.
The invention also provides a method for realizing the MIPI output interface, which comprises the following steps:
when a pair of lvcmos differential output interfaces in the FPGA chip, two voltage dividing resistor units and two first pull-down resistor units in the FPGA chip are enabled, outputting a high-speed differential signal conforming to an MIPI high-speed transmission mode through a first pin corresponding to one I/O interface and a second pin corresponding to the other I/O interface in the FPGA chip;
when two single-ended lvcmos output interfaces in the FPGA chip, the two voltage dividing resistor units and the two second pull-down resistor units in the FPGA chip are enabled, respectively outputting independent low-speed signals conforming to an MIPI low-speed transmission mode through the first pin and the second pin.
The invention also provides a data transmission system, which comprises a data output device and a data receiving device; the data output device comprises the FPGA interface circuit; the data output device is connected with the data receiving device through the first pin and the second pin.
The invention has the following beneficial technical effects:
on the basis of not changing the original I/O interface of the FPGA, the pull-down resistor unit and the voltage dividing resistor unit are connected with a high-speed LVCMOS differential interface in the FPGA IOS to realize the MIPI interface, the MIPI enable signal is controlled to enable the MIPI interface circuit, and the MIPI MODE control signal is controlled to realize HS MODE or LP MODE signal transmission, so that the requirement of the FPGA universal interface is not required to be changed, the attribute of two I/O interfaces of the FPGA is simultaneously switched by using the signal for controlling high-speed switching, the output of the MIPI signal can be realized in the FPGA chip, the problem of high-speed and low-speed switching time sequence of the MIPI is avoided, the MIPI interface is compatible in the FPGA, the use of the universal I/O interface of the FPGA is not influenced, the resource utilization is less, the circuit is simple, and the utilization rate of the I/O interface of the FPGA is high.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic circuit diagram of an FPGA interface circuit for implementing an MIPI output interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another circuit structure of an exemplary FPGA interface circuit for implementing an MIPI output interface according to an embodiment of the present invention;
fig. 3 is a schematic diagram of still another circuit configuration of an exemplary FPGA interface circuit for implementing an MIPI output interface according to an embodiment of the present invention;
fig. 4 is a schematic diagram of still another circuit structure of an exemplary FPGA interface circuit for implementing an MIPI output interface according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for implementing an MIPI output interface according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a data transmission system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Fig. 1 is a schematic circuit structure diagram of an FPGA interface circuit for implementing an MIPI output interface according to an embodiment of the present invention, as shown in fig. 1, where the circuit includes: the FPGA comprises an FPGA IOS (representing all I/O interfaces of the FPGA), wherein the FPGA IOS comprises a first I/O interface (pad a in fig. 1), a second I/O interface (pad b in fig. 1), a third I/O interface (pad c in fig. 1) and a fourth I/O interface (pad d in fig. 1); the first I/O interface unit corresponds to pin PAD A (referred to as the third pin), the second I/O interface unit corresponds to pin PAD B (referred to as the fourth pin), the third I/O interface unit corresponds to pin PAD C (referred to as the first pin), and the fourth I/O interface unit corresponds to pin PAD D (referred to as the second pin). Specifically, one end of a voltage dividing resistor unit is connected with a first I/O interface of the FPGA, the other end of the voltage dividing resistor unit is connected with a pin PAD C corresponding to a third I/O interface of the FPGA, one end of a first pull-down resistor unit and one end of a second pull-down resistor unit are both connected with the pin PAD C, and the other end of the first pull-down resistor unit and the other end of the second pull-down resistor unit are both connected with a ground end; one end of the other voltage dividing resistor unit is connected with a second I/O interface of the FPGA, the other end of the voltage dividing resistor unit is connected with a pin PAD, one ends of the other first pull-down resistor unit and the other second pull-down resistor unit are connected with the pin PAD, and the other ends of the other first pull-down resistor unit and the other second pull-down resistor unit are connected with a ground terminal.
In some embodiments, pin PAD A, pin PAD B, pin PAD C, and pin PAD D belong to the same QUAD of the FPGA. A QUAD includes 4 groups of GT high-speed transceivers, a BANK includes IO interfaces as many interface standards, and the QUAD is a part of the BANK. The IO interfaces of the FPGA are divided into a plurality of groups (BANK), the interface standard of each BANK is determined by the interface Voltage (VCCO) of each BANK, one BANK can only have one VCCO, and the VCCOs of different BANK can be different. Only ports of the same electrical standard can be connected together, VCCO being the same as the basic condition of the interface standard.
As shown in fig. 2, when the first I/O interface and the second I/O interface are configured as a pair of lvcmos D differential output interfaces, and the lvcmos D differential output interfaces, two voltage dividing resistance units (denoted by W in fig. 2), and two first pull-down resistance units (included in Q in fig. 2) are enabled, high-speed differential signals conforming to the MIPI high-speed transmission mode are output through the pin PAD C and the pin PAD D.
As shown in fig. 3, when the first I/O interface and the second I/O interface are each configured as a single-ended lvcmos output interface, and the single-ended lvcmos output interface, two voltage dividing resistance units (denoted by W in fig. 3), and two second pull-down resistance units (included in Q in fig. 3) are enabled, independent low-speed signals conforming to the MIPI low-speed transmission mode are output through the pin PAD C and the pin PAD D.
In the present application, lvcmosd and lvcmos are implemented through dynamic configuration of a transmission mode of an MIPI, and a control signal is used to switch between a high-speed transmission mode and a low-speed transmission mode of the MIPI, and switching between an I/O configuration mode is performed through the control signal.
In some embodiments, each voltage dividing resistance unit includes: the first switch and the first resistor are connected in series, one end of the first switch, which is not connected with the first resistor, is connected with the corresponding I/O interface, and one end of the first resistor, which is not connected with the first switch, is connected with the corresponding pin.
In some embodiments, each first pull-down resistance unit includes: a second switch and a second resistor; the second switch is connected in series with the second resistor, and one end of the second switch, which is not connected with the second resistor, is connected with the ground terminal, and one end of the second switch, which is not connected with the second resistor, is connected with the corresponding I/O interface.
In some embodiments, each of the second pull-down resistance units includes: a third switch and a third resistor; the third switch is connected in series with the third resistor, and one end of the third switch, which is not connected with the third resistor, is connected with the ground terminal, and one end of the third switch, which is not connected with the third resistor, is connected with the corresponding pin.
Exemplary, the interface circuit shown in FIG. 4 includes a first I/O interface, a second I/O interface, a third I/O interface, and a fourth I/O interface, wherein the first I/O interface, the second I/O interface are configured as a pair of lvcmos differential output interfaces (e.g., lvcmos25d, etc.), and a first switch S 1 And a first resistor R 1 In series, a first switch S 1 Is not with R 1 One end of the connection is respectively connected with the pin PAD A and the pin PAD B, R 1 Is not in contact with S 1 One end of the connection is respectively connected with the pin PAD C and the pin PAD D. Second switch S 2 And a second resistor R 2 In series, and S 2 Is not with R 2 One end of the connection is grounded, R 2 Is not in contact with S 2 One end connected with not only the resistor R 1 And the connection is also connected with the pin PAD C and the pin PAD D respectively. As shown in FIG. 4, when the third I/O interface and the fourth I/O interface corresponding to PAD C and pin PAD D are turned off, and the lvcmosd differential output interface is enabled, and S is enabled 1 And S is 2 Closing to S 3 R when disconnected 1 And R is 2 And performing voltage division, wherein a first I/O interface and a second I/O interface of the FPGA enter an HS MODE MODE of the MIPI, and high-speed differential signals conforming to the MIPI high-speed transmission MODE are output through a pin PAD C and a pin PAD.
When the first I/O interface and the second I/O interface are configured as single-ended lvcmos output interfaces, and the third I/O interface and the fourth I/O interface corresponding to the PAD C and the pin PAD D are turned off, enabling the two single-ended lvcmos output interfaces, and enabling S 1 、S 3 Closing, S 2 R when disconnected 1 And R is 3 Dividing voltage, enabling a first I/O interface and a second I/O interface of the FPGA to enter an LP MODE of MIPI, and outputting two paths of independent signals through PAD C and pin PAD DIs in compliance with the MIPI low-speed transmission mode.
In some embodiments, the first resistance, the second resistance, and the third resistance are calculated as:
R 1 ＝5R 2 ＝R 3 ；
wherein R is 1 Represents a first resistance, R 2 Represents a second resistance, R 3 Representing a third resistance; v (V) com The common mode voltage of the LVCMOS differential interface is represented, and the unit is V; i load The differential output driving current required by the MIPI protocol is expressed as mA, and r represents the internal resistance of a single-path I/O of the lvcmos differential output interface; r is R 1 、R 2 、R 3 And r are all in Ω.
In some embodiments, when S is opened 1 、S 2 、S 3 When the two pull-down resistor units, the two first pull-down resistor units and the two second pull-down resistor units are stopped to be turned off, the first I/O interface, the second I/O interface, the third I/O interface and the fourth I/O interface can be used as independent general I/Os, so that the first I/O interface can output a first I/O signal through the PAD A, the second I/O interface can also output a second I/O signal through the PAD B, the third I/O interface can output a third I/O signal through the PAD C, and the fourth I/O interface can output a fourth I/O signal through the PAD D.
According to the invention, on the basis of not changing the original I/O interface of the FPGA, the pull-down resistor unit and the voltage dividing resistor unit are connected with the high-speed LVCMOS differential interface in the FPGA IOS to realize the MIPI interface, the MIPI enable signal is controlled to enable the MIPI interface circuit, and the HS MODE or LP MODE signal transmission is realized by controlling the MIPI MODE control signal, so that the requirement of the FPGA universal interface is not required to be changed, the attribute of two I/O interfaces of the FPGA is simultaneously switched by only using the signal for controlling high-speed switching, the output of the MIPI signal can be realized in the FPGA chip, the problem of high-speed and low-speed switching time sequence of the MIPI is avoided, the FPGA is compatible with the MIPI interface, the use of the universal I/O interface of the FPGA is not influenced, the resource utilization is less, the circuit is simple, and the I/O interface of the FPGA has high utilization rate.
As shown in fig. 5, the present invention further provides a method for implementing an MIPI output interface, which may be applied to the FPGA interface circuit, where the method includes:
s1, when a pair of lvcmos differential output interfaces in an FPGA (field programmable gate array) chip, two voltage dividing resistor units and two first pull-down resistor units in the FPGA chip are enabled, outputting a high-speed differential signal conforming to an MIPI high-speed transmission mode through a first pin corresponding to one I/O interface and a second pin corresponding to the other I/O interface in the FPGA chip.
S2, when two single-end lvcmos output interfaces in the FPGA chip, two voltage dividing resistor units and two second pull-down resistor units in the FPGA chip are enabled, respectively outputting independent low-speed signals conforming to the MIPI low-speed transmission mode through the first pin and the second pin.
As shown in fig. 6, the present invention further provides a data transmission system, which includes a data output device and a data receiving device; the data output device comprises the FPGA interface circuit; the data output device is connected with the data receiving device through the first pin and the second pin.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. An FPGA interface circuit for implementing an MIPI output interface, comprising:
the voltage division resistor comprises an FPGA, two voltage division resistor units, two first pull-down resistor units and two second pull-down resistor units; one end of a voltage dividing resistor unit is connected with a first I/O interface of the FPGA, the other end of the voltage dividing resistor unit is connected with a first pin corresponding to a third I/O interface of the FPGA, one end of a first pull-down resistor unit and one end of a second pull-down resistor unit are both connected with the first pin, and the other end of the first pull-down resistor unit and one end of the second pull-down resistor unit are both connected with a ground end; one end of the other voltage dividing resistor unit is connected with a second I/O interface of the FPGA, the other end of the other voltage dividing resistor unit is connected with a second pin corresponding to a fourth I/O interface of the FPGA, one end of the other first pull-down resistor unit and one end of the other second pull-down resistor unit are both connected with the second pin, and the other end of the other first pull-down resistor unit and the other end of the other second pull-down resistor unit are both connected with a ground end;
when the first I/O interface and the second I/O interface are configured as an lvcmos d differential output interface and the lvcmos d differential output interface, the two voltage dividing resistor units and the two first pull-down resistor units are enabled, outputting high-speed differential signals conforming to an MIPI high-speed transmission mode through the first pin and the second pin;
when the first I/O interface and the second I/O interface are configured to be single-ended lvcmos output interfaces and the single-ended lvcmos output interfaces, the two voltage dividing resistor units and the two second pull-down resistor units are enabled, independent low-speed signals conforming to an MIPI low-speed transmission mode are output through the first pin and the second pin.
2. The FPGA interface circuit for implementing an MIPI output interface according to claim 1, wherein each voltage dividing resistor unit comprises: the first switch is connected with the first resistor in series, one end of the first switch, which is not connected with the first resistor, is connected with a corresponding I/O interface, and one end of the first resistor, which is not connected with the first switch, is connected with a corresponding pin.
3. The FPGA interface circuit for implementing an MIPI output interface according to claim 1, wherein each first pull-down resistor unit comprises: a second switch and a second resistor; the second switch is connected in series with the second resistor, one end of the second switch, which is not connected with the second resistor, is connected with a ground terminal, and one end of the second switch, which is not connected with the second resistor, is connected with a corresponding I/O interface.
4. The FPGA interface circuit for implementing an MIPI output interface according to claim 1, wherein each second pull-down resistor unit comprises: a third switch and a third resistor; the third switch is connected in series with the third resistor, one end of the third switch, which is not connected with the third resistor, is connected with a ground terminal, and one end of the third switch, which is not connected with the third resistor, is connected with a corresponding pin.
5. The FPGA interface circuit for implementing an MIPI output interface according to any one of claims 1-3, wherein the first resistor, the second resistor and the third resistor are calculated as:
R 1 ＝5R 2 ＝R 3 ；
wherein R is 1 Represents a first resistance, R 2 Represents a second resistance, R 3 Representing a third resistance; v (V) com The common mode voltage of the LVCMOS differential interface is represented, and the unit is V; i load The differential output driving current required by the MIPI protocol is expressed as mA, and r represents the internal resistance of a single-path I/O of the lvcmos differential output interface; r is R 1 、R 2 、R 3 And r are all in Ω.
6. An FPGA interface circuit for implementing an MIPI output interface according to any one of claims 1-3, wherein the first resistor and the second resistor are used for voltage division when outputting the high speed differential signal; the first resistor and the third resistor are used for dividing voltage when the low-speed signal is output.
7. The FPGA interface circuit for implementing an MIPI output interface according to claim 1, wherein the first I/O interface corresponds to a third pin and the second I/O interface corresponds to a fourth pin; when the two pull-down resistor units, the two first pull-down resistor units and the two second pull-down resistor units are turned off, the first I/O interface is further used for outputting a first I/O signal through the third pin, the second I/O interface is further used for outputting a second I/O signal through the fourth pin, the third I/O interface is used for outputting a third I/O signal through the first pin, and the fourth I/O interface is used for outputting a fourth I/O signal through the second pin.
8. The FPGA interface circuit for implementing an MIPI output interface according to claim 1, wherein the first pin and the second pin belong to the same QUAD of the FPGA.
9. A method for implementing an MIPI output interface, comprising:
when a pair of lvcmos differential output interfaces in the FPGA chip, two voltage dividing resistor units and two first pull-down resistor units in the FPGA chip are enabled, outputting a high-speed differential signal conforming to an MIPI high-speed transmission mode through a first pin corresponding to one I/O interface and a second pin corresponding to the other I/O interface in the FPGA chip;
when two single-ended lvcmos output interfaces in the FPGA chip, the two voltage dividing resistor units and the two second pull-down resistor units in the FPGA chip are enabled, respectively outputting independent low-speed signals conforming to an MIPI low-speed transmission mode through the first pin and the second pin.
10. A data transmission system comprising a data output device and a data receiving device; the data output device comprises an FPGA interface circuit according to any one of claims 1 to 8; the data output device is connected with the data receiving device through the first pin and the second pin.
CN202310639303.7A 2023-05-31 2023-05-31 FPGA interface circuit and method for realizing MIPI output interface and data transmission system Pending CN116561034A (en)

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