CN115866156B - Data processing method, device, electronic equipment and storage medium - Google Patents
Data processing method, device, electronic equipment and storage medium Download PDFInfo
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Abstract
The present disclosure provides a data processing method, apparatus, electronic device, and storage medium, the method and apparatus being applied to an image output module for displaying data or transmitting image data, the method comprising: confirming a protocol corresponding to data to be generated; outputting the data to be generated from a unique target port of the image output module based on a timing control signal and the protocol; wherein the protocol comprises a display serial interface protocol or a camera serial interface protocol; therefore, one module can simultaneously support two protocols, and function repetition and resource waste are avoided.
Description
Technical Field
The disclosure relates to the technical field of data processing, and in particular relates to a data processing method, a data processing device, electronic equipment and a storage medium.
Background
A display serial interface (Display Serial Interface, DSI) for display, a camera serial interface (Camera Serial Interface, CSI) for transmitting image data, both of which are not used at the same time; in order to support the DSI protocol and the CSI protocol, two separate modules need to be developed, resulting in functional repetition and resource waste.
Disclosure of Invention
The present disclosure provides a data processing method, apparatus, electronic device, and storage medium, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a data processing method applied to an image output module for displaying data or transmitting image data, the method comprising:
confirming a protocol corresponding to data to be generated;
outputting the data to be generated from a unique target port of the image output module based on a timing control signal and the protocol;
wherein the protocol includes a display serial interface protocol or a camera serial interface protocol.
According to a second aspect of the present disclosure, there is provided a data processing apparatus comprising an image output module for displaying data or transmitting image data, the apparatus comprising:
the judging module is used for confirming a protocol corresponding to the data to be generated;
the output module is used for outputting the data to be generated based on a time sequence control signal and the protocol;
wherein the protocol includes a display serial interface protocol or a camera serial interface protocol.
According to a third aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.
According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present disclosure.
The data processing method is applied to an image output module for displaying data or transmitting image data, and a protocol corresponding to the data to be generated is confirmed; outputting the data to be generated based on a time sequence control signal and the protocol; wherein the protocol comprises a display serial interface protocol or a camera serial interface protocol; therefore, one module (namely the image output module) can simultaneously support two protocols, and the function repetition and the resource waste are avoided.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 illustrates an alternative flow diagram of a data processing method provided by an embodiment of the present disclosure;
FIG. 2 shows another alternative flow diagram of a data processing method provided by an embodiment of the present disclosure;
FIG. 3 shows a schematic diagram of a module configuration in a chip provided by an embodiment of the disclosure;
FIG. 4 is a schematic diagram of generating a vertical direction data packet according to a timing control signal provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of generating a horizontal direction packet according to a timing control signal provided by an embodiment of the present disclosure;
FIG. 6 shows an alternative architecture diagram of a data processing apparatus provided by an embodiment of the present disclosure;
fig. 7 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
DSI is used for image output, such as a screen of an electronic device, and CSI is used for image access, such as an image sensor, a camera, and the like; in the related art, DSI and CSI are two independent and completely uncorrelated interfaces, and implementation requires two D-PHYs (a physical layer) to be configured separately, which is costly.
In addition, since DSI is used for display and CSI is used for transmitting image data to other electronic devices or system on a chip (SoC), both are not generally used at the same time, and two different modules (IPs) are required to support both protocols, which may cause functional duplication and resource waste.
Based on the defects in the related art, the present disclosure provides a data processing method, which can enable one module (interface) to simultaneously support two protocols, DSI and CSI, so as to solve some or all of the above technical problems.
Fig. 1 shows an alternative flowchart of a data processing method according to an embodiment of the present disclosure, and will be described according to the steps.
The data processing method provided by the embodiment of the disclosure is applied to an image output module, and the image output module is used for displaying data or transmitting image data; specifically, the image output module may output DSI protocol data when used for displaying data, and may output CSI protocol data when used for transmitting image data.
Step S201, the protocol corresponding to the data to be generated is confirmed.
In some embodiments, an execution carrier (hereinafter referred to as an execution carrier) of the data processing method confirms a protocol corresponding to data to be generated based on the instruction information stored in the register. The indication information is used for indicating a protocol corresponding to the data to be generated, and may be at least one of a chinese full name, an english full spelling or an abbreviation of the protocol, or may refer to a symbol of the protocol, for example, DSI protocol is 0, CSI protocol is 1, DSI protocol is a, CSI protocol is b, etc., which is not specifically limited in this disclosure.
In some embodiments, the protocol includes a display serial interface protocol or a camera serial interface protocol, and after the device confirms the protocol, the data to be generated corresponding to the protocol is generated.
Step S202, outputting the data to be generated from the unique target port of the image output module based on the timing control signal and the protocol.
In some embodiments, the timing control signals include a control signal in a vertical direction and a control signal in a horizontal direction, the vertical direction including a vertical synchronization sub-signal, a vertical synchronization sub-signal front shoulder, and a vertical resolution sub-signal; the horizontal direction includes a horizontal synchronization sub-signal, a horizontal synchronization sub-signal front shoulder, and a horizontal resolution sub-signal.
In some embodiments, the data to be generated comprises at least one data packet; unlike the related art, the at least one data packet is output from a unique destination port included in the image output module. The specific application of the image output module or the data protocol can be determined according to the indication information stored in the register, and it should be noted that the application of the image output module is not fixed and can be switched based on the indication information, such as switching from display data to transmission image data or switching from transmission image data to display data; accordingly, the protocol of the output data is switched from the DSI protocol to the CSI protocol or from the CSI protocol to the DSI protocol.
In some embodiments, the execution carrier outputs the data to be generated based on the destination port. Optionally, the execution carrier sends the data to be generated to an underlying protocol layer (Low Level Protocol) through which the data is sent to the target port; wherein the target port is a physical port.
In this way, by the data processing method provided by the embodiment of the present disclosure, DSI protocols and CSI protocols that need to be respectively supported by two modules in the related art are optimized to be supported by one module, and when output data is different, the function that the module is used for outputting DSI protocol data or CSI protocol data can be implemented by confirming the protocol corresponding to the data based on the indication information in the register, so that function repetition and resource waste are avoided.
FIG. 2 shows another alternative flow diagram of a data processing method provided by an embodiment of the present disclosure; FIG. 3 shows a schematic diagram of a module configuration in a chip provided by an embodiment of the disclosure; fig. 4 is a schematic diagram illustrating generation of a vertical direction packet according to a timing control signal provided by an embodiment of the present disclosure, and fig. 5 is a schematic diagram illustrating generation of a horizontal direction packet according to a timing control signal provided by an embodiment of the present disclosure.
In some embodiments, as shown in fig. 3, the data processing method provided in the embodiments of the present disclosure is applied to an image output module, where the image output module is used for displaying data or transmitting image data; specifically, the image output module may output DSI protocol data when used for displaying data, and may output CSI protocol data when used for transmitting image data.
Step S301, the protocol corresponding to the data to be generated is confirmed.
In some embodiments, the execution carrier of the data processing method confirms a protocol corresponding to the data to be generated based on the instruction information stored in the register. The indication information is used for indicating a protocol corresponding to the data to be generated, and may be at least one of a chinese full name, an english full spelling or an abbreviation of the protocol, or may refer to a symbol of the protocol, for example, DSI protocol is 0, CSI protocol is 1, DSI protocol is a, CSI protocol is b, etc., which is not specifically limited in this disclosure.
In some embodiments, the protocol includes a display serial interface protocol or a camera serial interface protocol, and after the performing of the carrier confirmation protocol, if the protocol is a DSI protocol, step S302 is performed, or if the protocol is a CSI protocol, step S303 is performed.
Step S302, outputting data to be generated corresponding to the DSI protocol based on the time sequence control signal.
In some embodiments, as shown in fig. 4 and fig. 5, if the protocol is DSI, the data to be generated includes a vertical data packet and a horizontal data packet; the vertical DATA packets include a vertical synchronization start DATA packet (Vertical Sync Start, VSS), a vertical synchronization end DATA packet (Vertical Sync End, VSE), a second DATA packet (DT and DATA in the vertical DATA packet); the horizontal DATA packets include a horizontal synchronization start DATA packet (HSS), a horizontal synchronization end DATA packet (HVSE), a first DATA packet (DT and DATA in the horizontal DATA packet). The timing control signal, the vertical direction (vtotal) includes a vertical synchronization sub-signal (vsync), a vertical synchronization sub-signal front shoulder (vbp), a vertical resolution sub-signal (vactive), and a vertical synchronization sub-signal rear shoulder (vfp); the horizontal direction (htotal) includes a horizontal synchronization sub-signal (hsync), a horizontal synchronization sub-signal front shoulder (hbp), a horizontal resolution sub-signal (hactive), and a vertical synchronization sub-signal rear shoulder (hfp).
In particular, as shown in fig. 4 and 5, the execution carrier generates a vertical synchronization start packet (VSS) in response to receiving the vertical synchronization sub-signal (vsync); generating a vertical synchronization end packet (VSE) in response to receiving the vertical synchronization sub-signal front shoulder (vbp); in response to receiving the vertical resolution sub-signal (vactive), generating a second DATA packet (DT and DATA in the vertical DATA packet) of a resolution corresponding to the vertical resolution sub-signal; in response to receiving the horizontal synchronization sub-signal (hsync), generating a horizontal synchronization start data packet (HSS); generating a horizontal synchronization end packet (HSE) in response to receiving the horizontal synchronization sub-signal front shoulder (hbp); in response to receiving the horizontal resolution sub-signal (active), a first DATA packet (DT and DATA in the horizontal DATA packet) of a resolution corresponding to the horizontal resolution sub-signal is generated.
In some embodiments, the execution carrier further outputs the vertical synchronization start packet, the vertical synchronization end packet, the horizontal synchronization start packet, the horizontal synchronization end packet, and the first packet and the second packet corresponding to data based on a destination port. Optionally, the execution carrier may output the generated data packet based on the destination port after generating the data packet, or may output the generated data packet based on the destination port after all the data packets are generated and packaged. As shown in fig. 2, the data packet needs to pass through the underlying protocol layer and then be output from the destination port.
Step S303, outputting the data to be generated corresponding to the CSI protocol based on the time sequence control signal.
In some embodiments, as shown in fig. 4 and fig. 5, if the protocol is CSI, the data to be generated includes a frame data packet and a data packet; the Frame DATA packets include a Frame Start DATA packet (FS), a Frame End DATA packet (FE), and a third DATA packet (DT and DATA in the Frame DATA packet); the DATA packets include a line synchronization start packet (LS), a line synchronization end packet (LE), and a fourth packet (DT and DATA in the DATA packets). The timing control signal, the vertical direction includes a vertical synchronization sub-signal (vsync), a vertical synchronization sub-signal front shoulder (vbp), a vertical resolution sub-signal (vactive), and a vertical synchronization sub-signal rear shoulder (vfp); the horizontal direction includes a horizontal synchronization sub-signal (hsync), a horizontal synchronization sub-signal front shoulder (hbp), a horizontal resolution sub-signal (have), and a vertical synchronization sub-signal rear shoulder (hfp).
In particular, as shown in fig. 4 and 5, the execution carrier generates a frame synchronization end packet (FE) in response to receiving the vertical synchronization sub-signal (vsync); generating a frame sync start packet (FS) in response to receiving the vertical sync sub-signal front shoulder (vbp); in response to receiving the vertical resolution sub-signal (vactive), generating a third DATA packet (DT and DATA in the frame DATA packet) of a resolution corresponding to the vertical resolution sub-signal; in response to receiving the horizontal synchronization sub-signal (hsync), generating a line synchronization end packet (LE); generating a line sync start data packet (LS) in response to receiving the horizontal sync sub-signal front shoulder (hbp); in response to receiving the horizontal resolution sub-signal (active), a fourth DATA packet (DT and DATA in the horizontal DATA packet) of a resolution corresponding to the horizontal resolution sub-signal is generated.
In some embodiments, the execution carrier further outputs the frame sync start packet, the frame sync end packet, the line sync start packet, the line sync end packet, and the third and fourth packets corresponding to data based on a destination port. Optionally, the execution carrier may output the generated data packet based on the destination port after generating the data packet, or may output the generated data packet based on the destination port after all the data packets are generated and packaged. As shown in fig. 2, the data packet needs to pass through the underlying protocol layer and then be output from the destination port.
In this way, through the data processing method provided by the embodiment of the present disclosure, DSI protocols and CSI protocols that need to be respectively supported by two modules in the related art are optimized to be supported by one module, and based on the indication information acknowledgement protocol in the register, the function that the module is used for outputting DSI protocol data or CSI protocol data is implemented, so that function repetition and resource waste are avoided.
Fig. 6 is a schematic diagram showing an alternative configuration of a data processing apparatus provided in an embodiment of the present disclosure, which will be described in terms of the respective parts.
In some embodiments, the data processing apparatus 700 includes an image output module 703; the data processing apparatus 700 further comprises a judging module 701 and an output module 702.
A judging module 701, configured to confirm a protocol corresponding to data to be generated;
an output module 702 for outputting the data to be generated from the unique target port of the image output module 703 based on a timing control signal and the protocol;
wherein the protocol includes a display serial interface protocol or a camera serial interface protocol.
The judging module 701 is specifically configured to confirm a protocol corresponding to the data to be generated based on the indication information stored in the register.
The data to be generated includes at least one data packet, and the output module 702 is specifically configured to output, based on the timing control signal, a vertical synchronization start data packet, a vertical synchronization end data packet, a horizontal synchronization start data packet, a horizontal synchronization end data packet, and a first data packet and a second data packet corresponding to the data to be generated from the unique destination port of the image output module 703 if the protocol is a display serial interface protocol.
The output module 702 is specifically configured to generate a vertical synchronization start packet in response to receiving the vertical synchronization sub-signal;
generating a vertical synchronization end packet in response to receiving the vertical synchronization sub-signal front shoulder;
in response to receiving the vertical resolution sub-signal, generating a second data packet of a resolution corresponding to the vertical resolution sub-signal;
generating a horizontal synchronization start data packet in response to receiving the horizontal synchronization sub-signal;
generating a horizontal sync end packet in response to receiving the horizontal sync sub-signal front shoulder;
in response to receiving a horizontal resolution sub-signal, generating a first data packet of a resolution corresponding to the horizontal resolution sub-signal;
outputting the vertical synchronization start data packet, the vertical synchronization end data packet, the horizontal synchronization start data packet, the horizontal synchronization end data packet, and the first data packet and the second data packet corresponding to data based on a destination port.
The data to be generated includes at least one data packet, and the output module 702 is specifically configured to output, based on the timing control signal, a frame synchronization start data packet, a frame synchronization end data packet, a line synchronization start data packet, a line synchronization end data packet, and third and fourth data packets corresponding to the data to be generated if the protocol is a camera serial interface protocol.
The output module 702 is specifically configured to generate a frame synchronization end packet in response to receiving the vertical synchronization sub-signal;
generating a frame sync start packet in response to receiving the vertical sync sub-signal front shoulder;
in response to receiving the vertical resolution sub-signal, generating a third data packet of resolution corresponding to the vertical resolution sub-signal;
generating a line synchronization end data packet in response to receiving the horizontal synchronization sub-signal;
generating a line sync start packet in response to receiving the horizontal sync sub-signal front shoulder;
generating a fourth data packet of resolution corresponding to the horizontal resolution sub-signal in response to receiving the horizontal resolution sub-signal;
and outputting a frame synchronization start data packet, a frame synchronization end data packet, a line synchronization start data packet, a line synchronization end data packet, a third data packet and a fourth data packet corresponding to the data to be generated from a target port based on the time sequence control signal.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
Fig. 7 shows a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 7, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM802, and the RAM803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output module 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM802 and/or the communication unit 809. When a computer program is loaded into RAM803 and executed by computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (5)
1. A data processing method applied to an image output module for displaying data or transmitting image data, the method comprising:
switching the use of the image output module based on the indication information stored in the register, and confirming a protocol corresponding to data to be generated based on the use of the switched image output module;
the data to be generated comprises at least one data packet, and if the protocol is a display serial interface protocol, based on a time sequence control signal, the vertical synchronization start data packet, the vertical synchronization end data packet, the horizontal synchronization start data packet, the horizontal synchronization end data packet, the first data packet and the second data packet corresponding to the data to be generated are output from the unique target port of the image output module;
if the protocol is a camera serial interface protocol, outputting a frame synchronization start data packet, a frame synchronization end data packet, a line synchronization start data packet, a line synchronization end data packet, a third data packet and a fourth data packet corresponding to the data to be generated from a unique target port of the image output module based on the time sequence control signal;
in response to the timing control signal including a vertical synchronization sub-signal, a horizontal synchronization sub-signal, a vertical synchronization sub-signal front shoulder, a horizontal synchronization sub-signal front shoulder, a vertical resolution sub-signal, and a horizontal resolution sub-signal, the outputting, from the unique destination port of the image output module based on the timing control signal, a vertical synchronization start data packet, a vertical synchronization end data packet, a horizontal synchronization start data packet, a horizontal synchronization end data packet, and first and second data packets corresponding to the data to be generated, includes:
generating a vertical synchronization start data packet in response to receiving the vertical synchronization sub-signal;
generating a vertical synchronization end packet in response to receiving the vertical synchronization sub-signal front shoulder;
in response to receiving the vertical resolution sub-signal, generating a second data packet of a resolution corresponding to the vertical resolution sub-signal;
generating a horizontal synchronization start data packet in response to receiving the horizontal synchronization sub-signal;
generating a horizontal sync end packet in response to receiving the horizontal sync sub-signal front shoulder;
in response to receiving a horizontal resolution sub-signal, generating a first data packet of a resolution corresponding to the horizontal resolution sub-signal;
outputting the vertical synchronization start data packet, the vertical synchronization end data packet, the horizontal synchronization start data packet, the horizontal synchronization end data packet, and the first data packet and the second data packet corresponding to data based on a destination port.
2. The method according to claim 1, wherein outputting, based on the timing control signal, a frame synchronization start packet, a frame synchronization end packet, a line synchronization start packet, a line synchronization end packet, and third and fourth packets corresponding to the data to be generated from a unique destination port of the image output module, comprises:
generating a frame synchronization end data packet in response to receiving the vertical synchronization sub-signal;
generating a frame sync start packet in response to receiving the vertical sync sub-signal front shoulder;
in response to receiving the vertical resolution sub-signal, generating a third data packet of resolution corresponding to the vertical resolution sub-signal;
generating a line synchronization end data packet in response to receiving the horizontal synchronization sub-signal;
generating a line sync start packet in response to receiving the horizontal sync sub-signal front shoulder;
generating a fourth data packet of resolution corresponding to the horizontal resolution sub-signal in response to receiving the horizontal resolution sub-signal;
and outputting a frame synchronization start data packet, a frame synchronization end data packet, a line synchronization start data packet, a line synchronization end data packet, a third data packet and a fourth data packet corresponding to the data to be generated from a target port based on the time sequence control signal.
3. A data processing apparatus comprising an image output module for displaying data or transmitting image data, the apparatus further comprising:
the judging module is used for switching the application of the image output module based on the indication information stored in the register and confirming a protocol corresponding to the data to be generated based on the application of the image output module after switching;
the data to be generated comprises at least one data packet, and if the protocol is a display serial interface protocol, the output module is used for outputting a vertical synchronization start data packet, a vertical synchronization end data packet, a horizontal synchronization start data packet, a horizontal synchronization end data packet, a first data packet and a second data packet corresponding to the data to be generated from a unique target port of the image output module based on a time sequence control signal;
if the protocol is a camera serial interface protocol, the output module is configured to output, based on the timing control signal, a frame synchronization start data packet, a frame synchronization end data packet, a line synchronization start data packet, a line synchronization end data packet, and a third data packet and a fourth data packet corresponding to the data to be generated from a unique target port of the image output module;
in response to the timing control signal including a vertical synchronization sub-signal, a horizontal synchronization sub-signal, a vertical synchronization sub-signal front shoulder, a horizontal synchronization sub-signal front shoulder, a vertical resolution sub-signal, and a horizontal resolution sub-signal, the output module is specifically configured to: generating a vertical synchronization start data packet in response to receiving the vertical synchronization sub-signal; generating a vertical synchronization end packet in response to receiving the vertical synchronization sub-signal front shoulder; in response to receiving the vertical resolution sub-signal, generating a second data packet of a resolution corresponding to the vertical resolution sub-signal; generating a horizontal synchronization start data packet in response to receiving the horizontal synchronization sub-signal; generating a horizontal sync end packet in response to receiving the horizontal sync sub-signal front shoulder; in response to receiving a horizontal resolution sub-signal, generating a first data packet of a resolution corresponding to the horizontal resolution sub-signal; outputting the vertical synchronization start data packet, the vertical synchronization end data packet, the horizontal synchronization start data packet, the horizontal synchronization end data packet, and the first data packet and the second data packet corresponding to data based on a destination port.
4. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-2.
5. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-2.
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