WO2009069094A1

WO2009069094A1 - Method and device for routing data between components

Info

Publication number: WO2009069094A1
Application number: PCT/IB2008/054979
Authority: WO
Inventors: Stephen Butts
Original assignee: Nxp B.V.
Priority date: 2007-11-30
Filing date: 2008-11-27
Publication date: 2009-06-04

Abstract

A number of different devices, systems and methods are used in connection with routing of signals between components. According to one embodiment of the present invention, a device is implemented for communicating debug trace data between components that each communicates the data using an advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) interface that is consistent with the CoreSight Architecture Specification Rev 1.0. The components communicate using signals operating at different frequencies and/or voltages, respectively. The device has a buffer (212) for storing data received from the first component (102), the data received from the first component (102) being transmitted according to a first clock (112). An output circuit (213) transmits data stored in the buffer (212) using a second clock (116) having a frequency that is different from a frequency of the first clock (112).

Description

METHOD AND DEVICE FOR ROUTING DATA BETWEEN COMPONENTS

The present invention relates generally to signal routing methods and devices, and more particularly, to trace data routing between different components of a circuit.

A variety of devices and methods are used in conjunction with the use of debug trace data in a system. The trace data can be passed between several different components in the circuit. Established protocols allow the different components to communicate with each other. One example involves a microprocessor circuit system. As the demand for more powerful and/or faster systems increases, design constraints, such as power consumption and heat dissipation, can become increasingly problematic.

For instance, to increase the performance of a component, a designer might chose to increase the frequency at which the component operates. This often comes at a cost of increased power consumption and more stringent timing constraints. Power consumption can be reduced by lowering the operating voltage of the device; however, this can sometimes require more expensive designs and/or increase manufacturing costs by, for example, using restrictive manufacturing processes to meet the timing constraints of a faster design. For some systems, the components within the system do not each require the same amount of performance. Thus, it may be desirable to operate the components at different voltages or frequencies. Components with different operating voltages and frequencies present problems with communications between the components, including mismatches between signaling levels and clock domains. These and other limitations present challenges to the implementation of communication routing systems and methods. Various aspects of the present invention are directed to methods and arrangements for implementing trace data routing circuits in a manner that addresses and overcomes the above-mentioned issues.

According to one embodiment of the present invention, a device is implemented for communicating debug trace data between components that transmit or receive the debug trace data using an advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) interface that is consistent with the CoreSight Architecture Specification Rev 1.0. The components communicate using signals operating at different frequencies and/or voltages, respectively. The device has a buffer for storing data received from the first component, the data received from the first component being transmitted according to a first clock. An output circuit transmits data stored in the buffer using a second clock signal that has a frequency different from a frequency of the first clock signal.

According to another embodiment of the present invention, a bridge circuit is implemented for communicating debug trace data between components that transmit or receive the debug trace data using an advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) interface that is consistent with the CoreSight Architecture Specification Rev 1.0. The components communicate using signals operating at different frequencies and/or voltages, respectively. The bridge circuit has a synchronizer circuit for receiving data from the first component, the data being transmitted using a first clock signal and for transmitting the data using a second clock signal. A handshake circuit provides an acknowledge signal to the first component.

According to another example embodiment of the present invention, a method is implemented for manufacturing an integrated circuit for transmitting debug trace data between components of a system. The components communicate using signals operating at different frequencies and voltages, respectively. The method includes a step of creating a slave input circuit for receiving data from a slave component communication using a first clock signal. A master output circuit is created for transmitting data to a master component communicating using a second clock signal. The method includes a section between a source synchronous implementation and a handshake implementation. Based upon the selection, one of a slave buffer or a handshake circuit is implemented. The slave buffer is for storing data received from the slave component, and for providing the stored data to the master output circuit using the second clock signal. The handshake circuit is for use in receiving data from the slave component, for providing the received data to the master output circuit using the second clock signal and for providing an acknowledge signal that indicates that the master output circuit is ready to receive data.

The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. Advantages and attainments, together with a more complete understanding of the invention, will become apparent and appreciated by referring to the following detailed description and claims taken in conjunction with the accompanying drawings. The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

FIG. IA depicts a block diagram of a circuit, consistent with an embodiment of the present invention;

FIG. IB depicts a timing diagram for data and clock signals of two components, consistent with an embodiment of the present invention;

FIG. 2 depicts a bridge circuit that includes a FIFO memory buffer and level shifters that are used to interface with components having ATB interfaces, according to an example embodiment of the present invention;

FIG. 3 depicts a bridge circuit that includes double synchronizers and level shifters that are used to interface with components having ATB interfaces, according to an example embodiment of the present invention;

FIG. 4 depicts a flow diagram for manufacturing a bridge circuit, according to an example embodiment of the present invention; and

FIG. 5 depicts a two-flop synchronizer, according to an example embodiment of the present invention.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

The present invention is believed to be applicable to a variety of circuits and approaches involving trace debug data systems and methods. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.

Consistent with an example embodiment of the present invention, a device is implemented for interfacing between components operating at asynchronous clocks or different voltage signaling levels. The device receives the data consistent with the signaling parameters of the source component and provides the data to the destination component according to signaling parameters of the destination component. Consistent with one embodiment of the present invention, the data received and transmitted by the device is debug trace data. Consistent with a more specific embodiment, the debug trace data is transmitted using the AMBA 3 ATB protocol from the CoreSight Architecture Specification Rev 1.0. FIG. IA depicts a block diagram of a circuit, consistent with an embodiment of the present invention. Components 102 and 106 operate at different frequencies or voltages. Thus, bridge circuit 104 provides a communications interface between the components 102 and 106. Bridge circuit 104 can be designed to interface with a number of different components and their respective voltages or frequencies. This can be useful for allowing component 102 to be designed without specific knowledge of the other component 106 and vice versa.

The bridge circuit 104 amplifies the signal as it passes from one voltage domain to another. In some instances, this amplification results in a reduction in the voltage. For example, the first component may have a signaling voltage between OV and 5V, while the second component has a signaling voltage between OV and 3.3V. A signal S that is received from the first component is amplified to produce a signal level approximately equal to (3.3/5)S before being transmitted to the second component. Whereas a signal S that is received from the second component is amplified to produce a signal level approximately equal to (5/3.3)S before being transmitted to the second component. In this sense, the amplification can be either a reduction or increase in the voltage level.

In one embodiment of the present invention, the bridge circuit 104 includes inputs that indicate signaling parameters for components 102 and 106. For instance, the inputs could receive a signal representing the operating voltage level for each component. The received signal could be provided directly from a power supply circuit or as an output provided by the components. The bridge circuit 104 is able to determine the respective signal voltage levels for the components from their provided operating voltage level. The signal levels can include, for example, Voh, Vih, VoI and ViI. In one example, these levels are determined using a voltage drop from the supplied operating voltage. Another example is to derive the voltages as a percentage of the operating voltage using, for example, a voltage divider circuit.

In another instance, one or more of the clock signals used by the components can be provided by bridge circuit 104. Bridge circuit 104 includes interfaces that use the respective clock signals to communicate with the components. The clock signals may be provided using a dedicated clock line or they can be derived from the data lines.

In one embodiment, an input source other than the components can provide the signaling information. In one instance, the input source is provided by the circuit design, such as a non- volatile memory or one or more configuration pins that can be tied to high or low voltage values to select different voltage levels. In another instance, the input source is a third component. This third component can be, for example, a power control module that determines the respective voltage or clock frequencies for components 102 and 106. The power control module can control the level shifters and/or clock generators. This can be particularly useful for systems that have dynamically adjustable voltage or frequency components.

FIG. IB depicts a timing diagram for data and clock signals of two components, consistent with an embodiment of the present invention. The timing diagram assumes a simple protocol in which the data 114 and 118 are valid during a negative to positive edge transition of clock signals 112 and 116, respectively. This example is not intended to be limiting as various other protocols can also be used, such as using both clock edges.

The particular example provided by FIG. IB has component 102 providing data 114 at a rate consistent with clock 112. Component 106 is shown as being able receive data 118 (corresponding to data 114) at a rate consistent with clock 116. Even assuming that the clocks happen to be synchronized for the first data transfer, it is apparent from this diagram that clock of component 106 will not be synchronized for successive data transfers. Thus, the data integrity cannot be ensured without the use of bridge 104. Moreover, the component 106 is not able to receive data as fast as component 102 can provide the data. This further complicates the transfer of data between components 102 and 106.

In one embodiment of the present invention, the bridge 104 includes a memory buffer that stores received data for future transmission. Data is stored in the buffer using the clock 112, and is thus generally operated synchronously to component 102. The stored data is then accessed by the bridge 104 and transmitted to component 106 using the clock 116. This memory buffer can be particularly useful for situations in which the data is transmitted in bursts with a relatively significant amount of unused clock cycles during the non-burst transmissions periods. The memory buffer is selected to be sufficiently large so as to be able to accommodate such bursts, allowing the bridge circuit to empty the buffer during the non-burst transmission periods. In a particular embodiment of the invention, the memory buffer is operated as a first- in-first-out (FIFO) buffer.

In another embodiment of the present invention, the bridge 104 includes a handshake circuit for controlling the data transfers between components. The handshake circuit determines when the bridge 104 is ready to receive data from components 102 or 106. A handshake/acknowledge signal is then sent to the corresponding component to indicate that the bridge is ready to receive data. This can be particularly useful for implementing the bridge 104 without a large memory buffer. It can also be useful for allowing the bridge 104 (or parts thereof) to operate asynchronous Iy with the transmitting component.

In order receive the data according to a first clock signal and send it using a second clock signal that is not necessarily synchronous with the first clock signal, a synchronizer circuit can be used. Such circuits can be particularly useful for avoiding metastable conditions due to mismatches between clocks and the corresponding periods during which the data levels are valid.

FIG. 2 depicts a bridge circuit that includes a FIFO memory buffer and level shifters that are used to interface with components having ATB interfaces, according to an example embodiment of the present invention. Bridge circuit 200 includes slave interface 202 and master interface 204. Each of these interfaces can operate using their respective signal parameters, such as voltage levels or clock signals. Source synchronous clock generator 206 provides a clock to ATB data interface 208. In one instance, the clock signal generated by clock generator 206 can be a buffered version of a received clock signal. In another instance, the clock signal generated can be derived from the data lines.

Data from ATB interface 208 is level shifted using level shifters/clamp 210. Level shifters 210 modify the signaling voltages and in particular, the voltage maximums and valid data voltage levels. The resulting data is then stored in FIFO buffer 212. In one instance the data is stored in FIFO buffer 212 at a rate commensurate with ATB interface 208. This can be accomplished by using the clock signal from clock generator 206. The data is then accessed as needed and provided to the ATB data bus of the master interface 204. In a similar manner data can flow from the master interface 204 to the slave interface 202, using ATB flush interface 222, clock generator 224, level shifters 220 and FIFO buffer 218.

FIFO buffers 212 and 218 are shown as optionally having a configurable depth. The depth of the FIFO buffer can be determined as a function of the clock rates of the slave and master components. For example, if the slave component is operating at a much faster rate relative to the master component, the size of FIFO buffer 212 can be increased while the size of FIFO buffer 218 can be decrease. In a particular embodiment, bridge circuit 200 includes at least a portion of memory that can be configured as a part of either FIFO buffer. This can be useful for reducing the total amount of memory necessary while maintaining a broad range of compatible clock speeds for the various components.

Bridge circuit 200 also includes control blocks 214 and 216. These blocks operate to monitor and control the flow of data between the master and slave interfaces and between the interfaces and the external components. In a specific embodiment, control blocks 214 and 216 are implemented as finite state machines. Various other implementations are also possible including, but not limited to, logic circuits, processing circuits, programmable logic circuits and discrete logic components.

FIG. 3 depicts a bridge circuit that includes double synchronizers and level shifters that are used to interface with components having ATB interfaces, according to an example embodiment of the present invention. Bridge circuit 300 includes slave interface 302 and master interface 304. Each of these interfaces can operate using their respective signal parameters, such as voltage levels or clock signals. ATB data interface 308 receives ATB data from the slave component. Control logic (e.g., a FSM, processor, or other control logic) 324 and 334 handle the data flow to and from ATB interfaces 308 and 313. This includes a handshake protocol between the interfaces 302 and 304. When a receiving interface is ready for additional data, the receiving interface provides a ready indication to the sending interface. The receiving interface can then notify the slave component that the bridge 300 is ready to receive additional data. The AMBA ATB protocol provides for such a mechanism using, for example, the ATREADY and AFREADY signals.

Data from ATB interface 308 is level shifted using level shifters/clamp 310. Level shifters 310 modify the signaling voltages and in particular, the voltage maximums and valid data voltage levels. The resulting data is then received and transmitted using ATB data interface 313.

In a similar manner data can flow from the master interface 304 to the slave interface 302, using ATB flush interface 322, controllers 336 and 338, level shifters 320 and synchronizers 330 and 332.

In a specific implementation the correct data transfer between two different clock domains is facilitated using two-flop synchronizers and a four-phase handshake protocol. Each of the ATB interfaces, Data and Flush, can be implemented with similar, yet independent, synchronization circuits. The Finite State Machines implement the four- phase handshake to synchronize the request for data and the acknowledgement of data between the two clock domains.

An example of a two-flop synchronizer is shown in FIG 5. The data is received by flip-flop 502 and clocked synchronous with the data (and the transmitting component) using clock 1. The output of flip-flop 502 is then sent to flip-flop 504, which is clocked synchronous with the receiving component using clock 2. As clock 1 and clock 2 can be asynchronous to one another, the output of flip-flop 504 can be subject to metastable conditions. To compensate, flip-flop 506 can be used to reduce the likely -hood of the final output being unstable. Additional flip-flops could be used to further reduce likelihood of having a metastable output; however, such additions may come at a cost of increased latency.

FIG. 4 depicts a flow diagram for manufacturing a bridge circuit, according to an example embodiment of the present invention. The process includes selection step 402 where a selection is made between a source-synchronous memory buffer implementation and an asynchronous handshake implementation. Steps 406 and 412 include the creation of a slave interface. Steps 408 and 414 include the creation of a master interface. Step 410 is implemented responsive to the selection made at step 402 and represents the formation of the (FIFO) memory buffer and other relevant components, such as the controller logic (FSM). Step 416 is also implemented responsive to the selection made at step 402 and represents the formation of a handshake/synchronizer circuit and other relevant components, such as the controller logic (FSM).

The manufacturing steps mentioned above need not be performed in the order depicted. For instance, each of steps 406-416 can be interchanged and/or implemented at essentially the same time. In one instance, the slave and master interfaces generated with respect to either selection can be very similar (or even identical). This modularity can be particularly useful for reducing production costs or design costs.

The selection at step 402 can be made based upon a number of different factors. One such factor is the performance requirements of the device to be manufactured. Higher performance devices would generally be implemented using the memory buffer from step 410. Another factor may be additional features that are to be included the bridge chip. Such additional features may require significant circuit area. Thus, these devices may be better suited for use with the lower circuit area design of the handshake/synchronizer from step 416. The various embodiments described above and shown in the figures are provided by way of illustration only and should not be construed to limit the invention. Based on the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the present invention without strictly following the exemplary embodiments and applications illustrated and described herein. For instance, various implementations would likely be compatible with modifications to the AMBA ATB protocol using similar approaches. In addition, one or more of the above example embodiments and implementations may be implemented with a variety of approaches, including those used in connection with protocols other than AMBA ATB protocols and approaches. The above example embodiments and implementations may also be integrated with a variety of circuits, devices, systems and approaches, including those for use in connection with cellular phones, laptop computers, and handheld computing devices. These approaches are implemented in connection with various example embodiments of the present invention. Such modifications and changes do not depart from the true scope of the present invention that is set forth in the following claims.

Claims

What is claimed is:

1. For communicating debug trace data between components using interfaces that implement advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) protocols according to CoreSight Architecture Specification Rev 1.0, the components communicating using signals operating at different frequencies and voltages, respectively, a bridge circuit comprising: a buffer (212) for storing data received from a first component (102), the data received from the first component (102) being transmitted according to a first clock (112); and an output circuit (213) for transmitting data stored in the buffer (212) to a second component (106) according to a second clock (116) that has a frequency that is different from a frequency of the first clock (112).

2. The bridge circuit of claim 1, wherein the output circuit transmits the data stored in the buffer using an amplification of a signal used in transmitting the data received from the first component.

3. The bridge circuit of claim 1, further comprising another buffer for storing data received from the second component, the data being transmitted using the second clock; and another output circuit for transmitting data stored in the another buffer using the first clock and an amplification of a signal used in transmitting the data received from the second component.

4. The bridge circuit of claim 1, wherein the bridge circuit includes a respective input for each of the first and second clocks and wherein the bridge circuit is configured to operate according to a range of frequencies for the first and second clocks.

5. The bridge circuit of claim 4, further comprising another buffer for storing data received from the second component, the data being transmitted according to the second clock; and another output circuit for transmitting data stored in the another buffer using the first clock and a signal level that is an amplification of a signal level of the second component, wherein sizes of the buffers are dynamically adjusted as a function of current frequencies of the first and second clocks.

6. The bridge circuit of claim 1 , wherein the buffer is a first- in-first-out buffer.

7. For communicating debug trace data between components using interfaces that implement advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) protocols according to CoreSight Architecture Specification Rev 1.0, the components communicating using signals operating at different frequencies and voltages, respectively, a bridge circuit comprising: a synchronizer circuit (326, 328) for receiving data from a first component (102), the data being transmitted using a first clock (112), and for transmitting the data to a second component (106) using a second clock signal (116); and a handshake circuit (324, 334) for providing an acknowledge signal to the first component (102).

8. The bridge circuit of claim 7, wherein the acknowledge signal indicates that the bridge circuit is ready to receive data from the first component.

9. The bridge circuit of claim 7, wherein the synchronizer circuit transmits the data at a signal level that is amplified relative to a signal level of the first component.

10. The bridge circuit of claim 7, wherein the synchronizer circuit includes a series combination of two flip-flops, a first flip-flop in the series clocked by the first clock signal and the second flip-flop clocked by the second clock signal.

11. The bridge circuit of claim 7, wherein the handshake circuit includes a finite state machine that controls the acknowledge signal.

12. A method for manufacturing an integrated circuit for transmitting debug trace data between components of a system, the components communicating using signaling protocols having different frequencies and voltages from one another, the method comprising: creating a slave input circuit (208) for receiving data from a slave component (102) that transmits using a first clock signal (112); creating a master output circuit (213) for transmitting data to a master component (106) using a second clock signal (116) having a frequency different than a frequency of the first clock signal (112); selecting between a memory buffer implementation and a handshake implementation; and based upon the selection, creating one of a slave buffer (212) for storing data received from the slave component

(102), and for providing the stored data to the master output circuit (213); and a handshake circuit (326, 328) for receiving data from the slave component (102), for providing the received data to the master output circuit (213) using the second clock signal (116) and for providing an acknowledge signal to the slave component (102), the acknowledge signal indicating that master output circuit is ready to receive data.

13. The method of claim 12, wherein the handshake circuit includes a series combination of two flip-flops, a first flip-flop in the series clocked by the first clock signal and the second flip-flop clocked by the second clock signal.

14. The method of claim 12, further comprising the steps of creating a master input circuit for receiving data from the master component; creating a slave output circuit for transmitting data to the slave component; based upon the selection, implementing one of a master buffer for storing data received from the master component and for providing the stored data to the slave output circuit using the first clock signal; and another handshake circuit for receiving data from the master component, for providing the received data to the slave output circuit using the first clock signal and for providing another acknowledge signal to the second component, the another acknowledge signal indicating that the slave output circuit is ready to receive data.

15. The method of claim 12, wherein the components of a system communicate data using advanced microcontroller bus architecture (AMBA) 3 advanced-trace-bus (ATB) protocols according to CoreSight Architecture Specification Rev 1.0.

16. The method of claim 12, further including the step of creating an amplification circuit for generating signal that is amplified relative to a signal from the slave component.

17. The method of claim 12, wherein the slave buffer is a first-in-first-out buffer

18. The method of claim 12, wherein the handshake circuit is controlled by a finite state machine.