CN107562673B - Bus protocol conversion bridging device applied to embedded processor - Google Patents
Bus protocol conversion bridging device applied to embedded processor Download PDFInfo
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- CN107562673B CN107562673B CN201710747423.3A CN201710747423A CN107562673B CN 107562673 B CN107562673 B CN 107562673B CN 201710747423 A CN201710747423 A CN 201710747423A CN 107562673 B CN107562673 B CN 107562673B
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Abstract
An embedded processor bus protocol conversion bridge device for converting the access timing logic of an embedded processor to the ahb _ bus access protocol of standard AMBA; the device comprises an embedded processor, a bus bridge logic module and an AMBA module which are controlled by the same clock; in the case where the data bit width of the embedded processor bus is consistent with the data bit width of the ahb _ bus of the AMBA module, the clock delay introduced by the bus bridge logic module is zero. The invention solves the problem that a specific embedded processor uniformly accesses the interface of the external equipment, namely, the aim of universal access is realized by using smaller logic circuit resources.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a logic design belonging to chip hardware, and particularly relates to a method for realizing protocol conversion bridging applied to an embedded processor bus.
Background
Since the advent of microprocessors, embedded systems have been rapidly developed, and the embedded processor is certainly the core part of the embedded system, and the embedded processor is directly related to the performance of the whole embedded system. An embedded processor (e.g., MicroController Unit; MCU) is generally referred to as a general term for computing and controlling core devices in an embedded system, is a core of the embedded system, and is a hardware Unit for controlling and assisting the operation of the system.
The embedded processor has a plurality of design schemes, different architectures and different characteristics, but essentially works based on a certain clock synchronization, and the embedded processor sequentially initiates a series of data interaction operations such as reading, waiting and writing.
It is clear to those skilled in the art that the most fundamental role of the bus is to uniformly convert various interface protocols so that the modules can interact with each other. The bus performance is embodied as: data bit width, clock delay, operating frequency freq, latency, theoretical maximum bandwidth, average data throughput, and actually measured random read-write comprehensive efficiency.
There are four basic types of operations on a typical bus: read, Write, wait for Stall, and Done, abbreviated as R/W/S/D, respectively. Generally, the access interface of an embedded processor includes multiple stages of addressing, read/write out, wait, response, and so on. The interface protocol for embedded processors is relatively complex and may include instructions and data, typically including different directions of reading and writing.
Referring to FIG. 1, FIG. 1 is a schematic diagram illustrating a single write-out timing sequence of an embedded processor in the prior art; as shown, the embedded processor is a 32-bit machine, Read is a Read request signal, Write is a Write request signal, Addr [31:2] is an access address, BE [3:0] is a Write byte valid, WData [31:0] is Write data, Stall is a pause waiting flag, and Clk is a synchronous clock.
Referring to FIG. 2, FIG. 2 is a timing diagram illustrating a single read operation of an embedded processor according to the prior art. As shown, the embedded processor is a 32-bit machine, Read is a Read request signal, Write is a Write request signal, Addr [31:2] is an access address, BE [3:0] is a Write byte valid, WData [31:0] is Write data, Stall is a pause wait flag, RData [31:0] is Read data, RBE [3:0] is a Read byte valid, and Clk is a synchronous clock.
As can be seen from fig. 1 and 2, it is impossible for the Read request signal Read/Write request signal Write operations to be simultaneously issued, i.e., when the Read request signal Read in fig. 1 is at a low level, a single Write request signal Write operation can be performed; similarly, when the Write request signal Write in fig. 2 is operated at a low level, the single Read request signal Read operation can be performed.
Generally, in order to improve performance, the operating frequency of the embedded processor may be higher, and there are more devices connected to the bus, and the operating clock of the synchronous bus must be lower or higher.
To solve this conflict, it is also considered in the industry to implement protocol conversion by using an asymmetric asynchronous circuit, so that the embedded processor and the bus peripherals connected to the embedded processor operate at different frequencies to achieve the maximum bandwidth. However, the design method of the clock domain crossing asynchronous circuit is complicated.
Disclosure of Invention
The invention aims to provide a method for realizing bus protocol conversion bridging applied to an embedded processor, which converts access sequential logic of a specific embedded processor into ahb _ bus access protocol of mainstream standard AMBA of an embedded system so as to realize that all logic of data storage processing based on the embedded processor is completed in the same clock domain without considering an asynchronous circuit design method crossing the clock domains.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an embedded processor bus protocol translation bridge for translating access sequencing logic of the embedded processor to ahb _ bus access protocol of standard AMBA; wherein the data bit width of the embedded processor is N, and is equal to ahb _ bus bit width of the standard AMBA, and N is a power of 2; the system is characterized by comprising an embedded processor, a bus bridging logic module and an AMBA module which are controlled by the same clock;
the bus bridge logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module; the embedded processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [ N-1:2], a Write byte valid BE [3:0] and Write data WData [ N-1:0] to the first interface unit, and the first interface unit inputs a pause waiting flag Stall, Read data RData [ N-1:0] and a Read byte valid RBE [3:0] to the embedded processor; the second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [ N-1:0], write data HWRITE, and write data bus HWDATA [ N-1:0] to the AMBA module; the AMBA module inputs the bus state mark HREADY and a read data bus HRDATA [ N-1:0] into the second interface unit;
the conversion unit performs the following operations:
the access address Addr [ N-1:2] of the embedded processor is expanded to an access address bus HADDR [ N-1:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [ N-1:0] correspond to the write byte valid BE [3:0] output by the embedded processor or the two bits of the write byte valid BE [3:0] are kept to BE 0; equating a Read request signal Read/Write request signal Write output by the embedded processor as Write data HWRITE of the AMBA module; the write data WData [ N-1:0] output by the embedded processor is equivalent to the write data bus HWDATA [ N-1:0] of the AMBA module; an input pause waiting indication Stall of the embedded processor is derived from the output of the bus bridge logic module, and the logic of the pause waiting indication Stall depends on the bus state indication HREADY of the AMBA module; the embedded processor input RData [ N-1:0] is derived from the output of the bus bridge logic module and has a value equal to the value of the read data bus HRDATA [ N-1:0] of the AMBA module; an input read byte valid RBE [3:0] of the embedded processor is derived from the output of the bus bridge logic module, logically dependent on the output write byte valid BE [3:0] of the embedded processor, and valid concurrently with read data RData [ N-1:0 ]; control signal HTARNS corresponds to a case where the output Read request signal Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are simultaneously valid.
Preferably, said N is 8, 16, 32, 64 or 128.
It can be seen from the above technical solutions that the technical solution adopted by the processor-embedded bus protocol conversion bridging device of the present invention has the following beneficial effects:
①, because the AMBA bus is the mainstream standard of the embedded system, the invention converts the access time sequence logic of the specific embedded processor into the ahb _ bus access protocol of the standard AMBA, namely, the embedded processor can carry out data interaction with the bus peripheral connected with the embedded processor in real time, namely, the embedded processor can work under the high-frequency condition of the embedded processor, thereby improving the working efficiency;
②, based on the data storage processing of the embedded processor, all the logics of the invention are completed in the same clock domain, and the design method of the asynchronous circuit crossing the clock domain is not considered;
③, the interface of the external device is accessed uniformly by the special embedded processor, the purpose of general access can be realized by using smaller logic circuit resources;
④, in the case of the embedded processor bus protocol being consistent with the bit width of the ahb _ bus of the standard AMBA, the clock delay introduced by the bus bridge logic is zero, and the extra latency period is also zero, so there is no loss in the performance of the embedded processor.
Drawings
FIG. 1 is a timing diagram of a single write operation of an embedded processor according to the prior art
FIG. 2 is a timing diagram of single read in of an embedded processor in the prior art
FIG. 3 is a diagram illustrating ahb _ bus timing of a generic AMBA
FIG. 4 is a circuit block diagram of an embedded processor bus protocol conversion bridge apparatus according to the present invention
FIG. 5 is a schematic diagram of a signal combination circuit for outputting a second interface unit of a bus bridge logic module to an AMBA module according to an embodiment of the present invention
FIG. 6 is a schematic diagram of a signal combination circuit for outputting the first interface unit of the bus bridge logic module to the embedded processor according to an embodiment of the present invention
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to fig. 3 to 6.
It should be noted that, the application scenarios of the embedded processors are very different, the portability/compatibility of the access interface is of great importance, and AMBA is almost a de facto standard in the embedded chip system.
Referring to fig. 3, fig. 3 is a timing diagram of ahb _ bus of the generic AMBA; as shown, unlike the single read/write time domain usage of the embedded processor, the Address phase and data phase are performed in different time domains. HCLK is the bus clock signal of ahb _ bus of AMBA, HARRD [31:0] is the access address bus, Control is the bus Control signal, which includes HTRANS and the write request signal HWRITE. HWDATA [31:0] is the write data bus, HREADY is the bus status indicator, and HRDATA [31:0] is the read data bus.
In the embodiment of the invention, when the data bit width of the embedded processor is the same as the ahb _ bus bit width of the standard AMBA, the access timing logic of the embedded processor is converted into the ahb _ bus access protocol of the standard AMBA, and the memory interface of the embedded processor is converted into the ahb _ bus access protocol of the AMBA through a bus bridge logic module (bridge).
In embodiments of the present invention, the data bit width of the embedded processor may be selected to be a power of 2, typically, 8, 16, 32, 64, or 128, for example. For convenience of description, the following embodiments take the data bit width of the embedded processor and the ahb _ bus bit width of the standard AMBA as 32 as an example, and the descriptions of other bit widths are omitted.
Referring to fig. 4, fig. 4 is a circuit diagram of an embedded processor bus protocol conversion bridge device according to the present invention. As shown in the figure, the bus protocol conversion bridging device of the embedded processor comprises the embedded processor, a bus bridging logic module and an AMBA module which are controlled by the same clock; the clock signal CLK is coupled to the clock input of the embedded processor, the clock input of the bus bridge logic module, and the clock input HCLK of the AMBA module, respectively.
The embedded processor includes output terminals of the embedded processor outputting a Read request signal Read, a Write request signal Write, an access address Addr [31:2], a Write byte valid BE [3:0], and Write data WData [31:0], and input terminals of a pause wait flag Stall, Read data RData [31:0], and a Read byte valid RBE [3:0 ].
The AMBA module includes inputs for control signals HTRANS [1:0], access address bus HADDR [ N-1:0], write data HWRITE, and write data bus HWDATA [31:0], and outputs for bus status flags HREADY and read data bus HRDATA [31:0 ].
The bus bridge logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module.
The embedding processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [31:2], a Write byte valid BE [3:0] and Write data WData [31:0] to the first interface unit, which inputs a pause waiting flag Stall, Read data RData [31:0] and a Read byte valid RBE [3:0] to the embedding processor.
The second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [ N-1:0], write data HWRITE, and write data bus HWDATA [31:0] to the AMBA module; the AMBA module inputs the bus state indication HREADY and the read data bus HRDATA [31:0] to the second interface unit.
The above-mentioned technical solution of hardware connection works in a clock domain, that is, all circuits are synchronous circuits, and the clock signal CLK may be from an external clock signal or an internal clock signal. For example, the sequential circuit seq may be implemented using a flip-flop.
In an embodiment of the present invention, the outputs of the first interface unit and the second interface unit of the bus bridge logic module are both dependent on the inputs of the first interface unit and the second interface unit of the bus bridge logic module. Specifically, the conversion unit of the bus bridge logic module performs the following operations:
the output address bus Addr [31:2] of the embedded processor is extended to the access address bus HADDR [31:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [31:0] can correspond to the write byte valid BE [3:0] output by the embedded processor, or the two bits of the write byte valid BE [3:0] can BE kept to BE 0.
The Read request signal Read/Write request signal Write output by the embedded processor may be equivalent to Write data HWRITE of the AMBA module; this is based on the fact that it is not possible for the embedded processor to issue Read/Write request signals Write simultaneously, so that the HWRITE equivalent Write request signal Write of AMBA can be used and vice versa～HWRITE operates in response to the Read request signal Read.
The write-out data WData [31:0] output by the embedded processor may be equivalent to the write data bus HWDATA [31:0] of the AMBA module.
The input Stall waiting indication Stall of the embedded processor is derived from the output of the bus bridge logic module, and the logic of the Stall waiting indication Stall depends on the bus state indication HREADY of the AMBA module.
The embedded processor inputs RData [31:0] are derived from the outputs of the bus bridge logic module and have a value equal to the value of the access address bus HRDATA [31:0] of the AMBA module.
The input read byte valid RBE [3:0] of the embedded processor is derived from the output of a bus bridge logic block whose logic depends on the output write byte valid BE [3:0] of the embedded processor and is valid concurrently with the read data RData [31:0 ].
The remainder of the signals between the bus bridge logic and the ahb _ bus of the AMBA module are relatively simple, and control signal HTARNS corresponds to the case where the output Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are both valid.
The logic of the combinational circuit of the output signal of the first interface unit and the output signal of the second interface unit of the bus bridge logic module is described below.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a signal combination circuit for outputting the second interface unit of the bus bridge logic module to the AMBA module according to the embodiment of the present invention. As shown, fig. 5 includes four combinational circuits (the combinational circuit is referred to as comb), an HTRANS combinational circuit, an HADDR combinational circuit, an HWRITE combinational circuit, and an HWDATA combinational circuit.
Suppose that: the internal variables of the bus bridge logic are:
valid＝(|BE[3:0])&(Read|Write)
the signals output to the AMBA module ahb _ bus are:
HTRANS＝{valid,1’b0}
HADDR＝Addr
HWRITE＝valid&Write&～Read
HWDATA＝WData
referring to fig. 6, fig. 6 is a schematic diagram of a signal combination circuit outputted from the first interface unit of the bus bridge logic module to the embedded processor according to an embodiment of the present invention. As shown, fig. 6 includes three combinational circuits (combinational circuit denoted comb), RData combinational circuit, Stall combinational circuit, and RBE combinational circuit.
Suppose that: the internal variables of the bus bridge logic are:
valid＝(|BE[3:0])&(Read|Write)
the signals output to the AMBA module ahb _ bus are:
RData＝HREADY？HRDATA:0
Stall＝HREADY
RBE＝HREADY？BE:0
in summary, the access timing logic of the specific embedded processor of the embedded processor bus protocol conversion bridge device of the present invention is converted into ahb _ bus access protocol of standard AMBA; i.e., where the data bit width of the embedded processor bus is consistent with the data bit width of the ahb _ bus of the AMBA module, the clock delay introduced by the bus bridge logic module is zero. That is to say, the data interaction can be carried out between the embedded processor and the bus peripheral connected with the embedded processor in real time, namely, the embedded processor can work under the high-frequency condition of the embedded processor, and the working efficiency is improved.
In addition, it should be emphasized that the bus protocol conversion bridging device of the embedded processor of the present invention solves the problem of uniformly accessing the interface of the external device by a specific embedded processor, and can realize the purpose of universal access with smaller logic circuit resources.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (2)
1. An embedded processor bus protocol translation bridge for translating access sequencing logic of the embedded processor to ahb _ bus access protocol of standard AMBA; wherein the data bit width of the embedded processor is N, and is equal to ahb _ bus bit width of the standard AMBA, and N is a power of 2; the system is characterized by comprising an embedded processor, a bus bridging logic module and an AMBA module which are controlled by the same clock;
the bus bridge logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module; the embedded processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [ N-1:2], a Write byte valid BE [3:0] and Write data WData [ N-1:0] to the first interface unit, and the first interface unit inputs a pause waiting flag Stall, Read data RData [ N-1:0] and a Read byte valid RBE [3:0] to the embedded processor; the second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [ N-1:0], write data HWRITE, and write data bus HWDATA [ N-1:0] to the AMBA module; the AMBA module inputs the bus state mark HREADY and a read data bus HRDATA [ N-1:0] into the second interface unit;
the conversion unit performs the following operations:
the access address Addr [ N-1:2] of the embedded processor is expanded to an access address bus HADDR [ N-1:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [ N-1:0] correspond to the write byte valid BE [3:0] output by the embedded processor or the two bits of the write byte valid BE [3:0] are kept to BE 0;
the Read request signal Read/Write request signal Write output by the embedded processor is equivalent to Write data HWRITE of the AMBA module;
the write data WData [ N-1:0] output by the embedded processor is equivalent to the write data bus HWDATA [ N-1:0] of the AMBA module;
an input pause waiting indication Stall of the embedded processor is derived from the output of the bus bridge logic module, and the logic of the pause waiting indication Stall depends on the bus state indication HREADY of the AMBA module;
the embedded processor input RData [ N-1:0] is derived from the output of the bus bridge logic module and has a value equal to the value of the read data bus HRDATA [ N-1:0] of the AMBA module; an input read byte valid RBE [3:0] of the embedded processor is derived from the output of the bus bridge logic module, logically dependent on the output write byte valid BE [3:0] of the embedded processor, and valid concurrently with read data RData [ N-1:0 ];
control signal HTARNS corresponds to a case where the output Read request signal Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are simultaneously valid.
2. The apparatus of claim 1, said N being 8, 16, 32, 64, or 128.
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| WO2009069094A1 (en) * | 2007-11-30 | 2009-06-04 | Nxp B.V. | Method and device for routing data between components |
| CN104714907A (en) * | 2013-12-11 | 2015-06-17 | 中国航空工业第六一八研究所 | Design method for converting PCI bus into ISA bus or APB bus |
| CN105512072A (en) * | 2015-12-09 | 2016-04-20 | 天津国芯科技有限公司 | Conversion device based on APB (advanced peripheral bus) and OPB (on-chip peripheral bus) |
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| US20050262376A1 (en) * | 2004-05-21 | 2005-11-24 | Mcbain Richard A | Method and apparatus for bussed communications |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2009069094A1 (en) * | 2007-11-30 | 2009-06-04 | Nxp B.V. | Method and device for routing data between components |
| CN104714907A (en) * | 2013-12-11 | 2015-06-17 | 中国航空工业第六一八研究所 | Design method for converting PCI bus into ISA bus or APB bus |
| CN105512072A (en) * | 2015-12-09 | 2016-04-20 | 天津国芯科技有限公司 | Conversion device based on APB (advanced peripheral bus) and OPB (on-chip peripheral bus) |
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