CN115168264A

CN115168264A - Clock domain-crossing APB bus bridge and method thereof

Info

Publication number: CN115168264A
Application number: CN202210901463.XA
Authority: CN
Inventors: 赵昌兵
Original assignee: Espressif Systems Shanghai Co Ltd
Current assignee: Espressif Systems Shanghai Co Ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2022-10-11

Abstract

There is provided an APB bus bridge across clock domains, the APB bus bridge comprising: the device comprises a source clock domain port, a destination clock domain port, an FIFO, an APB bus protocol generating circuit and a source clock domain handshake signal generating circuit. According to the application, the FIFO is used for caching write data, whether the source clock domain handshaking signal is pulled up or not is determined according to whether current transmission is write transmission enabled by the write cache and the cache state of the FIFO, namely whether the source clock domain handshaking signal is returned in advance or not is determined, so that the APB host is indicated that the current write transmission is completed, and therefore the write transmission is accelerated when the write cache is enabled. In addition, the application also provides a method for cross-clock domain access executed by the APB bus bridge.

Description

Clock domain-crossing APB bus bridge and method thereof

Technical Field

Embodiments of the present disclosure relate generally to the field of chip design, and more particularly, to an APB bus bridge across clock domains and a method thereof.

Background

This section introduces aspects that may facilitate a better understanding of the disclosure. Accordingly, the statements of this section should be read in this light, and not to be construed as an admission as to which content is prior art or which content is not prior art.

With the change of the demand and the development of the process size, a system on chip (SoC) has advantages of small area, low power consumption, and powerful function, and is more and more widely applied to the field of integrated circuits. The IP core multiplexing technology can greatly accelerate the design process of the SoC and improve the reliability, and is one of key technologies for SoC development. The IP core multiplexing needs to have a uniform bus interface, different design units in the system and other module interfaces follow a uniform bus protocol, communication can be carried out only by connecting, and the responsible interface conversion is not needed.

At present, an Advanced Microcontroller Bus Architecture (AMBA) protocol is a set of Bus protocols widely applied to SoC design, wherein an Advanced Peripheral Bus (APB) protocol is an interface protocol widely applied to register access, and the method has the advantages of low overhead, simplicity in implementation and the like. However, different functional modules in the system often work at different clock frequencies, and when a Central Processing Unit (CPU) wants to access registers in different clock domains through a bus, cross-clock domain processing is required, and cross-clock domain processing at an APB bus interface has the advantages of simple design, clear interface and the like, and can greatly accelerate subsequent clock domain cross checking (cdc).

At present, the existing APB clock domain crossing processing scheme mainly adopts handshake, FIFO or clock domain crossing processing using clock enable signals to perform edge alignment, and these schemes can be used for clock domain crossing processing of an APB bus, but no matter read operation or write operation, the processing can be executed after a handshake signal (ready) of a destination end is synchronized, so the speed is relatively slow.

In the prior art, chinese patent CN101377691A discloses a method for performing clock domain crossing processing by using a handshake manner of control signals. The clock synchronization circuit synchronizes a chip selection signal (psel) and an enable signal (enable) of the APB clock domain to the clock domain of the accessed terminal, outputs the chip selection signal (psel) and the enable signal (enable) to the control register as a control signal (msel), synchronizes the control signal (msel) back to the APB clock domain, and sends the control signal (msel) back to the APB bridge as a handshake signal (ready). However, this scheme has a problem, especially for a write transfer, it needs to wait until the handshake signal of the destination end is synchronized back to complete, so the write transfer speed is slow.

In another PCT international application WO2016192217A1, an APB bus bridge is disclosed. The technical scheme of the patent only deals with clock edge alignment, and a clock crossing domain of a synchronous clock with a frequency ratio of a positive integer N needs an additional clock enable signal. Similarly, the scheme has similar problems that writing cannot be accelerated, and the transmission of one writing can be completed only by waiting for the handshake signals to the destination end to be synchronized back.

Therefore, the prior art cannot dynamically accelerate the APB write transfer when realizing the APB bus crossing clock domains.

Disclosure of Invention

It is desirable to implement an APB bus bridge across clock domains that can dynamically speed up write transfers. To address at least some of the problems in the prior art described above, circuits, methods, and devices of an APB bus bridge are provided in the present disclosure. It will be appreciated that embodiments of the present disclosure are not limited to being on a system-on-a-chip SoC, but may be more broadly applied to any application scenario where similar issues exist.

The present invention buffers write data by using a FIFO (first in first out buffer), and once the write data is received into the FIFO, it can be selected whether to advance back to ready or not according to a control signal of a write buffer switch. When the write cache operation is enabled, the write transmission can be completed quickly, so that a CPU (central processing unit) and a bus can be released to process other tasks, and the system efficiency is increased;

various embodiments of the present disclosure are generally directed to circuits, methods, and apparatuses for implementing an APB bus bridge across clock domains. Other features and advantages of embodiments of the present disclosure will also be appreciated when reading the following description of specific embodiments in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of embodiments of the disclosure.

In general, embodiments of the present disclosure provide a solution for a clock domain crossing APB bus bridge for dynamically performing accelerated write input operations. The method uses the FIFO to buffer and write data, and determines whether to pull up the source clock domain handshaking signal or not according to whether the current transmission is write transmission enabled by the write buffer and the buffer state of the FIFO, namely, determines whether to return the source clock domain handshaking signal in advance so as to indicate to the APB host that the current write transmission is completed, thereby realizing the acceleration of the write transmission enabled by the write buffer. In a first aspect, there is provided an APB bus bridge across clock domains, the APB bus bridge comprising: the device comprises a source clock domain port, a destination clock domain port, an FIFO, an APB bus protocol generating circuit and a source clock domain handshake signal generating circuit. Wherein the source clock domain port is configured for connecting a master device operating in the source clock domain; the destination clock domain port is configured for connecting one or more APB slave devices operating in the destination clock domain; the transmission start detection circuit is configured to generate a transmission start flag (trans _ start) when a transmission request occurs; the FIFO is configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; the APB bus protocol generation circuit is configured to read and analyze information buffered in the FIFO from the FIFO and generate a destination clock domain write data signal in a destination clock domain, and is further configured to acquire a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain; the source clock domain handshake signal generation circuit is configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write buffer enabled write transmission and a buffer state of the FIFO; if the current transmission is write buffer enabled write transmission, the source clock domain handshake signal is pulled up after the buffer information required by the current transmission is written into the FIFO; when the transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, an FIFO write-in signal is generated and triggers to write the buffer information required by the current transmission into the FIFO; and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshaking signal after waiting for the generation of the target clock domain handshaking signal.

Further preferably, the buffer information includes write data including a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of the source clock domain APB port; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

Further preferably, the APB bus bridge includes a write cache enable synchronization circuit configured to trigger synchronization of the write cache enable signal (wbuf _ en) by the transfer start flag to obtain the write cache enable synchronization signal (wbuf _ en _ sync), wherein the synchronization is such that the write cache enable synchronization signal remains unchanged during a current transfer.

Still further preferably, the write cache enable synchronizing circuit performs synchronization of the write cache enable signal (wbuf _ en) including: when the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned as a write cache enable signal, and the write cache enable signal (wbuf _ en _ reg) is registered and updated as the write cache enable signal; when the value of the transfer start flag is 0, the write cache enable synchronization signal is asserted to register the write cache enable signal (wbuf _ en _ reg).

In one embodiment, if the clocks of the source and destination clock domains are synchronous clocks, the FIFO uses a synchronous FIFO with two clock ports; the FIFO uses an asynchronous FIFO if the clocks of the source and destination clock domains are asynchronous clocks.

In one embodiment, the APB bus bridge is applied to an SoC platform based on the AMBA protocol.

In one embodiment, the APB bus bridge is directly connected to the APB host. Wherein, the APB host is a host of APB protocol.

In one embodiment, the APB bus bridge is connected to the AXI protocol bus or the AHB protocol bus through a protocol translation bus bridge.

In a second aspect, there is provided a method of cross-clock domain access performed by an APB bus bridge, the APB bus bridge comprising: a source clock domain port for connecting a master device operating in a source clock domain; a destination clock domain port for connecting one or more APB slave devices operating in a destination clock domain; a transmission start detection circuit; a write cache enable synchronization circuit; a FIFO for buffering write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; APB bus protocol generating circuit; and a source clock domain handshake signal generation circuit configured to select a source that generates a source clock domain handshake signal according to whether a current transmission is a write transmission enabled by a write buffer and a buffer state of the FIFO; the method comprises, when a transmission request occurs, executing the following steps:

s1: a transmission start detection circuit generates a transmission start flag;

s2: triggering a write cache enabling synchronization circuit to execute synchronization of a write cache enabling signal by a transmission starting mark so as to obtain the write cache enabling synchronization signal, wherein the synchronization keeps the write cache enabling synchronization signal unchanged in the current transmission process;

s3: selecting a source for generating a source clock domain handshake signal (ready _ s) by a source clock domain handshake signal generating circuit according to whether current transmission is write transmission enabled by write cache and the cache state of FIFO; if the current transmission is write buffer enabled write transmission, after waiting for the buffer information required by the current transmission to be written into the FIFO, pulling up the source clock domain handshake signal, wherein when the transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, a FIFO write signal is generated and triggered to write the buffer information required by the current transmission into the FIFO; and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshaking signal after waiting for the generation of the target clock domain handshaking signal.

In one embodiment, the method further comprises performing the steps of: the APB bus protocol generation circuit reads and analyzes information buffered in the FIFO from the FIFO and generates a destination clock domain write data signal in a destination clock domain, and the APB bus protocol generation circuit also acquires a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain.

In one embodiment, the method further comprises performing the steps of: when the source clock domain handshake signal is generated and the transmission start detection circuit generates a FIFO write signal and the FIFO non-full signal of the FIFO is 1, the buffer information required by the current transmission is triggered to be written into the FIFO.

In one embodiment, the buffer information includes write data including a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of the source clock domain APB port; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

In one embodiment, the write cache enable synchronization circuit performs synchronization of the write cache enable signal including: when the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned as a write cache enable signal, and the write cache enable signal (wbuf _ en _ reg) is registered and updated as the write cache enable signal; when the value of the transfer start flag is 0, the write cache enable synchronization signal is asserted to register the write cache enable signal (wbuf _ en _ reg).

In a third aspect, there is provided an APB bus bridge across clock domains, the APB bus bridge comprising: a source clock domain port, a destination clock domain port, a transmission start detection module, an FIFO, an APB bus protocol generation module and a source clock domain handshake signal (ready _ s) generation module; a transmission start detection module configured to generate a transmission start flag (trans _ start) when a transmission request occurs; a FIFO configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; an APB bus protocol generation module configured to read and parse information buffered in the FIFO from the FIFO and generate a destination clock domain control signal and a destination clock domain write data signal in a destination clock domain, wherein the destination clock domain control signal includes a destination clock domain handshake signal (ready _ d); a source clock domain handshake signal generation module configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write transmission enabled by write buffer and a buffer status of the FIFO; if the current transmission is write transmission enabled by write cache, pulling up a source clock domain handshake signal after cache information required by the current transmission is written into the FIFO; when the transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, an FIFO write-in signal is generated and triggers to write the buffer information required by the current transmission into the FIFO; and if the current transmission is read transmission or write transmission which is not enabled by a write cache, pulling up the source clock domain handshake signal after waiting for the generation of the destination clock domain handshake signal.

In one embodiment, the APB bus bridge includes a write cache enable synchronization module configured to trigger synchronization of a write cache enable signal (wbuf en) by a transfer start flag to obtain a write cache enable synchronization signal (wbuf en sync), wherein the synchronization causes the write cache enable synchronization signal to remain unchanged during a current transfer.

According to various embodiments of the present disclosure, by buffering write data using a first-in-first-out buffer (FIFO), once the write data is written into the FIFO, it may be determined whether to return a source clock domain handshake signal (ready _ s) in advance. Therefore, when the write cache operation is in an enabling state, the write transmission can be completed quickly, so that a Central Processing Unit (CPU) and a protocol bus are released to process other tasks, and the system efficiency is increased. Therefore, a dynamic write-accelerated clock domain crossing APB bus bridge can be realized.

Drawings

The foregoing and other aspects, features and advantages of various embodiments of the present disclosure will become more fully apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals or letters are used to designate like or equivalent elements. The accompanying drawings, which are included to provide a further understanding of embodiments of the disclosure and are not necessarily drawn to scale, wherein:

FIG. 1 is a block diagram showing an SoC bus interconnect architecture based on the AMBA protocol;

FIG. 2 is a block diagram illustrating an architecture of an APB bus bridge across clock domains according to an embodiment of the present disclosure;

FIG. 3 is a block diagram illustrating an architecture of an APB bus bridge across clock domains according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating an example write cache enable synchronization circuit according to the present disclosure;

FIG. 5 is a waveform diagram illustrating the generation of source clock domain handshake signals (ready _ s) according to an embodiment of the present disclosure;

FIG. 6 is a waveform diagram illustrating two consecutive write buffer write operations (assuming the buffer status of the FIFO is not full) according to an example of the present disclosure;

FIG. 7 is a waveform diagram illustrating a one-write buffer enabled write input followed by a one-non-write buffer enabled write input according to an example of the present disclosure (assuming the buffer status of the FIFO is not full);

FIG. 8 is a waveform diagram illustrating a two-stroke non-write buffer enabled write input according to an example of the present disclosure (assuming that the buffer status of the FIFO is not full);

FIG. 9 is a waveform diagram illustrating a write input operation followed by a read operation with a write buffer enabled according to an example of the present disclosure (assuming that the buffer status of the FIFO is not full);

FIG. 10 is a block diagram illustrating a specific example of an APB bus bridge across clock domains in accordance with an embodiment of the present disclosure;

FIG. 11 is a flow diagram illustrating a method of cross-clock domain access performed by an APB bus bridge according to an embodiment of the present disclosure;

fig. 12 is a schematic block diagram illustrating an APB bus bridge across clock domains, according to a specific example of the present disclosure.

Detailed Description

The present disclosure will now be discussed with reference to several exemplary embodiments. It should be understood that these examples are discussed only for the purpose of enabling those skilled in the art to better understand the present disclosure and to thereby carry out the present disclosure, and do not imply any limitation on the scope of the present disclosure.

References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "has," "with," "contains," "containing," and/or "incorporates" when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Some exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a typical SoC bus interconnect architecture 100 based on an AMBA bus, specifically including: a Central Processing Unit (CPU) 102, a direct memory access unit (DMA) 104, and some other bus master 106; a bus interconnect module 108; memory 110 and other bus slaves 112; protocol conversion 114 and implementing a clock domain crossing bus bridge 116 from APB to APB. It should be understood that the following description of FIG. 1 is intended for purposes of illustration only and is not intended to imply any limitation as to the scope of the disclosure.

In the AMBA bus SoC system as shown in fig. 1, when performing high-speed data exchange, the bus interconnection based on AXI or AHB protocol is mainly used, and when performing low-speed operation such as configuring registers, the APB protocol is usually used, because such low-speed operation has low requirement on speed, and the APB protocol is relatively simple, so it is easy to implement and relatively low in overhead.

The configuration of the register is mainly processed by the CPU, and the protocol and clock domain crossing conversion from the bus interface of the CPU to the APB interface of the register needs to be performed through a bus bridge. Usually, registers of various peripheral devices have different frequencies, so that a protocol conversion before and a frequency conversion after can be adopted to reduce the overhead, and at this time, an APB-to-APB clock domain crossing bus bridge is needed. The benefit of this approach is: on one hand, the cost for realizing clock domain crossing at the APB protocol port is smaller than that for realizing clock domain crossing at AXI or AHB; on the other hand, one way of demultiplexing of the APB protocol is simpler than the AXI protocol or the AHB protocol. Therefore, this approach does not require the use of multiple AXIs or AHBs to APB protocol conversion bus bridges.

Example one

In one embodiment, an APB bus bridge across clock domains is provided.

Fig. 2 is a block diagram illustrating an architecture of an APB bus bridge 200 across clock domains according to an embodiment of the present disclosure. The APB bus bridge 200 according to the present embodiment includes the following parts: the device comprises a source clock domain port, a destination clock domain port, a transmission start detection circuit, a FIFO, an APB bus protocol generation circuit and a source clock domain handshake signal generation circuit. Wherein:

the source clock domain port is configured for connecting a master device operating in a source clock domain;

the destination clock domain port is configured for connecting one or more APB slave devices operating in the destination clock domain; by way of example and not limitation, an APB slave may be a peripheral register. By way of example and not limitation, the APB bus bridge performs address decoding by an address decoder to determine which APB slave device communicates with the master device based on the address and control signals.

The transmission start detection circuit is configured to generate a transmission start flag (trans _ start) when a transmission request occurs;

the FIFO is configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full;

the APB bus protocol generation circuit is configured to read and analyze information buffered in the FIFO from the FIFO and generate a destination clock domain write data signal in a destination clock domain, and is further configured to acquire a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain;

the source clock domain handshake signal generation circuit is configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write transmission enabled by write buffering and a buffering state of the FIFO; wherein the content of the first and second substances,

if the current transmission is write transmission of write cache enabling, pulling up a source clock domain handshake signal after cache information required by the current transmission is written into the FIFO; when the transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, an FIFO write-in signal is generated and triggers to write the buffer information required by the current transmission into the FIFO;

and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshaking signal after waiting for the generation of the target clock domain handshaking signal.

More specifically, the write-in buffer information includes write data including a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of the source clock field APB port; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

The APB bus bridge 200 shown in fig. 2 further includes input and output interface signals: a source clock domain clock clk _ s, a source clock domain reset signal rstn _ s, a destination clock domain clock clk _ d, a destination clock domain reset signal rstn _ d, other source clock domain end APB bus interface signals (the suffix of the signal name is marked as _ s), and other destination clock domain end APB bus interface signals (the suffix of the signal name is marked as _ d).

More specifically, the input signals of the transmission start detection circuit include a source clock domain selection signal (psel _ s) and a source clock domain enable signal (enable _ s), and status information of the FIFO. The transfer start detection circuit generates a transfer start flag, which is valid only for the first clock cycle at the start of transfer, in response to the transfer request, the signal being used for synchronization of the write cache enable register. The transmission start detection circuit may generate a FIFO write signal (push) according to the determination logic, and specifically, when the transmission start flag is 1 and the buffer status of the FIFO is not full, the FIFO write signal is generated, and the FIFO write signal triggers writing of the buffer information required for the current transmission into the FIFO. The FIFO write signal is required to ensure that each transmission has a corresponding correct valid message written into the FIFO.

Example two

In a second embodiment, an APB bus bridge across clock domains is provided.

Fig. 3 is a block diagram illustrating an architecture of an APB bus bridge 300 across clock domains according to an embodiment of the present disclosure. The APB bus bridge 300 according to the present embodiment includes the following parts: the device comprises a source clock domain port, a destination clock domain port, a transmission start detection circuit, a write cache enable synchronization circuit, a FIFO (first in first out), an APB (advanced peripheral bus) bus protocol generation circuit and a source clock domain handshake signal generation circuit. Wherein:

the destination clock domain port is configured for connecting one or more APB slave devices operating in the destination clock domain; by way of example and not limitation, an APB slave may be a peripheral register; by way of example and not limitation, the APB bus bridge performs address decoding by an address decoder to determine which APB slave device communicates with the master device based on the address and control signals.

the write cache enabling synchronization circuit is configured to trigger synchronization of a write cache enabling signal (wbuf _ en) by the transmission start flag to obtain a write cache enabling synchronization signal (wbuf _ en _ sync), wherein the synchronization keeps the write cache enabling synchronization signal unchanged in the process of current transmission;

the source clock domain handshake signal generation circuit is configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write transmission enabled by write buffering and a buffering state of the FIFO; wherein, the first and the second end of the pipe are connected with each other,

if the current transmission is write buffer enabled write transmission, after the buffer information required by the current transmission is written into the FIFO, pulling up the source clock domain handshake signal; when the transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, an FIFO write-in signal is generated and triggers to write the buffer information required by the current transmission into the FIFO;

and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshake signal after the generation of the destination clock domain handshake signal.

More specifically, in the source clock domain handshake signal generation circuit, the default state of the source clock domain handshake signal (ready _ s) is set to 0, and the source clock domain handshake signal becomes 1 when pulled high.

And if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshake signal after the generation of the destination clock domain handshake signal. As an example, if the current transfer is a read transfer or a write cache not enabled write transfer, a pulse signal is generated based on a destination clock domain handshake signal (ready _ d), a destination clock domain enable signal (enable _ d), and a destination clock domain select signal (psel _ d) of the destination clock domain and synchronized back to the source clock domain to generate a source clock domain handshake signal as an output of the source clock domain handshake signal generation circuit. Wherein the destination clock domain handshake signal is generated after waiting for all write buffer enabled write transfers in the destination clock domain to complete.

More specifically, a write cache enable signal (wbuf _ en _ d) synchronized to the destination clock domain is used to mask the handshake signal of the write cache enable transmission of the destination clock domain. When the transmission is write buffer enabling transmission, the handshake signals of the source clock domain are generated through the source clock domain handshake signal generation circuit and do not need to be generated again, so that useless handshake signals of the destination clock domain are shielded by using the signals, and transmission errors caused by mistaken transmission to the source clock domain are prevented.

More specifically, the FIFO write timing is set to: if the buffer state of the FIFO is not full, generating a FIFO write-in signal by a transmission start detection circuit in the first clock period of each transmission; if the buffer status of the FIFO is full, the write timing is the first clock cycle in which the FIFO becomes non-full and has a transfer request. The readout timing of the FIFO is set to: the buffer status of the FIFO is not empty and read.

More specifically, the write-in buffer information includes write data, which includes a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of the APB port of the source clock field; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

More specifically, the synchronization of the write cache enable signal (wbuf _ en) performed by the write cache enable synchronization circuit includes:

when the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned as a write cache enable signal, and the write cache enable signal (wbuf _ en _ reg) is registered and updated as the write cache enable signal;

when the value of the transfer start flag is 0, the write cache enable synchronization signal is asserted as the registered write cache enable signal (wbuf _ en _ reg).

Since the input write buffer enable signal (wbuf _ en) may change at any time, the write buffer enable synchronization circuit may synchronize the value of the write buffer enable signal in the first clock cycle from the beginning of a transfer to obtain the write buffer enable synchronization signal, which is used as a flag indicating whether the transfer enables the write buffer.

FIG. 4 shows a schematic diagram of a write cache enable synchronization circuit as an example. Wherein, the input of the write cache enable synchronization circuit comprises a transmission start flag (trans _ start) and a write cache enable signal (wbuf _ en). As an example, the write buffer enable synchronization circuit uses a D flip-flop and a selector, and synchronizes the write buffer enable signal with a transmission start flag, thereby outputting a write buffer enable synchronization signal (wbuf _ en _ sync) that can remain unchanged during transmission of the source clock domain port. It is to be noted that the circuit configuration of the write cache enable synchronizing circuit described above is merely an example of the present disclosure, but the present disclosure is not limited thereto. For example, other circuit configurations may be employed depending on the actual situation.

Specifically, according to the write cache enable circuit shown in fig. 4, the specific operation principle is as follows: when the transmission start flag (trans _ start) is 1, the write cache enable synchronization signal (wbuf _ en _ sync) is asserted as the write cache enable signal (wbuf _ en), and the registered write cache enable signal (wbuf _ en _ reg) is updated as the write cache enable signal (wbuf _ en), and the registered write cache enable signal (wbuf _ en _ reg) is kept unchanged at the rest of the time; when the transmission start flag (trans _ start) is 0, the write buffer enable synchronization signal (wbuf _ en _ sync) is asserted to register the write buffer enable signal (wbuf _ en _ reg).

By way of example and not limitation, if the clocks of the source and destination clock domains are synchronous clocks, the FIFO uses a synchronous FIFO with two clock ports; the FIFO uses an asynchronous FIFO if the clocks of the source clock domain and said destination clock domain are asynchronous clocks.

By way of example and not limitation, the APB bus bridge is applied to an SoC platform based on the AMBA protocol.

By way of example and not limitation, the APB bus bridge is directly connected to the APB host. Wherein, the APB host is a host of APB protocol.

By way of example and not limitation, the APB bus bridge is connected to an AXI protocol bus or an AHB protocol bus through a protocol translation bus bridge. .

More specifically, the APB bus protocol generation circuit is further configured to generate the control signal and the data signal according to the APB bus protocol according to a destination clock domain handshake signal (ready _ d) input by the APB bus of the destination clock domain.

Example one: two successive writes buffer enabled write transfer (assuming FIFO buffer status is not full and full, respectively)

The overall working flow of the parts of the APB bus bridge combined to generate the source clock domain handshake signals is shown in fig. 5, which is described in detail as follows:

when a transmission request starts, firstly, the write buffer enable signal (wbuf _ en) is synchronized through the write buffer enable synchronizing circuit to obtain the write buffer enable synchronizing signal (wbuf _ en _ sync), which is kept unchanged during the transmission process of the source clock domain port.

As shown in fig. 5, the source clock domain select signal (psel _ s) is 1 and the source clock domain enable signal (enable _ s) is 0, indicating that a write transfer request enabled by the first write cache is generated, and thus the transfer start flag (trans _ start) becomes 1 (as indicated by the first dotted circle from left to right in fig. 5). At this time, the corresponding FIFO non-full signal (FIFO _ full) is 0, which indicates that the buffer status of the FIFO is not full, so that the transfer start detection circuit generates a FIFO write signal corresponding to the first transfer request at the end of the current cycle of the transfer start flag (trans _ start) (as indicated by the first arrow from left to right in fig. 5). And storing the information which is required to be buffered by the current write transmission request into the FIFO according to the generated FIFO write signal. And, the source clock domain handshake signal generating circuit pulls up the source clock domain handshake signal (ready _ s) (as shown by the first solid line circle from left to right in fig. 5), i.e., returns the source clock domain handshake signal to indicate to the APB host that the write transfer is currently completed. Wherein, the APB host is a host of APB protocol.

When the source clock domain select signal (psel _ s) is 1 and the source clock domain enable signal (enable _ s) changes from 1 to 0 again, a write transmission request indicating that the second write buffer is enabled is generated, and thus the transmission start flag (trans _ start) changes to 1 again (as indicated by the second dotted circle in fig. 5). At this time, the corresponding FIFO non-full signal (FIFO _ full) is 1, which indicates that the buffer status of the FIFO is full. Therefore, the source clock domain handshake signal generation circuit needs to wait for the buffer status of the FIFO to become non-full, and then the source clock domain handshake signal generation circuit will pull up the source clock domain handshake signal (ready _ s) (as shown by the second solid line circle from left to right in fig. 5), and the transmission start detection circuit will generate the FIFO write signal corresponding to the first transmission request (as shown by the second arrow from left to right in fig. 5). And storing the information which is required to be buffered by the current write transmission request into the FIFO according to the generated FIFO write signal. Specifically, the source clock domain handshake signal may be set to the inverted value when the FIFO non-full signal (FIFO _ full) becomes 0.

It should be appreciated that if the current transfer request is a read transfer or a write cache not enabled write transfer, the source clock domain handshake signal is pulled high after the destination clock domain transfer is completed.

In addition, the APB bus protocol generation circuit is configured to determine whether to read the buffered information from the FIFO according to the buffer status of the read end of the FIFO. When the buffer state of the reading end of the FIFO is non-empty, the APB bus protocol generating circuit reads and analyzes the information buffered in the FIFO, and generates control and write data signals which accord with the APB protocol in a target clock domain.

Further optimally, the destination clock domain APB port generates a destination clock domain handshake signal (ready _ d), and determines whether the destination clock domain handshake signal (ready _ d) needs to be synchronized to the source clock domain according to the write buffer enable signal (wbuf _ en _ d) and the destination clock domain direction signal (pwrite _ d) synchronized to the destination clock domain, specifically:

if the write cache enable signal (wbuf _ en _ d) and the destination clock domain direction signal (pwrite _ d) are both 1, then the transfer indicating the current destination clock domain is a write cache enabled write transfer. Because the source clock domain handshake signal generation circuit returns handshake signals in advance, the destination clock domain handshake signal (ready _ d) does not need to be synchronized to the source clock domain at the moment;

otherwise, the destination clock domain handshake signal (ready _ d) is synchronized to the source clock domain and assigned to the source clock domain handshake signal (ready _ s).

Furthermore, the destination clock domain data signal (prdata _ d) is assigned to the source clock domain data signal (prdata _ s) and the destination clock domain error response signal (pslverr _ d) is assigned to the source clock domain error response signal (pslverr _ s).

Example two: two consecutive writes buffer enabled writes (assuming the buffer status of the FIFO is not full)

The overall working flow of combining the parts of the APB bus bridge to generate the source clock domain handshake signals is shown in fig. 6, which is described in detail as follows:

it is assumed in this example that the buffer status of the FIFO remains always not full (i.e. the signal is 0), as shown in fig. 6 the waveform diagram of the FIFO not full signal (FIFO _ full) is not shown. As shown in FIG. 6, both write transfer requests are write buffer enabled write transfer operations. As indicated in the figure, after receiving the write transmission request in the source clock domain, since the buffer status of the FIFO is not full, the buffer information is written into the FIFO, and the source clock domain handshake signals are pulled up (as indicated by the first and second circles and arrows from left to right in the figure), without waiting for the handshake signal (ready _ d) returned by the destination clock domain. The transmission of the two write buffer enable can be completed only by 4 source clock cycles at the source clock domain end, and handshake signals of the source clock domain are respectively returned. At the destination clock domain, it is necessary to wait for a period of time before actually writing the data to the destination (as indicated by the third and fourth circles and arrows from left to right in the figure).

Therefore, according to the technical scheme, the write input operation enabled by the write cache can be speeded up by returning the handshake signal of the source clock domain in advance, and the CPU is released in advance to perform other operations.

Example three: one write buffer enabled write input is followed by one non-write buffer enabled write input (assuming that the buffer status of the FIFO is not full)

The overall working flow of the parts of the APB bus bridge combined to generate the source clock domain handshake signals is shown in fig. 7, which is described in detail as follows:

it is assumed in this example that the buffer status of the FIFO remains always not full (i.e. the signal is 0), as shown in fig. 7 the waveform diagram of the FIFO not full signal (FIFO _ full) is not shown. As shown in FIG. 7, a write buffer enabled write input is followed by a non-write buffer enabled write input. As identified in fig. 7, for the first write buffer enabled write input operation, after receiving the write transfer request in the source clock domain, since the buffer status of the FIFO is not full, the buffer information is written into the FIFO, and the source clock domain handshake signals are pulled up (as identified by the first circle and arrow from left to right in the figure) without waiting for the handshake signal (ready _ d) returned by the destination clock domain. The second write input request is a non-write buffer enabled write input operation (as indicated by the second circle and arrow from left to right in the figure), and therefore, the second write input request needs to return (as indicated by the fourth circle and arrow in the figure) the destination domain handshake signal (ready _ d) corresponding to the second non-write buffer enabled write operation after all buffer write operations before the destination clock domain is completed, so as to generate the source clock domain handshake signal (ready _ s) (as indicated by the fifth circle and arrow from left to right in the figure).

Example four: two non-write cache enabled write inputs (assuming that the cache states of the FIFO are all not full)

The overall working flow of the parts of the APB bus bridge combined to generate the source clock domain handshake signals is shown in fig. 8, which is described in detail as follows:

it is assumed in this example that the buffer status of the FIFO remains always not full (i.e. the signal is 0), as shown in fig. 8, the waveform diagram of the FIFO not full signal (FIFO _ full) is not shown. As shown in FIG. 8, two non-write cache enabled write inputs. As identified in fig. 8, for the first non-write cache enabled write input operation, after receiving the write transmission request in the source clock domain, because the non-write cache enabled write input operation, it is necessary to wait until the destination clock domain completes all the cache write operations before the destination clock domain completes (as identified by the second circle and arrow from left to right in the figure), and return the destination domain handshake signal (ready _ d) corresponding to the first non-write cache enabled write operation for generating the source clock domain handshake signal (ready _ s) (as identified by the third arrow from left to right in the figure). Similarly, for the second non-write buffer enabled write input operation, after the write transfer request is received in the source clock domain, because the write transfer request is a non-write buffer enabled write input, it is necessary to wait until all buffer write operations before the destination clock domain is completed (as indicated by the fourth circle and arrow from left to right in the figure), and return the destination domain handshake signal (ready _ d) corresponding to the second non-write buffer enabled write operation to generate the source clock domain handshake signal (ready _ s) (as indicated by the sixth arrow from left to right in the figure).

Example five: one write cache enabled write input operation is followed by one read operation (assuming the FIFO cache status is not full)

The overall workflow of combining portions of an APB bus bridge to generate source clock domain handshake signals is shown in fig. 9, and is described in detail as follows:

it is assumed in this example that the buffer status of the FIFO remains always not full (i.e. the signal is 0), as shown in fig. 9 the waveform diagram of the FIFO not full signal (FIFO _ full) is not shown. As shown in FIG. 9, a write-cache enabled write-in operation is followed by a read operation. As identified in fig. 9, for the first write buffer enabled write input operation, after receiving the write transfer request in the source clock domain, since the buffer status of the FIFO is not full, the buffer information is written into the FIFO, and the source clock domain handshake signals are pulled up (as identified by the first circle and arrow from left to right in the figure) without waiting for the handshake signal (ready _ d) returned by the destination clock domain. The second pen request is a read operation (as indicated by the second circle and arrow from left to right in the figure), and therefore, after all the cache write operations before the destination clock domain is completed, the read transferred data (prdata _ d) and the read transferred error response signal (pslverr _ d) need to be returned to the source clock domain, and the destination domain handshake signal (ready _ d) corresponding to the second read operation is returned (as indicated by the fourth circle and arrow in the figure) for generating the source clock domain handshake signal (ready _ s) (as indicated by the fifth circle and arrow from left to right in the figure).

EXAMPLE III

In the third embodiment, a specific example of an APB bus bridge across clock domains is provided. Fig. 10 is a block diagram illustrating an architecture of an APB bus bridge 1000 across clock domains according to an embodiment of the present disclosure. The APB bus bridge 1000 according to the present embodiment includes the following parts: the device comprises a source clock domain port, a destination clock domain port, a transmission start detection circuit, a write cache enable synchronization circuit, a FIFO (first in first out), an APB (advanced peripheral bus) bus protocol generation circuit and a source clock domain handshake signal generation circuit. Wherein: the source clock domain handshake signal generation circuit comprises a handshake signal synchronization module (ready synchronization module), a selector and an AND gate.

Wherein the source clock domain port is configured for connecting a master device operating in the source clock domain; the destination clock domain port is configured to be used for connecting one or more APB slave devices working in a destination clock domain, wherein the APB slave devices can be peripheral registers; the transmission start detection circuit is configured to generate a transmission start flag (trans _ start) when a transmission request occurs; the write cache enabling synchronization circuit is configured to trigger synchronization of a write cache enabling signal (wbuf _ en) by the transmission start flag to obtain a write cache enabling synchronization signal (wbuf _ en _ sync), wherein the synchronization keeps the write cache enabling synchronization signal unchanged in the process of current transmission; the FIFO is configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; the APB bus protocol generation circuit is configured to read and analyze information buffered in the FIFO from the FIFO and generate a destination clock domain write data signal in a destination clock domain, and is further configured to acquire a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain; the source clock domain handshake signal generation circuit is configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write buffer enabled write transmission and a buffer state of the FIFO; wherein, the first and the second end of the pipe are connected with each other,

The technical scheme of the application can support the dynamic switching of the write cache enabling signal (wbuf _ en), and the rewrite cache enabling signal (wbuf _ en) can come from a register or buffer information in an awcache signal in an AXI protocol.

When a plurality of registers need to be configured at one time and a plurality of writing transmission operations exist, the system speed is obviously accelerated, and if the writing data are required to be ensured to be really written to the destination end, a writing operation of reading or a non-cache writing operation is added after the writing operation.

Example four

In a fourth embodiment, a method of cross-clock domain access performed by an APB bus bridge is provided. Figure 11 is a flow diagram illustrating a method of cross clock domain access performed by an APB bus bridge, according to an embodiment of the present disclosure. The APB bus bridge according to the present embodiment includes the following parts: a source clock domain port for connecting a master device operating in a source clock domain; a destination clock domain port for connecting one or more APB slave devices operating in a destination clock domain; a transmission start detection circuit; a write cache enable synchronization circuit; a FIFO for buffering write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; APB bus protocol generating circuit; and a source clock domain handshake signal generation circuit configured to select a source generating the source clock domain handshake signal according to whether a current transmission is a write buffer enabled write transmission and a buffer status of the FIFO. Wherein the APB slave may be a peripheral register, by way of example and not limitation.

A method for cross-clock domain access performed by an APB bus bridge, comprising, when a transfer request occurs, performing the steps of:

step 1: a transmission start detection circuit generates a transmission start flag;

step 2: triggering a write cache enabling synchronization circuit to execute synchronization of a write cache enabling signal by a transmission starting mark so as to obtain the write cache enabling synchronization signal, wherein the synchronization keeps the write cache enabling synchronization signal unchanged in the current transmission process;

and 3, step 3: determining whether to pull up a source clock domain handshake signal (ready _ s) by a source clock domain handshake signal generating circuit according to whether current transmission is write transmission enabled by write cache and the cache state of FIFO; if the current transmission is write buffer enabled write transmission, after waiting for the buffer information required by the current transmission to be written into the FIFO, raising a source clock domain handshake signal, wherein when a transmission start detection circuit generates a transmission start mark and the buffer state of the FIFO is not full, a FIFO write signal is generated and triggers to write the buffer information required by the current transmission into the FIFO; and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshaking signal after waiting for the generation of the target clock domain handshaking signal.

Preferably, the method may further comprise:

and 4, step 4: the APB bus protocol generation circuit reads and analyzes information buffered in the FIFO from the FIFO and generates a destination clock domain write data signal in a destination clock domain, and the APB bus protocol generation circuit also acquires a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain.

Specific examples

In a fifth embodiment, an APB bus bridge across clock domains is provided. Fig. 12 is a schematic block diagram illustrating an APB bus bridge across clock domains, according to a specific example of the present disclosure. The APB bus bridge includes: the device comprises a source clock domain port, a destination clock domain port, an FIFO, an APB bus protocol generation module and a source clock domain handshake signal (ready _ s) generation module;

a transmission start detection module configured to generate a transmission start flag (trans _ start) when a transmission request occurs;

a FIFO configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full;

an APB bus protocol generation module configured to read and parse information buffered in the FIFO from the FIFO and generate a destination clock domain control signal and a destination clock domain write data signal in a destination clock domain, wherein the destination clock domain control signal includes a destination clock domain handshake signal (ready _ d);

a source clock domain handshake signal generation module configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether current transmission is write buffer enabled write transmission and a buffer state of the FIFO; by way of example and not limitation, the source clock domain handshake signal generation module includes an edge synchronization module and a read or non-buffered write completion signal generation module. In the specific implementation process, firstly, a read or non-cache write completion signal generation module generates a completion signal (done _ d), wherein the completion signal (done _ d) is a single-cycle pulse signal; the monocycle signal is synchronized to the source clock domain by an edge synchronization module by using an edge synchronization method so as to generate a source clock domain (ready _ s) signal. When the destination domain chip select signal (psel _ d), the destination domain enable signal (enable _ d) and the destination clock domain handshake signal (ready _ d) are simultaneously 1, and the operation of the destination domain is a read operation or a non-cache write operation, the completion signal (done _ d) is set to 1. Furthermore, the read transferred data (prdata _ s) and the read transferred error response signal (pslverr _ s) of the source clock domain need to be updated to the read transferred data (prdata _ d) and the read transferred error response signal (pslverr _ d) of the destination clock domain when the completion signal (done _ d) is 1. By this buffering operation, it is ensured that after the transfer of the destination clock domain is completed, even if the read transferred data (prdata _ d) and the read transferred error response signal (pslverr _ d) of the destination clock domain have changed and the transfer of the source clock domain has not been completed, errors of the read transferred data (prdata _ s) and the read transferred error response signal (pslverr _ s) obtained by the source clock domain do not occur.

Preferably, the APB bus bridge includes a write buffer enable synchronization module configured to trigger synchronization of the write buffer enable signal (wbuf _ en) by the transmission start flag to obtain the write buffer enable synchronization signal (wbuf _ en _ sync), wherein the synchronization is such that the write buffer enable synchronization signal remains unchanged during the current transmission. According to the technical scheme, the clock domain crossing APB bus bridge is creatively designed, through a connection method and an interactive working mode of each unit in a system, FIFO is used for realizing clock domain crossing access, a write cache enabling synchronizing circuit is triggered through a transmission start mark (trans _ start) to synchronize a write cache enabling signal (wbuf _ en), and then a source clock domain handshake signal generating circuit is used for realizing early return of a write input operation of write cache enabling to a source clock domain handshake signal without waiting for completion of a corresponding write input operation of a destination terminal. Thus, switching between write cache enabled and non-write cache enabled write operations may be performed dynamically.

The invention uses FIFO buffer to write data and control information, and decides whether to return the source clock domain handshake signal (ready _ s) in advance according to the control signal to finish the write transmission in advance, thereby realizing the acceleration of write transmission when the write buffer option is enabled, enabling the CPU (central processing unit) and the bus in the system to finish the register configuration operation in advance, processing other affairs, and greatly improving the efficiency of the system.

In addition, the invention can support both synchronous and asynchronous clock crossing domains, if the synchronous clock crosses the clock domains, the FIFO uses the synchronous FIFO, otherwise, the asynchronous FIFO is used; the FIFO uses an asynchronous FIFO if the clocks of the source and destination clock domains are asynchronous clocks.

The invention adopts a method for dynamically enabling the write cache function, so that write cache enabling switches of each write transmission can be the same or different, and write acceleration options are increased while the method is compatible with the traditional APB clock domain crossing method.

The technical scheme of the invention is applied to an MCU (micro control unit) chip, and the feasibility of the technical scheme is proved by a simulation result and an FPGA test.

In general, the various embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While various aspects of the embodiments of the disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

By way of example, embodiments of the disclosure may be described in the general context of machine-executable instructions (e.g., instructions included in program modules) being executed in a device on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between program modules as desired. Machine-executable instructions of program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain scenarios, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the disclosure has been described in language specific to structural features and/or methodological acts, it is to be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An APB bus bridge across clock domains, the APB bus bridge comprising:

a source clock domain port configured for connecting a master device operating in a source clock domain;

a destination clock domain port configured for connecting one or more APB slave devices operating in a destination clock domain;

a transmission start detection circuit configured to generate a transmission start flag (trans _ start) when a transmission request occurs;

a FIFO configured to buffer write data and control information, wherein the FIFO has a not full signal (-FIFO full) indicating whether the buffer of the FIFO is full;

an APB bus protocol generation circuit, configured to read and parse the information buffered in the FIFO from the FIFO, and generate a destination clock domain write data signal in the destination clock domain, the APB bus protocol generation circuit is further configured to obtain a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain;

a source clock domain handshake signal generation circuit configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether the current transmission is a write buffer enabled write transmission and a buffer status of the FIFO; wherein the content of the first and second substances,

if the current transmission is write transmission of write cache enabling, pulling up the source clock domain handshake signal after waiting for the cache information required by the current transmission to be written into the FIFO;

when the transmission start detection circuit generates the transmission start mark and the buffer status of the FIFO is not full, generating an FIFO write-in signal which triggers the buffer information required by the current transmission to be written into the FIFO;

2. The APB bus bridge of claim 1, wherein the cache information comprises write data including a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of a source clock domain APB port; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

3. The APB bus bridge of claim 2, wherein the APB bus bridge comprises a write cache enable synchronization circuit configured to trigger synchronization of a write cache enable signal (wbuf en) by the transfer start flag to obtain a write cache enable synchronization signal (wbuf en _ sync), wherein the synchronization causes the write cache enable synchronization signal to remain unchanged during a current transfer.

4. The APB bus bridge of claim 3, wherein the write cache enable synchronization circuit to perform synchronization of the write cache enable signal (wbuf _ en) comprises:

5. The APB bus bridge of claim 1, wherein if the clocks of the source and destination clock domains are synchronous clocks, the FIFOs use synchronous FIFOs with two clock ports; the FIFO uses an asynchronous FIFO if the clocks of the source clock domain and the destination clock domain are asynchronous clocks.

6. The APB bus bridge of any one of claims 1-5, wherein the APB bus bridge is implemented on an SoC platform based on AMBA protocol.

7. The APB bus bridge of any one of claims 1-5, wherein the APB bus bridge is directly connected to an APB host.

8. The APB bus bridge of claim 7, wherein the APB bus bridge is connected to an AXI protocol bus or an AHB protocol bus via a protocol translation bus bridge.

9. A method of cross-clock domain access performed by an APB bus bridge,

the APB bus bridge includes: a source clock domain port for connecting a master device operating in a source clock domain; destination clock domain ports for connecting one or more APB slave devices operating in a destination clock domain; a transmission start detection circuit; a write cache enable synchronization circuit; a FIFO for buffering write data and control information, wherein the FIFO has a not full signal (-FIFO _ full) indicating whether the buffer of the FIFO is full; APB bus protocol generating circuit; and a source clock domain handshake signal generation circuit configured to select a source that generates the source clock domain handshake signal according to whether the current transmission is write transmission enabled by write buffer and a buffer state of the FIFO;

the method comprises, when a transmission request occurs, performing the steps of:

the transmission start detection circuit generates a transmission start flag;

triggering the write cache enabling synchronization circuit to execute synchronization of a write cache enabling signal by the transmission starting mark so as to obtain the write cache enabling synchronization signal, wherein the synchronization enables the write cache enabling synchronization signal to be kept unchanged in the current transmission process;

determining whether to pull up a source clock domain handshake signal (ready _ s) by the source clock domain handshake signal generation circuit according to whether the current transmission is write transmission enabled by write cache and the cache state of FIFO; if the current transmission is write buffer enabled write transmission, after waiting for the buffer information required by the current transmission to be written into the FIFO, pulling up the source clock domain handshake signal, wherein when the transmission start detection circuit generates the transmission start mark and the buffer state of the FIFO is not full, generating an FIFO write signal which triggers the buffer information required by the current transmission to be written into the FIFO; and if the current transmission is read transmission or write transmission which is not enabled by the write cache, pulling up the source clock domain handshaking signal after waiting for the generation of the target clock domain handshaking signal.

10. The method of claim 9, further comprising performing the steps of:

the APB bus protocol generation circuit reads and analyzes the information buffered in the FIFO from the FIFO and generates a destination clock domain write data signal in the destination clock domain, and the APB bus protocol generation circuit also acquires a destination clock domain handshake signal (ready _ d) input by an APB bus of the destination clock domain.

11. The method of claim 10, wherein the cache information comprises write data, the write data comprising a direction signal (pwrite), a write data signal (pwdata), a write strobe signal (pstrb), and an address signal (paddr) of a source clock domain APB port; wherein if the direction signal (pwrite) is equal to 1, then the current transfer is a write input; if the direction signal (pwrite) is equal to 0, then the current transfer is a read input.

12. The method of claim 11, wherein the write cache enable synchronization circuitry performing synchronization of a write cache enable signal comprises:

when the value of the transmission start flag is 1, the write cache enable synchronization signal is assigned as a write cache enable signal, and the registered write cache enable signal (wbuf _ en _ reg) is updated as the write cache enable signal;

13. An APB bus bridge across clock domains, the APB bus bridge comprising: the device comprises a source clock domain port, a destination clock domain port, an FIFO, an APB bus protocol generation module and a source clock domain handshake signal (ready _ s) generation module;

an APB bus protocol generation module configured to read and parse information buffered in the FIFO from the FIFO and generate a destination clock domain control signal and a destination clock domain write data signal in the destination clock domain, wherein the destination clock domain control signal includes a destination clock domain handshake signal (ready _ d);

a source clock domain handshake signal generation module configured to determine whether to pull up a source clock domain handshake signal (ready _ s) according to whether the current transmission is write buffer enabled write transmission and a buffer status of the FIFO; wherein the content of the first and second substances,

14. The APB bus bridge of claim 13, wherein the APB bus bridge comprises a write cache enable synchronization module configured to trigger synchronization of a write cache enable signal (wbuf en) by the transfer start flag to obtain a write cache enable synchronization signal (wbuf en _ sync), wherein the synchronization is such that the write cache enable synchronization signal remains unchanged during a current transfer.

15. The APB bus bridge of any one of claims 13-14, wherein the APB bus bridge is directly connected to an APB host.

16. The APB bus bridge of claim 15, wherein the APB bus bridge is connected to an AXI protocol bus or an AHB protocol bus via a protocol translation bus bridge.