CN107562674B - Bus protocol asynchronous logic circuit implementation device embedded into processor - Google Patents

Abstract

A bus protocol asynchronous logic circuit implementation device of an embedded processor is used for converting access sequential logic of the embedded processor into ahb _ bus access protocol of standard AMBA; the device comprises an embedded processor, a bus protocol asynchronous logic module and an AMBA module which are controlled by the same clock; under the condition that the data bit width of the embedded processor bus and the data bit width of the ahb _ bus of the AMBA module are multiple, the data exchange between the embedded processor and the system bus across the clock domain can be processed, more bit width data buses can be used, more data can be transmitted at the same time under the same clock frequency, and the bandwidth performance is improved. The invention solves the problem that a specific embedded processor uniformly accesses the interface of the external equipment, namely, the aim of universal access is realized by using smaller logic circuit resources.

Description

Bus protocol asynchronous logic circuit implementation device embedded into processor

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a logic design belonging to chip hardware, and particularly relates to a bus protocol asynchronous logic circuit implementation device applied to an embedded processor.

Background

Since the advent of microprocessors, embedded systems have been rapidly developed, and the embedded processor is certainly the core part of the embedded system, and the embedded processor is directly related to the performance of the whole embedded system. An embedded processor (e.g., MicroController Unit; MCU) is generally referred to as a general term for computing and controlling core devices in an embedded system, is a core of the embedded system, and is a hardware Unit for controlling and assisting the operation of the system.

The embedded processor has a plurality of design schemes, different architectures and different characteristics, but essentially works based on a certain clock synchronization, and the embedded processor sequentially initiates a series of data interaction operations such as reading, waiting and writing.

It is clear to those skilled in the art that the most fundamental role of the bus is to uniformly convert various interface protocols so that the modules can interact with each other. The bus performance is embodied as: data bit width, clock delay, operating frequency freq, latency, theoretical maximum bandwidth, average data throughput, and actually measured random read-write comprehensive efficiency.

There are four basic types of operations on a typical bus: read, Write, wait for Stall, and Done, abbreviated as R/W/S/D, respectively. Generally, the access interface of an embedded processor includes multiple stages of addressing, read/write out, wait, response, and so on. The interface protocol for embedded processors is relatively complex and may include instructions and data, typically including different directions of reading and writing.

Referring to FIG. 1, FIG. 1 is a schematic diagram illustrating a single write-out timing sequence of an embedded processor in the prior art; as shown, the embedded processor is a 32-bit machine, Read is a Read request signal, Write is a Write request signal, Addr [31:2] is an access address, BE [3:0] is a Write byte valid, WData [31:0] is Write data, Stall is a pause waiting flag, and Clk is a synchronous clock.

Referring to FIG. 2, FIG. 2 is a timing diagram illustrating a single read operation of an embedded processor according to the prior art. As shown, the embedded processor is a 32-bit machine, Read is a Read request signal, Write is a Write request signal, Addr [31:2] is an access address, BE [3:0] is a Write byte valid, WData [31:0] is Write data, Stall is a pause wait flag, RData [31:0] is Read data, RBE [3:0] is a Read byte valid, and Clk is a synchronous clock.

As can be seen from fig. 1 and 2, it is impossible for the Read request signal Read/Write request signal Write operations to be simultaneously issued, i.e., when the Read request signal Read in fig. 1 is at a low level, a single Write request signal Write operation can be performed; similarly, when the Write request signal Write in fig. 2 is operated at a low level, the single Read request signal Read operation can be performed.

Generally, in order to improve performance, the operating frequency of the embedded processor may be higher, and there are more devices connected to the bus, and the operating clock of the synchronous bus must be lower or higher.

To solve this conflict, it is also considered in the industry to implement protocol conversion by using an asymmetric asynchronous circuit, so that the embedded processor and the bus peripherals connected to the embedded processor operate at different frequencies to achieve the maximum bandwidth. However, the design method of the clock domain crossing asynchronous circuit is complicated.

Disclosure of Invention

The invention aims to provide a method for realizing bus protocol conversion bridging applied to an embedded processor, which converts access sequential logic of a specific embedded processor into ahb _ bus access protocol of mainstream standard AMBA of an embedded system so as to realize that all logic of data storage processing based on the embedded processor is completed in the same clock domain without considering an asynchronous circuit design method crossing the clock domains.

In order to achieve the purpose, the technical scheme of the invention is as follows:

an embedded processor bus protocol asynchronous logic circuit implementation apparatus for converting the embedded processor access timing logic to the ahb _ bus access protocol of standard AMBA; the data bit width of the embedded processor is N, the data bit width M of the ahb _ bus of the standard AMBA is an integral multiple of N, or the data bit width N of the embedded processor is an integral multiple of the data bit width M of the ahb _ bus of the standard AMBA, wherein N, M is a power of 2; the system is characterized by comprising an embedded processor, a bus protocol asynchronous logic module and an AMBA module; the clock signal Clk is connected with the embedded processor and the clock input ends of the bus protocol asynchronous logic module, and the bus clock HCLK is connected with the clock input ends of the bus protocol asynchronous logic module and the AMBA module; the clock signal Clk and the bus clock HCLK are asynchronous clocks;

the bus protocol asynchronous logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module; the embedded processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [ N-1:2], a Write byte valid BE [3:0] and Write data WData [ N-1:0] to the first interface unit, and the first interface unit inputs a pause waiting flag Stall, Read data RData [ N-1:0] and a Read byte valid RBE [3:0] to the embedded processor; the second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [ M-1:0], write data HWRITE, and write data bus HWDATA [ M-1:0] to the AMBA module; the AMBA module inputs the bus state mark HREADY and a read data bus HRDATA [ M-1:0] into the second interface unit;

the conversion unit performs the following operations:

the output address bus Addr [ N-1:2] of the embedded processor is expanded to an access address bus HADDR [ M-1:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [ M-1:0] correspond to BE [3:0] output by the embedded processor or keep the two bits of BE [3:0] to BE 0;

the Read request signal Read/Write request signal Write output by the embedded processor is equivalent to Write data HWRITE of the AMBA module;

the write-out data WData [ N-1:0] output by the embedded processor is equivalent to the write data bus HWDATA [ M-1:0] of the AMBA module;

the input pause waiting marking Stall of the embedded processor is derived from the output of the bus protocol asynchronous logic module, and the logic of the pause waiting marking Stall depends on the bus state marking HREADY of the AMBA module;

the input RData [ N-1:0] of the embedded processor is derived from the output of the bus protocol asynchronous logic module, if the data bit width N of the embedded processor is larger than Y times of the data bit width M of the ahb _ bus of the standard AMBA, the bus protocol asynchronous logic module sends data for Y times, and the numerical bit width of each output is equal to the numerical bit width of an access address bus HRDATA [ M-1:0] of the AMBA module; wherein Y is a positive integer greater than or equal to 1;

if the data bit width N of the embedded processor is less than X times of the data bit width M of the ahb _ bus of the standard AMBA, the output numerical bit width of the bus protocol asynchronous logic module is equal to the numerical bit width of X times of an access address bus HRDATA [ M-1:0] of the AMBA module; that is, the access address bus HRDATA [ M-1:0] of the AMBA module receives the output value of the bus protocol asynchronous logic module for X times; x is a positive integer greater than 1;

an input read byte valid RBE [3:0] of the embedded processor is derived from the output of the bus protocol asynchronous logic module, logically dependent on an output write byte valid BE [3:0] of the embedded processor and valid concurrently with read data RData [ N-1:0 ];

the embedded processor's inputs RBE [3:0] are derived from the output of the bus protocol asynchronous logic module whose logic depends on the embedded processor's outputs BE [3:0] being active simultaneously with RData [ N-1:0 ];

control signal HTARNS corresponds to a case where the output Read request signal Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are simultaneously valid.

Preferably, said N is selected from one of 8, 16, 32, 64 and 128; the M is selected from one of 8, 16, 32, 64 and 128.

It can be seen from the above technical solutions that the technical solution adopted by the bus protocol asynchronous logic circuit implementation device embedded in the processor of the present invention has the following beneficial effects:

①, because the AMBA bus is the mainstream standard of the embedded system, the invention converts the access time sequence logic of the specific embedded processor into the ahb _ bus access protocol of the standard AMBA, namely, the embedded processor can carry out data interaction with the bus peripheral connected with the embedded processor in real time, namely, the embedded processor can work under the high-frequency condition of the embedded processor, thereby improving the working efficiency;

②, based on the data storage processing of the embedded processor, all the logics of the invention are completed in the same clock domain, and the design method of the asynchronous circuit crossing the clock domain is not considered;

③, the interface of the external device is accessed uniformly by the special embedded processor, the purpose of general access can be realized by using smaller logic circuit resources;

④, respectively realizing the transmission of address, data and control according to the characteristics of the access interface of the embedded processor;

⑤, flexible use of combination circuit and sequential circuit to reduce waiting, that is, use of synchronous queue to realize pipeline operation and increase working clock frequency, use of asynchronous queue to reduce waiting, realize pipeline operation and increase working clock frequency, use of asymmetric queue to realize maximum bandwidth in embedded processor and external bus space working under different frequency.

Drawings

FIG. 1 is a timing diagram of a single write operation of an embedded processor according to the prior art

FIG. 2 is a timing diagram of single read in of an embedded processor in the prior art

FIG. 3 is a diagram illustrating ahb _ bus timing of a generic AMBA

FIG. 4 is a circuit diagram of an apparatus for implementing bus protocol asynchronous logic circuit embedded in a processor according to the present invention

FIG. 5 is a schematic diagram of a signal combination circuit for outputting a second interface unit of a bus protocol asynchronous logic module to an AMBA module according to an embodiment of the present invention

FIG. 6 is a schematic diagram of a signal combination circuit for outputting a first interface unit of a bus protocol asynchronous logic module to an embedded processor according to an embodiment of the present invention

Detailed Description

The following describes the embodiments of the present invention in further detail with reference to fig. 3 to 6.

It should be noted that, the application scenarios of the embedded processors are very different, the portability/compatibility of the access interface is of great importance, and AMBA is almost a de facto standard in the embedded chip system.

Referring to fig. 3, fig. 3 is a timing diagram of ahb _ bus of the generic AMBA; as shown, unlike the single read/write time domain usage of the embedded processor, the Address phase and data phase are performed in different time domains. For example, data width is 32, HCLK is ahb _ bus clock signal of AMBA, HADDR [63:0] is access address bus, Control is bus Control signal, and bus Control signal includes HTRANS and write request signal HWRITE. HWDATA [63:0] is the write data bus, HREADY is the bus status indicator, and HRDATA [63:0] is the read data bus.

The invention discloses a device for realizing bus protocol asynchronous logic circuit of an embedded processor, which is mainly used for converting access sequence logic of the embedded processor into ahb _ bus access protocol of standard AMBA, namely converting a storage interface of the embedded processor into ahb _ bus access protocol of AMBA through a bus protocol asynchronous logic module (bridge).

In an embodiment of the present invention, the data bit width of the embedded processor may be generally selected to be a power of 2, and assuming that the data bit width of the embedded processor is N, the data bit width M of the ahb _ bus of the standard AMBA may be an integer multiple of N, or the data bit width N of the embedded processor may be an integer multiple of the data bit width M of the ahb _ bus of the standard AMBA, where N, M is a power of 2.

In the embodiment of the present invention, N may be selected from a number of powers of 2, and preferably, N may be selected from one of 8, 16, 32, 64, and 128, for example. M may also be selected from a number to the power of 2, and preferably, M may be selected from one of 8, 16, 32, 64 and 128. That is, M may be greater than, equal to, or less than N.

It should be noted that, in the embodiment of the present invention, if the data bit width N of the embedded processor is greater than Y times of the data bit width M of the ahb _ bus of the standard AMBA, the bus protocol asynchronous logic module sends data for Y times, and the bit width of the output value at each time is equal to the bit width of the access address bus HRDATA [ M-1:0] of the AMBA module; wherein Y is a positive integer of 1 or more.

If the data bit width N of the embedded processor is less than X times of the data bit width M of the ahb _ bus of the standard AMBA, the output numerical bit width of the bus protocol asynchronous logic module is equal to the numerical bit width of X times of an access address bus HRDATA [ M-1:0] of the AMBA module; that is, the access address bus HRDATA [ M-1:0] of the AMBA module receives the output value of the X-time bus protocol asynchronous logic module; x is a positive integer greater than 1.

For convenience of description, the following embodiments take the example that the data bit width N of the embedded processor is 32, and the bit width of the ahb _ bus of the standard AMBA is 64 as an example, and the descriptions of other bit widths are omitted.

Referring to fig. 4, fig. 4 is a circuit diagram of an apparatus for implementing bus protocol asynchronous logic circuit embedded in a processor according to the present invention. As shown, the apparatus includes an embedded processor, a bus protocol asynchronous logic module, and an AMBA module. The clock signal Clk is connected with the clock input ends of the embedded processor and the bus protocol asynchronous logic module, and the bus clock HCLK is connected with the clock input ends of the bus protocol asynchronous logic module and the AMBA module. The clock signal Clk and the bus clock HCLK are asynchronous clocks.

The embedded processor includes output terminals of the embedded processor outputting a Read request signal Read, a Write request signal Write, an access address Addr [31:2], a Write byte valid BE [3:0], and Write data WData [31:0], and input terminals of a pause wait flag Stall, Read data RData [63:0], and a Read byte valid RBE [7:0 ].

The AMBA module includes inputs for control signals HTRANS [1:0], access address bus HADDR [63:0], write data HWRITE, and write data bus HWDATA [63:0], and outputs for bus state identification HREADY and read data bus HRDATA [63:0 ].

The bus protocol asynchronous logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module.

The embedding processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [31:2], a Write byte valid BE [3:0] and Write data WData [31:0] to the first interface unit, which inputs a pause waiting flag Stall, Read data RData [63:0] and a Read byte valid RBE [7:0] to the embedding processor.

The second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [63:0], write data HWRITE, and write data bus HWDATA [63:0] to the AMBA module; the AMBA module inputs the bus state identification HREADY and the read data bus HRDATA [63:0] to the second interface unit.

In the above-mentioned hardware connection solution, the clock signal Clk and the bus clock HCLK may be from an external clock signal or an internal clock signal. For example, the sequential circuit seq may be implemented using a flip-flop.

In the embodiment of the present invention, the outputs of the first interface unit and the second interface unit of the bus protocol asynchronous logic module are both dependent on the inputs of the first interface unit and the second interface unit of the bus protocol asynchronous logic module. Specifically, the conversion unit of the bus protocol asynchronous logic module performs the following operations:

the output address bus Addr [31:2] of the embedded processor is expanded into an access address bus HADDR [63:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [63:0] correspond to BE [3:0] output by the embedded processor or keep the two bits of BE [3:0] to BE 0;

the Read request signal Read/Write request signal Write output by the embedded processor is equivalent to Write data HWRITE of the AMBA module; this is based on the fact that it is not possible for the embedded processor to issue Read/Write request signals Write simultaneously, so that the HWRITE equivalent Write request signal Write of AMBA can be used and vice versa^～HWRITE operates in response to the Read request signal Read.

The write-out data WData [31:0] output by the embedded processor is equivalent to the write data bus HWDATA [63:0] of the AMBA module.

The input pause waiting indication Stall of the embedded processor is derived from the output of the bus protocol asynchronous logic module, and the logic of the pause waiting indication Stall depends on the bus state indication HREADY of the AMBA module.

In this embodiment, X is 2, i.e., the embedded processor data bit width 32 is less than twice the data bit width 64 of the ahb _ bus of a standard AMBA, the access address bus HRDATA [63:0] of the AMBA module receives the output value of the bus protocol asynchronous logic module twice; the embedded processor input RData [63:0] is derived from the output of the bus protocol asynchronous logic module and has a value equal to both the high/low portions of HRDATA [63:0] of the AMBA.

An input read byte valid RBE [7:0] of an embedded processor is derived from the output of a bus protocol asynchronous logic module, whose logic depends on the output write byte valid BE [3:0] of the embedded processor and is valid concurrently with the read data RData [31:0 ].

The remainder of the signals between the bus protocol asynchronous logic module and the ahb _ bus of the AMBA module are relatively simple, and control signal HTARNS corresponds to the case where the output Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are simultaneously valid.

The logic of the combinational circuit of the output signal of the first interface unit and the output signal of the second interface unit of the bus protocol asynchronous logic module is described below.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a signal combination circuit for outputting the second interface unit of the bus protocol asynchronous logic module to the AMBA module according to the embodiment of the present invention. As shown, fig. 5 includes four combinational circuits (the combinational circuit is referred to as comb), an HTRANS combinational circuit, an HADDR combinational circuit, an HWRITE combinational circuit, and an HWDATA combinational circuit. In addition, in the embodiment of the present invention, a First-in First-out queue (FIFO) may be used to reduce the mutual latency between the ahb _ bus buses embedded in the processor and the AMBA module.

Suppose that: the internal variables of the bus protocol asynchronous logic module are:

valid＝(|BE[3:0])&(Read|Write)

the signals output to the AMBA module ahb _ bus are:

HTRANS＝{valid,1’b0}

HADDR＝Addr

HWRITE＝valid&Write&^～Read

HWDATA＝WData

referring to fig. 6, fig. 6 is a schematic diagram of a signal combination circuit outputted from the first interface unit of the bus protocol asynchronous logic module to the embedded processor according to the embodiment of the present invention. As shown, fig. 6 includes three combinational circuits (combinational circuit denoted comb), RData combinational circuit, Stall combinational circuit, and RBE combinational circuit. In addition, in the embodiment of the present invention, a First-in First-out queue (FIFO) may be used to reduce the mutual latency between the ahb _ bus buses embedded in the processor and the AMBA module.

Suppose that: the internal variables of the bus protocol asynchronous logic module are:

valid＝(|BE[3:0])&(Read|Write)

the signals output to the AMBA module ahb _ bus are:

RData＝HREADY？HRDATA:0

Stall＝HREADY

RBE＝HREADY？BE:0

in summary, considering that the AMBA bus is the mainstream standard for embedded systems, the bus protocol asynchronous logic circuit of the embedded processor of the present invention implements the conversion of the access timing logic of the device specific embedded processor into the ahb _ bus access protocol of the standard AMBA. Under the condition that the data bit width of the embedded processor bus and the data bit width of the ahb _ bus of the AMBA module are mutually multiple, the processor and the system bus which cross a clock domain can be processed, more bit width data buses can be used, more data can be transmitted at the same time under the same clock frequency, and the bandwidth performance is improved.

In addition, it should be emphasized that the bus protocol asynchronous logic circuit implementation device of the embedded processor of the invention solves the problem of uniformly accessing the interface of the external device by a specific embedded processor, and can realize the purpose of universal access by using smaller logic circuit resources.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (2)

1. An embedded processor bus protocol asynchronous logic circuit implementation apparatus for converting the embedded processor access timing logic to the ahb _ bus access protocol of standard AMBA; the data bit width of the embedded processor is N, the data bit width M of the ahb _ bus of the standard AMBA is an integral multiple of N, or the data bit width N of the embedded processor is an integral multiple of the data bit width M of the ahb _ bus of the standard AMBA, wherein N, M is a power of 2; the system is characterized by comprising an embedded processor, a bus protocol asynchronous logic module and an AMBA module; the clock signal Clk is connected with the embedded processor and the clock input end of the bus protocol asynchronous logic module, and the bus clock HCLK is connected with the clock input ends of the bus protocol asynchronous logic module and the AMBA module; the clock signal Clk and the bus clock HCLK are asynchronous clocks;

the bus protocol asynchronous logic module comprises a first interface unit for interacting data with the embedded processor, a conversion unit and a second interface unit for interacting data with the AMBA module; the embedded processor outputs a Read request signal Read, a Write request signal Write, an access address Addr [ N-1:2], a Write byte valid BE [3:0] and Write data WData [ N-1:0] to the first interface unit, and the first interface unit inputs a pause waiting flag Stall, Read data RData [ N-1:0] and a Read byte valid RBE [3:0] to the embedded processor; the second interface unit inputs control signals HTRANS [1:0], access address bus HADDR [ M-1:0], write data HWRITE, and write data bus HWDATA [ M-1:0] to the AMBA module; the AMBA module inputs a bus state mark HREADY and a read data bus HRDATA [ M-1:0] into the second interface unit;

the conversion unit performs the following operations:

the output address bus Addr [ N-1:2] of the embedded processor is expanded to an access address bus HADDR [ M-1:0] of the AMBA module, wherein the lower two bits [1:0] of the access address bus HADDR [ M-1:0] correspond to BE [3:0] output by the embedded processor or keep the two bits of BE [3:0] to BE 0;

the Read request signal Read/Write request signal Write output by the embedded processor is equivalent to Write data HWRITE of the AMBA module;

the write-out data WData [ N-1:0] output by the embedded processor is equivalent to the write data bus HWDATA [ M-1:0] of the AMBA module;

the input pause waiting marking Stall of the embedded processor is derived from the output of the bus protocol asynchronous logic module, and the logic of the pause waiting marking Stall depends on the bus state marking HREADY of the AMBA module;

the input RData [ N-1:0] of the embedded processor is derived from the output of the bus protocol asynchronous logic module, if the data bit width N of the embedded processor is larger than Y times of the data bit width M of the ahb _ bus of the standard AMBA, the bus protocol asynchronous logic module sends data for Y times, and the numerical bit width of each output is equal to the numerical bit width of an access address bus HRDATA [ M-1:0] of the AMBA module; wherein Y is a positive integer greater than or equal to 1;

if the data bit width N of the embedded processor is less than X times of the data bit width M of the ahb _ bus of the standard AMBA, the output numerical bit width of the bus protocol asynchronous logic module is equal to the numerical bit width of X times of an access address bus HRDATA [ M-1:0] of the AMBA module; that is, the access address bus HRDATA [ M-1:0] of the AMBA module receives the output value of the bus protocol asynchronous logic module for X times; x is a positive integer greater than 1;

an input read byte valid RBE [3:0] of the embedded processor is derived from the output of the bus protocol asynchronous logic module, logically dependent on an output write byte valid BE [3:0] of the embedded processor and valid concurrently with read data RData [ N-1:0 ];

the embedded processor's inputs RBE [3:0] are derived from the output of the bus protocol asynchronous logic module whose logic depends on the embedded processor's outputs BE [3:0] being active simultaneously with RData [ N-1:0 ];

control signal HTARNS corresponds to a case where the output Read request signal Read/Write request signal Write and Write byte valid BE [3:0] of the embedded processor are simultaneously valid.

2. The apparatus of claim 1, said N being selected from one of 8, 16, 32, 64, and 128; the M is selected from one of 8, 16, 32, 64 and 128.

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