CN107562674A - A kind of bus protocol asynchronous loogical circuit realization device of embedded processor - Google Patents

Abstract

The bus protocol asynchronous loogical circuit realization device of a kind of embedded processor, for the access sequential logic of embedded processor to be converted to standard AMBA ahb_bus bus access agreements；The device is included by the insertion processor of same clock control, bus protocol asynchronous logic module and AMBA modules；In the case where the data bit width and the data bit width of the ahb_bus buses of AMBA modules for being embedded in processor bus are in multiple, the data exchange between the insertion processor of cross clock domain and system bus can not only be handled, and more bit wide data/address bus can be used, the more data of simultaneous transmission, improve bandwidth performance under identical clock frequency.The present invention solves the interface problem of specific embedded processor Uniform Access external equipment, i.e., with less logic circuit resource, realizes the purpose of universal access.

Description

A kind of bus protocol asynchronous loogical circuit realization device of embedded processor

Technical field

The present invention relates to technical field of integrated circuits, more particularly to belong to the logical design of chip hardware, particularly A kind of bus protocol asynchronous loogical circuit realization device for being applied to embedded processor.

Background technology

Since the appearance of microprocessor, embedded system has obtained development at full speed, and embeded processor is certainly It is the core of embedded system, embeded processor is directly connected to the performance of whole embedded system.Under normal circumstances Embeded processor is (for example, micro-control unit MicroController Unit；MCU it is considered as) to being transported in embedded system Calculation and the total appellation of control core device, it is the core of embedded system, is control, the hardware cell of accessory system operation.

Embedded Processor scheme is numerous, and framework is different, has their own characteristics each, but inherently sees and be all based on some Clock works asynchronously, the volume of data interactive operations such as embeded processor is initiated to read in successively, waits, writes out.

It will be apparent to those skilled in the art that the most basic effect of bus is changed various interface protocols are unified so that each Module can be with interaction data.Bus performance is presented as：It is data bit width width, clock delay delay, working frequency freq, latent Cycle latency, theoretical maximum bandwidth bandwidth, average data handle up throughput, actual measurement random read-write overall efficiency The parameters such as efficiency.

There is following four classes basic operation on general bus：Read is read in, Write is write out, waits Stall, completes Done, point R/W/S/D is not abbreviated as it.Usually, the access interface of embedded processor includes addressing, reads in/write out, waits, responding etc. and be multiple Stage.The interface protocol of embeded processor is more complicated, can include instruction and data, generally comprises reading and writes out Different directions.

Referring to Fig. 1, Fig. 1, which show the single of embeded processor in the prior art, writes out time diagram；As schemed Show, embedded processor be 32 machines, and Read is reading request signal, and Write is write request signal, Addr [31:2] it is access Address, BE [3:0] it is effective for the section that writes, WData [31:0] it is write-in data, Stall waits sign for pause, and Clk is synchronous Clock.

Referring to Fig. 2, Fig. 2 show the single reading time diagram of embeded processor in the prior art.As schemed Show, embedded processor be 32 machines, and Read is reading request signal, and Write is write request signal, Addr [31:2] it is access Address, BE [3:0] it is effective for the section that writes, WData [31:0] sign, RData [31 are waited for pause for write-in data, Stall: 0] it is reading data, RBE [3:0] effective to read byte, Clk is synchronised clock.

Can be seen that from Fig. 1 and Fig. 2 read request signal Read/ write request signals Write operation be impossible simultaneously Send, i.e., be low level when the reading request signal Read in Fig. 1 is operated, can just carry out single write request signal Write is operated；Similarly, when the write request signal Write operations in Fig. 2 are low level, can just carry out single reading please Signal Read is asked to operate.

Usually, for embeded processor in order to improve performance, its working frequency may equipment that is higher, and being connected in bus More, the work clock of synchronous bus must be just low just not high, if the equipment connected in bus is operated in lower limit, they Working clock frequency quickly, that is, will not have the loss of performance between different sequential, therefore, embeded processor access interface Portable/compatibility is most important.

In order to solve this contradiction, industry makes to be embedded in processing it is contemplated that asymmetric asynchronous circuit realizes protocol conversion Device and the bus peripheral hardware being attached thereto realize maximum bandwidth in the case of being operated in different frequency.However, cross clock domain is asynchronous Circuit design method is more complicated.

The content of the invention

It is an object of the invention to provide one kind to be applied to embedded processor bus protocol conversion bridge joint implementation method, and it will The access sequential logic of specific embedded processor, be converted to the mainstream standard AMBA of embedded system ahb_bus bus access Agreement, to realize that whole logics of the data storage processing based on embedded processor are completed in same clock zone, it is not necessary to examine Consider the Asynchronous circuit design method of cross clock domain.

To achieve the above object, technical scheme is as follows：

The bus protocol asynchronous loogical circuit realization device of a kind of embedded processor, for depositing the embedded processor Sequential logic is taken to be converted to standard AMBA ahb_bus bus access agreements；Wherein, the data bit width of the embedded processor is N, and the data bit width M of the ahb_bus buses of the standard AMBA is N integral multiple, or the data bit of the embedded processor Wide N is the data bit width M of the ahb_bus buses of standard AMBA integral multiple, wherein, N, M are 2 power side；Its feature It is, including by embedded processor, bus protocol asynchronous logic module and AMBA modules；Described in the clock signal clk connection The input end of clock of embedded processor and the bus protocol asynchronous logic module, the bus clock HCLK connections bus The input end of clock of agreement asynchronous logic module and the AMBA modules；Wherein, the input clock Clk and bus clock HCLK For asynchronous clock；

The bus protocol asynchronous logic module include with the first interface unit of the embedded processor interaction data, turn Change unit and the second interface unit with the AMBA modules interaction data；The embedded processor output reads request signal Read, write request signal Write, access address Addr [N-1:2], write the effective BE [3 of section:0] and write-in data WData [N-1:0] the first interface unit is output to, the first interface unit, which will suspend, to be waited sign Stall, reads data RData[N-1:0] and byte effective RBE [3 is read:0] it is input to the embedded processor；The second interface unit, which will control, to be believed Number HTRANS [1:0], access address bus HADDR [M-1:0] data HWRITE and write-in data/address bus HWDATA [M-, are write 1:0] the AMBA modules are input to；The bus state is indicated HREADY and reads data/address bus by the AMBA modules HRDATA[M-1:0] it is input to the second interface unit；

The converting unit performs following operation：

The OPADD bus Addr [N-1 of the embedded processor:2] access address for expanding to the AMBA modules is total Line HADDR [M-1:0], wherein, the access address bus HADDR [M-1:0] low two [1:0] the corresponding embedded processing The BE [3 of device output:0] or keep BE [3:0] two are 0；

The reading request signal Read/ write request signals Write of the embedded processor output is equivalent to the AMBA The write-in data HWRITE of module；

Data WData [N-1 are write out in the embedded processor output:0] the write-in data of the AMBA modules are equivalent to Bus HWDATA [M-1:0]；

The input pause of the embedded processor waits sign Stall from the bus protocol asynchronous logic module Output, the pause wait sign Stall logic dependent on the bus state sign HREADY of the AMBA modules；

Input RData [the N-1 of the embedded processor:0] output of the bus protocol asynchronous logic module is derived from, If Y times of the data bit width M of ahb_bus buses of the data bit width N of the embedded processor more than the standard AMBA, institute State bus protocol asynchronous logic module and divide Y transmission data, the numerical value bit wide exported every time is equal to the access of the AMBA modules Address bus HRDATA [M-1:0] numerical value bit wide；Wherein, Y is the positive integer more than or equal to 1；

If the data bit width M of ahb_bus buses of the data bit width N of the embedded processor less than the standard AMBA X times, the output numerical value bit wide of the bus protocol asynchronous logic module is equal to the access address bus of the AMBA modules HRDATA[M-1:0] the numerical value bit wide of X/mono-；The access address bus HRDATA [M-1 of i.e. described AMBA modules:0] connect Receive the output numerical value of the X bus protocol asynchronous logic module；X is the positive integer more than 1；

The effective RBE [3 of byte is read in the input of the embedded processor:0] the bus protocol asynchronous logic module is derived from Output, its logic writes the effective BE [3 of section dependent on the output of the embedded processor:0], and with reading data RData [N- 1:0] while effectively；

The input RBE [3 of the embedded processor:0] output of the bus protocol asynchronous logic module is derived from, it is described The logic of bus protocol asynchronous logic module depends on the output BE [3 of the embedded processor:0], with RData [N-1:0] it is same Shi Youxiao；

The output that control signal HTARNS corresponds to the embedded processor reads request signal Read/ write request signals The Write and effective BE [3 of section that writes:0] while effective situation.

Preferably, a data of the N in 8,16,32,64 and 128；The M is selected from 8,16,32,64 and 128 In a data.

It can be seen from the above technical proposal that the bus protocol asynchronous loogical circuit realization device of the embedded processor of the present invention Used technical scheme, has the advantages that：

1., due to AMBA buses be the mainstream standard of embedded system, the present invention is the access specific embedded processor Sequential logic, be converted to standard AMBA ahb_bus bus access agreements；The bus peripheral hardware that i.e. the insertion processor is attached thereto Between can carry out data interaction in real time, i.e., embeded processor can work under high frequency situation possessed by itself, improve Operating efficiency；

2., the data storage processing based on embedded processor, whole logics of the invention are completed in same clock zone, The Asynchronous circuit design method of cross clock domain is not considered；

3., solve the interface of specific embedded processor Uniform Access external equipment, can be provided with less logic circuit Source, realize the purpose of universal access；

4., according to the access interface feature of embedded processor, realize address address, data data, control respectively Control is respectively transmitted；

5., flexibly use combinational circuit and sequence circuit, reduce wait；Isochronous queue is used, realizes pile line operation, Working clock frequency is improved, using asynchronous queue, reduces and waits, realize pile line operation, improve working clock frequency, use is non- Symmetrical queue, it can make to be embedded in processor and external bus Space-Work realizes maximum bandwidth in the case of different frequency.

Brief description of the drawings

Fig. 1 show the single time diagram write out of embeded processor in the prior art

Fig. 2 show the time diagram of the single reading of embeded processor in the prior art

Fig. 3 show general AMBA ahb_bus bus timing schematic diagrames

Fig. 4 show the circuit block diagram of the bus protocol asynchronous loogical circuit realization device of the embedded processor of the present invention

The second interface unit that Fig. 5 show bus protocol asynchronous logic module in the embodiment of the present invention exports and gives AMBA moulds Block signal combinational circuit schematic diagram

The first interface unit that Fig. 6 show bus protocol asynchronous logic module in the embodiment of the present invention is exported to embedded The signal combination circuit schematic diagram of processor

Embodiment

3- Fig. 6 below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.

It should be noted that the application scenarios of embedded processor vary, portability/compatibility of access interface is extremely Close important, and AMBA is almost de facto standard in embedded chip system, it is contemplated that different embedded being handled each Device access interface is converted to general AMBA interfaces, there is provided a kind of efficient portable/compatible implementation method.

Referring to Fig. 3, Fig. 3 show general AMBA ahb_bus bus timing schematic diagrames；As illustrated, with it is embedded The single reading of processor/single time domain service condition write out is different, address phase Address phase and data phase Data Phase is carried out in different time domains.Wherein, so that data width is 32 as an example, when HCLK is AMBA ahb_bus bus Clock signal, HADDR [63:0] it is access address bus, Control is bus control signal, bus control signal Control bags Include HTRANS and write request signal HWRITE.HWDATA[63:0] indicated for write-in data/address bus, HREADY for bus state, HRDATA[63:0] it is reading data/address bus.

In the bus protocol asynchronous loogical circuit realization device of the insertion processor of the present invention, its purport is by the insertion The access sequential logic of processor is converted to standard AMBA ahb_bus bus access agreements, i.e., the storage of embedded processor Interface is converted to AMBA ahb_bus bus access agreements by bus protocol asynchronous logic module (bridge).

In an embodiment of the present invention, the data bit width of the insertion processor can generally select the power side for 2, it is assumed that The data bit width of embedded processor is N, then, the data bit width M of standard AMBA ahb_bus buses can be N integral multiple, Or or embedded processor data bit width N be standard AMBA ahb_bus buses data bit width M integral multiple, Wherein, N, M are 2 power side.

In an embodiment of the present invention, N can selected from 2 power side a number, it is preferred that for example, N can be selected from 8, 16th, a data in 32,64 and 128.M can also selected from 2 power side a number, it is preferred that M can be selected from 8,16, 32nd, a data in 64 and 128.That is, M can be greater than, equal to or less than N.

It should be noted that in an embodiment of the present invention, if the data bit width N of embedded processor is more than standard AMBA Y times of data bit width M of ahb_bus buses, then, bus protocol asynchronous logic module divides Y transmission data, every time output Numerical value bit wide be equal to AMBA modules access address bus HRDATA [M-1:0] numerical value bit wide；Wherein, Y is more than or equal to 1 Positive integer.

If X times of the data bit width M of ahb_bus buses of the data bit width N less than standard AMBA of embedded processor, always The output numerical value bit wide of wire protocol asynchronous logic module is equal to the access address bus HRDATA [M-1 of AMBA modules:0] X points One of numerical value bit wide；That is the access address bus HRDATA [M-1 of AMBA modules:0] X secondary bus agreement asynchronous logic moulds are received The output numerical value of block；X is the positive integer more than 1.

For sake of convenience, the following examples are to be embedded in the data bit width N of processor as 32, standard AMBA ahb_ Bus buses bit wide is described exemplified by being 64, and the situation of other bit wides no longer repeats one by one.

Referring to Fig. 4, Fig. 4 show the electricity of the bus protocol asynchronous loogical circuit realization device of the embedded processor of the present invention Road block diagram.As illustrated, the device is included by embedded processor, bus protocol asynchronous logic module and AMBA modules.Clock is believed The input end of clock of the embedded processor of number CLK connections and bus protocol asynchronous logic module, bus clock HCLK connections bus are assisted Discuss the input end of clock of asynchronous logic module and AMBA modules.Wherein, when input clock Clk and bus clock HCLK is asynchronous Clock.

Embedded processor includes embedded processor output and reads request signal Read, write request signal Write, access ground Location Addr [31:2], write the effective BE [3 of section:0] and write-in data WData [31:The output end such as 0], in addition to pause wait mark Show Stall, read data RData [63:0] and byte effective RBE [7 is read:The input such as 0].

AMBA modules include control signal HTRANS [1:0], access address bus HADDR [63:0] data, are write HWRITE and write-in data/address bus HWDATA [63:The input such as 0], in addition to bus state sign HREADY and to read data total Line HRDATA [63:The output end such as 0].

Bus protocol asynchronous logic module include with the first interface unit of embedded processor interaction data, converting unit and With the second interface unit of AMBA module interaction datas.

Embedded processor output reads request signal Read, write request signal Write, access address Addr [31:2]、 Write the effective BE [3 of section:0] and write-in data WData [31:0] it is output to first interface unit, first interface unit will suspend etc. Stall to be indicated, read data RData [63:0] and byte effective RBE [7 is read:0] it is input to embedded processor.

Second interface unit is by control signal HTRANS [1:0], access address bus HADDR [63:0] data, are write HWRITE and write-in data/address bus HWDATA [63:0] the AMBA modules are input to；AMBA modules indicate bus state HREADY and reading data/address bus HRDATA [63:0] it is input to second interface unit.

In the technical scheme of above-mentioned hardware connection, clock signal clk and bus clock HCLK can come from external clock letter Number, can also internal clock signal.It is, for example, possible to use trigger realizes sequence circuit seq.

In an embodiment of the present invention, the first interface unit of bus protocol asynchronous logic module and second interface unit Output, all relies on the input of the first interface unit and second interface unit of bus protocol asynchronous logic module.Specifically, always The converting unit of wire protocol asynchronous logic module performs following operation：

The OPADD bus Addr [31 of embedded processor:2] the access address bus of the AMBA modules is expanded to HADDR[63:0], wherein, the access address bus HADDR [63:0] low two [1:0] it is correspondingly embedded in processor output BE[3:0] or keep BE [3:0] two are 0；

The reading request signal Read/ write request signals Write of embedded processor output is equivalent to institute's AMBA modules Write data HWRITE；The foundation so designed is that embedded processor can not possibly be simultaneously emitted by reading request signal Read/ write-ins Request signal Write is operated, thus can be opposite using the AMBA equivalent write request signal Write of HWRITE~ HWRITE correspondingly reads request signal Read operations.

Data WData [31 is write out in embedded processor output:0] it is equivalent to the write-in data/address bus for stating AMBA modules HWDATA[63:0]。

The input pause of embedded processor, which waits, indicates the output that Stall derives from bus protocol asynchronous logic module, temporarily Stop waiting sign Stall logic to indicate HREADY dependent on the bus state of the AMBA modules.

In this embodiment, X 2, i.e., ahb_bus bus of the data bit width 32 less than standard AMBA of embedded processor Twice of data bit width 64, the access address bus HRDATA [63 of AMBA modules:0] bus protocol asynchronous logic mould twice is received The output numerical value of block；The input RData [63 of embedded processor:0] output of bus protocol asynchronous logic module is derived from, it is counted HRDATA [63 of the value equal to AMBA:0] high/low two parts.

The effective RBE [7 of byte is read in the input of embedded processor:0] output of bus protocol asynchronous logic module is derived from, its Logic is write dependent on the output of the embedded processor and saves effective BE [3:0], and with reading data RData [31:0] have simultaneously Effect.

Residual signal between bus protocol asynchronous logic module and the ahb_bus buses of AMBA modules is fairly simple, control The output that signal HTARNS processed corresponds to embedded processor reads request signal Read/ write request signal Write and the section that writes Effective BE [3:0] while effective situation.

The first interface element output signal and second interface unit of bus protocol asynchronous logic module is set forth below The combinational circuit logic of output signal.

Referring to Fig. 5, the second interface unit that Fig. 5 show bus protocol asynchronous logic module in the embodiment of the present invention is defeated Go out and give AMBA module by signal combinational circuit schematic diagrames.As illustrated, Fig. 5 includes four combinational circuits, (combinational circuit is referred to comb Generation), HTRANS combinational circuits, HADDR combinational circuits, HWRITE combinational circuits and HWDATA combinational circuits.In addition, in the present invention Embodiment in, First Input First Output (First Input First Output, abbreviation FIFO) can also be used, it is embedding to reduce Enter the mutual wait between processor and the ahb_bus buses of AMBA modules.

Assuming that：The built-in variable of bus protocol asynchronous logic module is：

Valid=(| BE [3:0])&(Read|Write)

Export and be to the signal of AMBA module ahb_bus buses：

HTRANS={ valid, 1 ' b0 }

HADDR=Addr

HWRITE=valid＆Write＆~Read

HWDATA=WData

Referring to Fig. 6, the first interface unit that Fig. 6 show bus protocol asynchronous logic module in the embodiment of the present invention is defeated Go out the signal combination circuit schematic diagram to embeded processor.As illustrated, Fig. 6 include three combinational circuits (combinational circuit with Comb is referred to), RData combinational circuits, Stall combinational circuits and RBE combinational circuits.In addition, in an embodiment of the present invention, also First Input First Output (First Input First Output, abbreviation FIFO) can be used, with reduce embedded processor and Mutual wait between the ahb_bus buses of AMBA modules.

Assuming that：The built-in variable of bus protocol asynchronous logic module is：

Valid=(| BE [3:0])&(Read|Write)

Export and be to the signal of AMBA module ahb_bus buses：

RData=HREADYHRDATA:0

Stall=HREADY

RBE=HREADYBE:0

In summary, it is contemplated that AMBA buses are the mainstream standards of embedded system, insertion processor of the invention it is total The access sequential logic of the specific embedded processor of wire protocol asynchronous loogical circuit realization device is converted to standard AMBA ahb_bus Bus access agreement.It is mutual in the data bit width and the data bit width of the ahb_bus buses of AMBA modules for being embedded in processor bus In the case of multiple, the processor and system bus of cross clock domain can be not only handled, and more bit wides can be used Data/address bus, the more data of simultaneous transmission, improve bandwidth performance under identical clock frequency.

In addition, also it is emphasized that the bus protocol asynchronous loogical circuit realization device solution of the insertion processor of the present invention Determine the interface problem of specific embedded processor Uniform Access external equipment, can have been realized logical with less logic circuit resource With the purpose of access.

Above-described is only the preferred embodiments of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in In protection scope of the present invention.

Claims (2)

1. a kind of bus protocol asynchronous loogical circuit realization device of embedded processor, for by the access of the embedded processor Sequential logic is converted to standard AMBA ahb_bus bus access agreements；Wherein, the data bit width of the embedded processor is N, And the data bit width M of the ahb_bus buses of the standard AMBA is N integral multiple, or the data bit width N of the embedded processor For the data bit width M of the ahb_bus buses of standard AMBA integral multiple, wherein, N, M are 2 power side；Its feature exists In, including by embedded processor, bus protocol asynchronous logic module and AMBA modules；The clock signal clk connection is described embedding Enter processor and the input end of clock of the bus protocol asynchronous logic module, the bus clock HCLK connections bus association Discuss the input end of clock of asynchronous logic module and the AMBA modules；Wherein, the input clock Clk and bus clock HCLK are Asynchronous clock；

The bus protocol asynchronous logic module includes single with the first interface unit of the embedded processor interaction data, conversion Member and the second interface unit with the AMBA modules interaction data；The embedded processor output reading request signal Read, Write request signal Write, access address Addr [N-1:2], write the effective BE [3 of section:0] and write-in data WData [N-1:0] The first interface unit is output to, the first interface unit, which will suspend, to be waited sign Stall, reads data RData [N-1: 0] and byte effective RBE [3 is read:0] it is input to the embedded processor；The second interface unit is by control signal HTRANS [1:0], access address bus HADDR [M-1:0] data HWRITE and write-in data/address bus HWDATA [M-1, are write:0] input To the AMBA modules；The bus state is indicated HREADY and reads data/address bus HRDATA [M-1 by the AMBA modules: 0] it is input to the second interface unit；

The converting unit performs following operation：

The OPADD bus Addr [N-1 of the embedded processor:2] the access address bus of the AMBA modules is expanded to HADDR[M-1:0], wherein, the access address bus HADDR [M-1:0] low two [1:0] the corresponding embedded processor The BE [3 of output:0] or keep BE [3:0] two are 0；

The reading request signal Read/ write request signals Write of the embedded processor output is equivalent to the AMBA modules Write-in data HWRITE；

Data WData [N-1 are write out in the embedded processor output:0] it is equivalent to the write-in data/address bus of the AMBA modules HWDATA[M-1:0]；

The input pause of the embedded processor waits sign Stall from the defeated of the bus protocol asynchronous logic module Go out, the pause waits sign Stall logic dependent on the bus state sign HREADY of the AMBA modules；

Input RData [the N-1 of the embedded processor:0] output of the bus protocol asynchronous logic module is derived from, if Y times of the data bit width M of ahb_bus buses of the data bit width N of the embedded processor more than the standard AMBA, it is described total Wire protocol asynchronous logic module divides Y transmission data, and the numerical value bit wide exported every time is equal to the access address of the AMBA modules Bus HRDATA [M-1:0] numerical value bit wide；Wherein, Y is the positive integer more than or equal to 1；

If the data bit width M of ahb_bus buses of the data bit width N of the embedded processor less than standard AMBA X Times, the output numerical value bit wide of the bus protocol asynchronous logic module is equal to the access address bus HRDATA of the AMBA modules [M-1:0] the numerical value bit wide of X/mono-；The access address bus HRDATA [M-1 of i.e. described AMBA modules:0] X institute is received State the output numerical value of bus protocol asynchronous logic module；X is the positive integer more than 1；

The effective RBE [3 of byte is read in the input of the embedded processor:0] from the defeated of the bus protocol asynchronous logic module Go out, its logic is write dependent on the output of the embedded processor and saves effective BE [3:0], and with reading data RData [N-1:0] Effectively simultaneously；

The input RBE [3 of the embedded processor:0] output of the bus protocol asynchronous logic module, the bus are derived from The logic of agreement asynchronous logic module depends on the output BE [3 of the embedded processor:0], with RData [N-1:0] have simultaneously Effect；

The output that control signal HTARNS corresponds to the embedded processor reads request signal Read/ write request signals The Write and effective BE [3 of section that writes:0] while effective situation.

2. device according to claim 1, a data of the N in 8,16,32,64 and 128；The M is selected from 8th, a data in 16,32,64 and 128.