CN219916336U - LPC interface to AXI bus protocol bridge - Google Patents

Abstract

The utility model discloses an LPC interface to AXI bus protocol bridge, the protocol bridge is connected with a main device through the LPC interface, and is connected with an AXI slave device through the AXI bus interface; the protocol bridge comprises an encoding arbitration unit, an input buffer unit, an output buffer unit and a protocol conversion unit, wherein the encoding arbitration unit is connected with one path of main equipment and is used for LPC protocol decoding and bus arbitration; the input buffer unit is connected between the coding arbitration unit and the protocol conversion unit and is used for buffering operation commands and data; the output buffer unit is connected with the coding arbitration unit and the protocol conversion unit and is used for buffering the data returned by the protocol conversion unit to the main equipment; the protocol conversion unit is connected with the AXI bus. The utility model has the advantages that the master device accesses the high-speed slave device through the low-speed interface, so that a plurality of master devices can be interconnected through the AXI bus to establish a shared access channel.

Description

LPC interface to AXI bus protocol bridge

Technical Field

The utility model relates to the application fields of embedded computing, digital signal processing and the like, in particular to an LPC interface-to-AXI bus protocol bridge.

Background

The CPU/DSP processor usually adopts LPC interface as low-speed interface for starting and peripheral accessing, and in the design of high-performance computing module containing multiple processors, the shared access channel is required to be realized among the multiple processors by LPC interface.

LPC (Low Pin Count) is the Intel corporation 33MHz 4bit parallel bus protocol standard, maximum transfer rate 16MB/s. The LPC interface comprises 7 necessary signals and 6 optional signals, wherein the 7 necessary signals comprise a clock signal LPC_CLK, a reset signal LPC_RSTN, a read-write FRAME signal LPC_FRAME and 4bit data LPC_LAD [3:0].

The AXI bus interface (Advanced eXtensible Interface) is an important part in AMBA (Advanced Microcontroller Bus Architecture) 3.0.0 protocols proposed by ARM company, is an on-chip bus oriented to high performance, high bandwidth and low delay, is separated in address, data and control, supports unaligned data transmission, burst access, outtiming transmission and out-of-order access, and meets the requirements of high-performance transmission and complex system-on-chip design. The AMBA4.0 protocol upgrades its modifications to AXI4.0.

Disclosure of Invention

The utility model adopts generalized, standardized and modularized design thought aiming at the LPC bus and the AXI bus mentioned in the background art, abstracts and refines the design of a protocol conversion bridge based on FPGA hardware resources aiming at the application system requirement, and establishes a conversion bridge channel from the LPC bus to the AXI bus protocol, thereby realizing the read-write access of a plurality of processors to the external high-speed DDR memory of the FPGA and the shared memory space of the internal SRAM.

The utility model provides an LPC interface to AXI bus protocol bridge based on the logic design of FPGA, which realizes that a master device accesses a high-speed slave device by a low-speed interface, so that a plurality of master devices can be interconnected by AXI buses to establish a shared access channel.

The technical scheme adopted is as follows:

an LPC interface to AXI bus protocol bridge, the protocol bridge connects a path of master equipment through LPC interface, connect a path of AXI slave equipment through AXI bus interface at the same time; the protocol bridge comprises an encoding arbitration unit, an input buffer unit, an output buffer unit and a protocol conversion unit, wherein the encoding arbitration unit is connected with one path of main equipment and is used for LPC protocol decoding and bus arbitration; the input buffer unit is connected between the coding arbitration unit and the protocol conversion unit and is used for buffering operation commands and data; the output buffer unit is connected with the coding arbitration unit and the protocol conversion unit and is used for buffering the data returned by the protocol conversion unit to the main equipment; the protocol conversion unit is connected with the AXI bus and is used for the mutual conversion of asynchronous clock domain transmission protocols between the master device interface and the slave device interface.

Further preferably, the AXI bus interface is connected to an AXI bus switch, and the expansion bus interface is connected to multiple AXI slave devices.

Further preferably, the coding arbitration unit monitors read-write operation from the main equipment by using a main equipment interface channel associated clock, decodes operation commands and data, and stores the commands and the data into the input buffer unit; and judging the non-empty state of the output buffer unit, and controlling the read data to be released to the LPC bus in an arbitration mode when the slave equipment stores the returned data.

The protocol conversion unit is used for the transmission protocol mutual conversion between the master device interface and the slave device interface, and comprises a master device interface protocol command and data for controlling the read-out input buffer, converts the data into the read-write operation control time sequence of the AXI bus protocol by using the AXI bus clock, waits for latching the data returned from the slave device to the master device, and stores the data into the output buffer unit.

Further preferably, the input buffer unit and the output buffer unit each comprise FIFO first-in first-out logic modules.

Further preferably, the interface protocol used by the master device includes an LPC open kernel protocol, the data width is 8 bits, the address width is 32 bits, and the clock frequency is 33.33MHz.

Further preferably, the main device interface outputs a reset signal to provide synchronous reset of each functional unit of the protocol bridge.

Further preferably, the interface protocol used by the slave device includes an AXI bus open core protocol, the data width is 32 bits, the address width is 32 bits, and the bus clock is 100MHz.

Further preferably, the AXI slave device is a high-speed slave device, and the high-speed slave device comprises a double data rate synchronous dynamic memory DDR.

Compared with the prior art, the utility model has the beneficial effects that:

1. the protocol bridge establishes the bridge channel from the LPC interface to the AXI bus, the application system can exemplarily call the multi-path protocol bridge, each path of AXI bus can be connected with an AXI bus interconnection switch, a plurality of CPU/DSP processors can share and access a plurality of memories/peripherals (RAM/DDR/FLASH) on the AXI bus through the LPC interface by address addressing decoding mapping, and the design has better reusability and expansibility.

2. The protocol bridge of the utility model has the interface design conforming to the LPC interface and AXI bus protocol standard, and has good universality, compatibility and adaptability, and is beneficial to the fusion and integration of user systems.

3. The protocol bridge realizes the LPC interface to the AXI bus protocol bridge by using the on-board FPGA resource design, and does not increase the hardware resource cost additionally.

4. The protocol bridge is designed based on FPGA resources aiming at application requirements, and the bridge interface/function can be redefined by software, so that the product function performance can be expanded and upgraded conveniently.

5. The protocol bridge provides a general, standard and software solution for bridging data communication among different transmission interfaces/protocols, has strong practicability, and is stable and reliable in design through product test verification.

Drawings

Fig. 1 is a block diagram of an application system of the present embodiment.

Fig. 2 is a conversion flow chart of the protocol bridge in the present embodiment.

FIG. 3 is a diagram illustrating the LPC protocol Memory read/write timing supported by this embodiment.

Fig. 4 is an LPC protocol Start state definition.

Fig. 5 is an LPC protocol Cycle type state definition.

Fig. 6 is an AXI bus protocol transport channel supported by the present embodiment.

Fig. 7 is an AXI bus protocol master interface write timing supported by the present embodiment.

Fig. 8 is an AXI bus protocol master interface read timing supported by the present embodiment.

Detailed Description

The technical scheme of the present utility model is described in detail below, but the scope of the present utility model is not limited to the embodiments.

In order to make the contents of the present utility model more comprehensible, the present utility model is further described with reference to fig. 1 to 8 and the detailed description below.

The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

As shown in fig. 2, the protocol bridge conversion flow of the present embodiment is as follows:

the main equipment interface outputs an effective reset signal, so that after each unit of the protocol bridge is synchronously reset, the main equipment interface sets the reset signal to be high level, and the bridge starts to enter a working state. After sampling a working frame starting signal by a main equipment associated clock to be low level, latching an operation command and data, and releasing an input buffer write signal; judging that the input buffer is not empty, indicating that the main equipment initiates operation, releasing the input buffer reading signal to read and latch the buffer command and the data; judging whether the operation is a read operation or not, if the operation is a write operation, extracting the operation address and the data of the latch data, correspondingly releasing the operation address and the data to an AXI bus write transmission signal channel, ending the write operation of the main equipment, returning to judging whether an input buffer is not empty, and entering a subsequent operation conversion flow. If the operation is the read operation, the operation address and the data of the latch data are extracted and correspondingly released to an AXI bus read transmission signal channel, the slave device waits for returning the data to the AXI bus, latches the return data, releases the output buffer write signal to buffer the return data, judges that the output buffer is not empty, releases the output buffer read signal, reads out the output buffer data, arbitrates the interface bus of the main device, outputs the return data to the main device, ends the main device read operation, returns to judge whether the input buffer is not empty, and enters the subsequent operation conversion flow.

The embodiment is an LPC interface to AXI bus protocol bridge, the protocol bridge includes four functional units: the device comprises an encoding arbitration unit, an input buffer unit, an output buffer unit and a protocol conversion unit. The coding arbitration unit is used for LPC protocol decoding and bus arbitration, the input buffer FIFO unit stores LPC instructions/data, the output buffer FIFO unit stores data returned to the LPC master device, and the protocol conversion unit is used for the mutual conversion between the master device interface protocol and the slave device interface protocol of the asynchronous clock domain.

In this embodiment, the master device outputs a synchronous reset signal to the protocol bridge, and the reset signal is valid at a low level. When the reset signal is high level, the protocol bridge enters into working state.

The coding arbitration unit latches LPC read-write operation instructions, addresses and data by LPC_CLK (33.33 MHz) sampling, and 42bit data definition is sequentially from high to low: 2'b00 (read)/2' b01 (write), 8bit data, 32bit address, and store in the input buffer FIFO unit; and gives out signal control such as bus bidirectional state switching, long waiting, synchronization and the like of LPC interface read-write operation; the coding arbitration unit module monitors the output buffer FIFO unit to be non-empty, which indicates that the bus response state and the read data are stored in the output buffer FIFO unit, and generates FIFO read signals to read data for arbitration and release to the LPC bus.

The protocol conversion unit monitors that the input buffer FIFO unit is not empty, indicates that the master device initiates LPC read-write operation, releases the read signal of the input buffer FIFO, reads out the buffer command and data of the input LPC operation, converts the buffer command and the data into the AXI bus read-write operation control time sequence output by using an AXI bus clock of 100MHz, and stores the read-back data into the output buffer FIFO unit.

The LPC interface signal of the protocol bridge of the present embodiment includes: 1) The clock signal LPC_CLK, frequency 33.33MHz; 2) The reset signal LPC_RSTN is active low; 3) The read-write FRAME signal LPC_FRAME is active low; 4) 4bit data LPC_LAD [3:0]. The data width of the LPC interface reading or writing cycle is 8bit, and the address width is 32bit. The single read-write data width of the LPC interface is single byte (8 bit), the data width of the AXI bus interface is four bytes (32 bit), and the 8bit data of the LPC interface is decoded according to the low two bits of the access address and is latched to the corresponding byte in the four bytes.

In this embodiment, the input buffer unit parameter is configured to be 16x42 bits, and is used for buffering the input of the LPC operation instruction, the address and the data, where the 42bit data definition is sequentially from high to low: 2'b00 (read)/2' b01 (write), 8bit data, 32bit address. The input buffer FIFO cell parameters are configured as 16x10 bits, 10bit data defining the order from high to low: 2bit response status, 8bit data.

As shown in FIG. 3, a typical LPC protocol Memory read/write sequence, a typical LPC operation Cycle, is generally composed of Start, type of operation Cycle type, address ADDR, bus arbitration TAR, synchronization Sync, and DATA DATA. Fig. 4 and 5 give the LPC protocol status word definitions. The coding arbitration unit STARTs a Memory/IO read/write cycle with LPC_CLK sampling when LPC_FRAME is active low and the last clock LPC_LAD [3:0] enters the START state (4' b 0000). The next clock, LPC_LAD, inputs the Cycle type state, determining the type of read and write operations. The next 8 clocks, LPC_LAD, input the 32bit operation address. If the operation is writing operation, then 2 clocks are used, the LPC_LAD inputs 8bit operation data, and then the bus state switching and response state is entered; if the read operation is performed, the bus state switching is performed, data waiting is performed, and the data state is synchronously read. The coding arbitration unit samples and extracts the read-write, address and data of each LPC operation period, releases the write signal of the input buffer FIFO, and controls the input 42bit coding data to be written into the input buffer FIFO.

In this embodiment, the encoding arbitration unit monitors the output buffer FIFO non-empty state, controls the output buffer read signal to obtain the read-write response state (2 bit) and the read data (8 bit), arbitrates the LPC bus, and latches the read data to output the lpc_lad [3:0] signal.

In this embodiment, the protocol conversion unit monitors the non-empty state of the input buffer FIFO, controls the input buffer read signal to obtain the LPC read-write type, address and data, and generates the AXI protocol master interface read-write timing control by using the AXI bus clock of 100Mhz, and operates the AXI bus slave device. As shown in fig. 6, AXI bus interconnect traffic includes 5 transmission channels: a write address channel (AW), a write data channel (W), a write response channel (B), a read address channel (AR) and a read data channel (R). As shown in fig. 7-8, the present utility model provides AXI bus protocol master interface read and write operation timing, and each transmission channel uses an effective effect signal (VALID/READY) to control the synchronization handshake of the transmission address and data.

In this embodiment, when the AXI bus is in write operation, the protocol conversion unit writes the 8-bit operation data into the corresponding byte of m_axi_wdata [31:0] according to the lower two bits of the write address, and sets the byte latch signal m_axi_wstrb. And when the protocol conversion unit is in an AXI bus reading operation, extracting data of bytes corresponding to m_axi_rdata [31:0] according to the low two-bit decoding of the reading address, and writing the data into an output buffer FIFO.

The application system designs and instantiates more than one protocol bridge, the main device interfaces of the multi-path protocol bridge are correspondingly connected with a plurality of LPC main devices, the AXI bus main interfaces of the protocol bridge are correspondingly connected with multi-path slave interfaces of an AXI bus exchange switch, the multi-path AXI main interfaces are expanded through the AXI bus exchange switch, and the multi-path slave devices are connected. An AXI bus exchange switch in the application system is an AXI bus interconnection functional unit mapped by an FPGA internal address, and comprises a plurality of AXI bus slave interfaces and a plurality of AXI bus master interfaces, wherein the AXI bus slave interfaces are correspondingly connected with one or more AXI bus master interfaces; and the AXI bus master interface is correspondingly connected with one or more slave devices.

The multi-channel AXI bus main interface of the AXI bus exchange switch in the application system is at least connected with more than one peripheral controller, wherein one of the multi-channel AXI bus main interfaces is a high-speed slave interface.

The multi-master in the application system exchanges switch addressing mapping through a multipath protocol bridge and an AXI bus, and the access slave mode comprises single master and single slave (point-to-point), single master and multiple slave (point-to-multiple), multiple master and one slave (sharing), multiple master and multiple slave (mixing).

As shown in fig. 1, this embodiment provides an application system based on a protocol bridge, where the application system calls four protocol bridges, connects LPC interfaces of four processors (master devices), connects AXI bus switch, and enables each processor to operate one or more memories (SRAM/DDR) on the AXI bus and multiple slave devices through the LPC interfaces by addressing the mapping space, so as to implement access of the LPC low-speed interface to the AXI bus high-speed slave device (DDR), and supports multi-mode access such as point-to-point, sharing between the master devices and the slave devices through the AXI bus.

In this embodiment, based on the application requirement that the multi-chip processor establishes the shared data access channel through the LPC interface, the implementation scheme of abstracting the LPC interface to the AXI bus protocol bridge is abstracted by using the on-board FPGA hardware resource. The protocol bridge interface communication protocol is standardized, modularized and generalized; based on FPGA resource design, bridge interfaces and functions can be redefined by software, so that the product function performance can be expanded and upgraded conveniently.

The utility model is not related in part to the same as or can be practiced with the prior art.

As described above, although the present utility model has been shown and described with reference to certain preferred embodiments, it is not to be construed as limiting the utility model itself. Various changes in form and details may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims (9)

1. The bridge is characterized in that the bridge is connected with one path of master equipment through an LPC interface and one path of AXI slave equipment through an AXI bus interface;

the protocol bridge comprises an encoding arbitration unit, an input buffer unit, an output buffer unit and a protocol conversion unit, wherein the encoding arbitration unit is connected with one path of main equipment and is used for LPC protocol decoding and bus arbitration; the input buffer unit is connected between the coding arbitration unit and the protocol conversion unit and is used for buffering operation commands and data; the output buffer unit is connected with the coding arbitration unit and the protocol conversion unit and is used for buffering the data returned by the protocol conversion unit to the main equipment; the protocol conversion unit is connected with the AXI bus and is used for the mutual conversion of asynchronous clock domain transmission protocols between the master device interface and the slave device interface.

2. The LPC interface to AXI bus protocol bridge of claim 1, wherein an AXI bus interface is connected to an AXI bus switch and an expansion bus interface is connected to multiple AXI slave devices.

3. The LPC interface to AXI bus protocol bridge according to claim 1, wherein the coding arbitration unit listens for read and write operations from the master device with the master device interface channel clock, decodes operation commands and data, and stores the commands and data into the input buffer unit; and judging the non-empty state of the output buffer unit, and controlling the read data to be released to the LPC bus in an arbitration mode when the slave equipment stores the returned data.

4. The LPC interface to AXI bus protocol bridge according to claim 1, wherein the protocol conversion unit is used for the mutual conversion of transmission protocols between the master interface and the slave interface, and comprises a master interface protocol command and data for controlling the read-out input buffer, converting the command and the data into the read-write operation control time sequence of the AXI bus protocol by an AXI bus clock, waiting for latching the data returned from the slave to the master, and storing the data in the output buffer unit.

5. The LPC interface to AXI bus protocol bridge of claim 1, wherein said input buffer unit and said output buffer unit each include FIFO first-in-first-out logic.

6. The LPC interface to AXI bus protocol bridge of claim 1, wherein the interface protocol used by the host device includes an LPC open core protocol having a data width of 8 bits, an address width of 32 bits, and a clock frequency of 33.33MHz.

7. The LPC interface to AXI bus protocol bridge of claim 6, wherein a master device interface outputs a reset signal providing a synchronous reset of each functional unit of said protocol bridge.

8. The LPC interface to AXI bus protocol bridge of claim 1, wherein the interface protocol used by the slave device includes an AXI bus open core protocol, a data width of 32 bits, an address width of 32 bits, and a bus clock of 100MHz.

9. The LPC interface to AXI bus protocol bridge of claim 8, wherein said AXI slave is a high speed slave including a double data rate synchronous dynamic memory DDR.