CN103226531A - Dual-port peripheral configuration interface circuit - Google Patents
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Abstract
The invention belongs to the field of embedded systems, and discloses a dual-port peripheral configuration interface circuit. According to the interface circuit, only two IO interfaces are provided externally, one is an RCK (read clock) input port, and the other is an RDA (remote data access) data two-way port. A read-write data port, a read/write address signal port, and a read-write enable signal port are connected with a register set. The interface circuit comprises a clock counter, a read-write judging register, an address/data shifting register, a read data shifting register, an address register, a write enable signal generation register and a read enable signal generation register. The interface circuit disclosed by the invention has the advantages that the communication protocol and the circuit are simple, external ports are few, the communication speed changes with the rate change of an externally supplied RCK clock, an externally supplied system clock is not needed, and the like.
Description
Technical Field
The invention belongs to the field of embedded systems, and relates to a fully digital logic dual-port peripheral configuration interface circuit.
Background
Many kinds of common Peripheral configuration interface circuits are available, but the application of a single host to a single slave is often complicated, for example, a common spi (serial Peripheral interface) interface needs 4 ports such as CSN/SCK/MOSI/MISO, and MOSI/MISO does not work at the same time, which causes resource waste; while the commonly used I2C (Inter-Integrated Circuit) interface uses only two ports, SCL/SDA, only 3 protocols of 100Kps/400Kbps/3.4Mbps are good rate in terms of rate. And as specified by the protocol, the slave machines need to respond to ACK after the data transmission of the host machine is finished every time, and for a single host machine and a single slave machine system, the ACK is unnecessary, so that the waste of hardware resources is caused; while another common UART (Universal Asynchronous Receiver/Transmitter) interface has only two TxD/RxD at the port, both sides need to negotiate the rate first, and both sides need to have their own system clock to complete the normal communication process.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an interface circuit which has fewer external ports, simpler protocol, adjustable speed and no need of externally supplying a system clock when a single host and a single slave are applied.
The utility model provides a dual-port peripheral hardware configuration interface circuit which characterized in that, externally only have two IO interfaces: one is an RCK clock input port; the other is an RDA data bi-directional port. For exchanging information with external devices, typically connected to a configured initiating host. The connection ports with the register group are as follows: read and write data ports reg _ rdD [7:0] and reg _ wrD [7:0], read/write address signal ports reg _ addr [6:0], read and write enable signal ports reg _ rd and reg _ wr. The dual-port peripheral configuration interface circuit comprises: a clock counter p _ cnt [3:0], a read-write judgment register p _ r _ wn, an address/data shift register p _ d _ shift [7:0], a read data shift register n _ d _ shift [7:0], an address register p _ reg _ addr [6:0], a write enable signal generation register n _ reg _ wr and a read enable signal generation register n _ reg _ rd. Wherein,
and the clock counter p _ cnt [3:0] is used for counting the input clock RCK and outputting a time sequence pulse signal for controlling the working state of the whole circuit. The counter is a four-bit binary counter, the clock input end of the counter is connected with an RCK clock input port, and the counting output is respectively sent to selectors before p _ r _ wn, n _ reg _ rd, n _ reg _ wr and p _ reg _ addr [6:0 ]. The count value is automatically added with 1 at the rising edge of each clock and changes from 0 to 15 cycles, and one counting period is 16 RCK clocks, which corresponds to one reading/writing operation period.
And a read/write judgment register p _ r _ wn for judging the type (read or write) of the operation. The register is a one-bit register, the clock input end of the register is connected with the RCK clock input port, and the data output end of the register is respectively connected with selectors before the write enable signal generation register n _ reg _ wr and the read enable signal generator n _ reg _ rd. When the p _ cnt counts to 0, sampling data on the RDA, and judging the type of the operation: if the voltage level is high, the operation is read; if it is low, the operation is a write operation.
The read enable signal generation register n _ reg _ rd is used for generating a read enable signal. The register is a one-bit register, the clock input end of the register is connected with the clock input port of the clock RCK, the data input end of the register is connected with the output end of the front selector, and the data output end of the register is connected with the selector in front of the read data shift register n _ d _ shift and the read enable port reg _ rd. When p _ cnt [3:0] counts to 7, the falling edge of RCK triggers the register to generate a read enable signal of width 1 beat RCK.
The write enable signal generation register n _ reg _ wr generates a write enable signal. The register is a one-bit register, the clock input end of the register is connected with the clock input port of the clock RCK, the data input end of the register is connected with the output end of the front selector, and the data output end of the register is connected with the write enable port reg _ wr. When p _ cnt [3:0] counts to 15, the falling edge of RCK triggers the register to generate a write enable signal reg _ wr of width 1 beat RCK.
An address register p _ reg _ addr [6:0] for storing address signals for read/write data. The register is a 7-bit register with a clock input connected to the RCK clock input port and a data output connected directly to the address signal port reg _ addr [6:0] operating on the register bank. When p _ cnt [3:0] counts to 7, the lower 7 bits of the p _ d _ shift [7:0] register are stored in the address register, generating address signals for reading/writing data.
An address/data shift register p _ d _ shift [7:0] for converting serial address or write data signals into parallel data. The address/data shift register is an 8-bit shift register which is connected in series and is connected out, a shift control end is connected with an RCK clock input port, a serial input end is connected with an RDA, an 8-bit parallel output data line is connected with a write data port reg _ wrD [7:0], and a lower 7-bit data line p _ d _ shift [6:0] is also connected with a selector in front of the address register. On the rising edge of each clock cycle RCK, p _ d _ shift samples and shifts left the data on the RDA. When p _ cnt [3:0] counts to 7, the shift register outputs 7-bit address signals p _ d _ shift [6:0] in parallel. On the occurrence of the falling edge in beat 15, the 8-bit write data is output to write data port reg _ wrD [7:0 ].
A read data shift register n _ d _ shift [7:0] for converting the parallel read data into serial data. The register is an 8-bit shift register which is merged into and serially output, a shift control end is connected with an RCK clock input port, a parallel data input end is connected with a read data end reg _ rdD [7:0], an enabling control end is respectively connected with p _ r _ wn and n _ reg _ rd, and a serial output end is connected with RDA. When p _ r _ wn is low (the operation is write operation at this time), n _ d _ shift does not act; when p _ r _ wn is high (this operation is a read operation) and n _ reg _ rd is also high, the value of the corresponding register (least significant bit is 1) will be read from the read data port reg _ rdD [7:0 ]. Then, on each falling edge of RCK, n _ d _ shift performs a left shift operation until the 8-bit data is shifted out completely.
When the internal circuit works, no matter read operation or write operation is carried out, for the invention, data sampling is carried out on an RDA port at the rising edge of a signal of an RCK clock input port, and data change is carried out at the falling edge.
The RDA port is designed into bidirectional IO, so that the number of IO can be saved, and the two actions of reading and writing which are not performed simultaneously are completed on the same IO in a time sharing mode.
The invention has the beneficial effects that: the communication protocol is simple; the number of external ports is small, so that IO resources can be saved; the circuit is simple, and the layout area is small; the rate adjustment is convenient and changes along with the change of the rate of the externally supplied RCK clock, and the externally supplied system clock is not needed.
Drawings
FIG. 1 is a schematic diagram of an interface circuit of the present invention;
FIG. 2 is a standard timing diagram for a write operation of the present invention;
FIG. 3 is a standard timing diagram of a read operation according to the present invention;
FIG. 4 is a wiring diagram of an application example of the present invention.
Detailed Description
The dual-port peripheral configuration interface circuit described in the invention can use a unified dual port to communicate with the outside when connecting different peripherals, and the communication speed is completely determined by an external clock.
The following description of the present invention is provided in connection with the accompanying drawings.
FIG. 1 is an electrical schematic diagram of an interface circuit of the present invention, which is mainly composed of a clock counter p _ cnt [3:0], a read/write judgment register p _ r _ wn, an address/data shift register p _ d _ shift [7:0], a read data shift register n _ d _ shift [7:0], an address register p _ reg _ addr [6:0], a write enable signal generation register n _ reg _ wr, and a read enable signal generation register n _ reg _ rd.
After the design verification of the interface circuit is finished, the rtl (register Transfer level) code is synthesized to form a netlist, the layout is drawn corresponding to the process device of the shanghai warrior corporation, and finally the tape-out is successfully performed under the 350nm process of the shanghai warrior science and technology limited company.
Fig. 2 is an operation timing of the interface circuit at the time of write operation. The signal on the RDA is sampled temporarily at the rising edge of the 1 st clock, the operation type (read or write) is judged, and if the signal is low in the figure, the communication is write operation. The counter p _ cnt [3:0] performs a self-accumulation operation on the rising edge of each clock, incrementing by 1 each time. One write cycle is 16 beats of clock, corresponding to one count cycle of p _ cnt [3:0 ]. The address/data shift register p _ d _ shift [7:0] samples the RDA at the rising edge of each clock, performing a left shift operation. The signals of the 2 nd to 8 th beats of the RDA are address information, when the RDA is in the 8 th beat, the p _ d _ shift [6:0] outputs a 7-bit address (0 x 06) to an address register p _ reg _ addr [6:0], and the address register p _ reg _ addr [6:0] is kept unchanged in the communication process; the last 8 beats of the data are shifted left to form p _ d _ shift [6:0] (as the high 7 bits) and the signal on the RDA (as the lowest bit) at the falling edge of the 15 th beat of the data are combined to write data and sent to the write data port reg _ wrD [7:0] of the register group. Meanwhile, at the falling edge from the 15 th beat to the 16 th beat, a write enable signal reg _ wr lasting for 1 beat is output to a write data enable terminal of the register group, and data is stored in the register group. At this point, a write operation is completed.
Fig. 3 is an operation timing of the interface circuit at the time of the read operation. Likewise, one read cycle is also 16 beats. The 1 st clock rising edge samples the level signal on the RDA, judges the operation type (reading or writing), and if the operation type is high in the figure, the communication is read operation. And (3) reading to obtain address information in the RCK beat 2-8, and when the RCK beat 8 is carried out, sending a 7-bit address (0 x 06) output by p _ d _ shift [6:0] to an address register p _ d _ shift [6:0], and keeping the address unchanged in the communication process. Meanwhile, during the falling edge of beat 7 to the falling edge of beat 8, a read enable signal reg _ rd having a width of 1 beat is formed, and data (0 x 5A) in the register corresponding to the address (0 x 06) is read from the read data ports reg _ rdD [7:0] of the register group. This data is stored in shift register n _ d _ shift [7:0] at the falling edge of beat 8, and the register performs a shift left function (least significant bit filled with 1) at the falling edge of each RCK of beats 8-16. And the host releases the RDA when 8 beats are finished, so that the output of the RDA of the slave can be reflected to the host, and the function of an output port of the slave is completed. The output RDA changes following the most significant bit of n _ d _ shift at the falling edge of each clock until the transmission process of the data is completed. At the same time, the host acquires data by sampling the RDA at the rising edge of each clock. In this way, the transmission of the entire byte, i.e., the 8-bit data is completed from the falling edge of beat 8 to the falling edge of beat 16.
An example of the application of the present invention is given below. FIG. 4 is a block diagram of a register set connected to another analog chip to be configured. The communication port of the interface circuit is used as a slave in communication, the communication port is connected with an MCU (micro Control unit) through JTAG (Joint Test Action group) of a computer, an MSP430 chip is set as a host, and the read/write communication time sequence (one GPIO is used as a clock port RCK, and one GPIO is used as a bidirectional data port RDA) is simulated by using a GPIO (general Purpose Input output) of the MSP430 chip as the host, so that the configuration work between the external and simulated chip registers can be completed. The address space is 0-127, and the maximum is 128 bytes.
The final chip test result shows that the interface circuit can work well and can meet the read/write requirements of the register group to be configured.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention should be included in the present invention.
Claims (3)
1. The utility model provides a dual-port peripheral hardware configuration interface circuit which characterized in that, externally only have two IO interfaces: one is an RCK clock input port, and the other is an RDA data bidirectional port; the connection ports with the register group are as follows: read and write data ports reg _ rdD [7:0] and reg _ wrD [7:0], read/write address signal ports reg _ addr [6:0], read and write enable signal ports reg _ rd and reg _ wr; the dual-port peripheral configuration interface circuit comprises: a clock counter p _ cnt [3:0], a read-write judgment register p _ r _ wn, an address/data shift register p _ d _ shift [7:0], a read data shift register n _ d _ shift [7:0], an address register p _ reg _ addr [6:0], a write enable signal generation register n _ reg _ wr and a read enable signal generation register n _ reg _ rd; wherein,
the clock counter p _ cnt [3:0] is used for counting an input clock RCK and outputting a time sequence pulse signal for controlling the working state of the whole circuit; the clock counter is a four-bit binary counter, the clock input end of the clock counter is connected with an RCK clock input port, and counting output is respectively sent to a selector before p _ r _ wn, n _ reg _ rd, n _ reg _ wr and p _ reg _ addr [6:0 ]; automatically adding 1 to the count value of the rising edge of each clock, and circularly changing from 0 to 15, wherein one counting period is 16-beat RCK clock and corresponds to one read/write operation period;
the read-write judging register p _ r _ wn is used for judging the type (read or write) of operation; the read-write judging register is a one-bit register, the clock input end of the read-write judging register is connected with the RCK clock input port, and the data output end of the read-write judging register is respectively connected with selectors in front of the write enable signal generating register n _ reg _ wr and the read enable signal generator n _ reg _ rd; when p _ cnt [3:0] counts to 0, sampling data on an RDA port, and judging the type of the operation: if the voltage level is high, the operation is read; if the level is low, the operation is a write operation;
the read enable signal generation register n _ reg _ rd is used for generating a read enable signal; the read enable signal generation register is a one-bit register, a clock input end of the read enable signal generation register is connected with an RCK clock input port, a data input end of the read enable signal generation register is connected with the output end of a front selector, and a data output end of the read enable signal generation register is connected with a front selector of the read data shift register n _ d _ shift and a read enable port reg _ rd; when p _ cnt [3:0] counts to 7, the falling edge of RCK triggers the register to generate a read enable signal with the width of 1 beat RCK clock;
the write enable signal generation register n _ reg _ wr is used for generating a write enable signal; the write enable signal generating register is a one-bit register, the clock input end of the write enable signal generating register is connected with the RCK clock input port, the data input end of the write enable signal generating register is connected with the output end of the front selector, and the data output end of the write enable signal generating register is connected with the write enable port reg _ wr; when p _ cnt [3:0] counts to 15, the falling edge of RCK triggers the register to generate a write enable signal with the width of 1 beat RCK clock;
the address register p _ reg _ addr [6:0] is used for storing address signals of read/write data; the address register is a 7-bit register, the clock input end of the address register is connected with the RCK clock input port, and the data output end of the address register is connected with an address signal port reg _ addr [6:0 ]; when p _ cnt [3:0] counts to 7, storing the low-order 7-bit data of the address/data shift register p _ d _ shift [7:0] into the address register to generate an address signal for reading/writing data;
the address/data shift register p _ d _ shift [7:0] is used for converting serial address or write data signals into parallel data; the address/data shift register is an 8-bit shift register which is connected in series-parallel, a shift control end is connected with an RCK clock input port, a serial input end is connected with an RDA, an 8-bit parallel output data line is connected with a write data port reg _ wrD [7:0], and a lower 7-bit data line p _ d _ shift [6:0] is also connected with a selector in front of the address register; at the rising edge of each clock cycle RCK, sampling and left shifting data on the RDA by p _ d _ shift; when p _ cnt [3:0] counts to 7, the address/data shift register outputs 7-bit address signals p _ d _ shift [6:0] in parallel; when falling edge of beat 15 occurs, 8 bits of write data are output to write data port reg _ wrD [7:0 ];
a read data shift register n _ d _ shift [7:0] for converting parallel read data into serial data; the register is an 8-bit shift register which is merged into and serially output, a shift control end is connected with an RCK clock input port, a parallel data input end is connected with a read data end reg _ rdD [7:0], an enabling control end is respectively connected with p _ r _ wn and n _ reg _ rd, and a serial output end is connected with RDA; when p _ r _ wn is low (the operation is write operation at this time), n _ d _ shift does not act; when p _ r _ wn is high (the operation is a read operation) and n _ reg _ rd is also high, reading the value of the corresponding register from a read data port reg _ rdD [7:0 ]; thereafter, on each falling edge of RCK, n _ d _ shift performs a left shift operation until the 8-bit data is shifted out completely.
2. The dual port peripheral configuration interface circuit of claim 1, wherein a read operation or a write operation samples data from the RDA port on a rising edge of the RCK clock input port signal and data changes on a falling edge.
3. The dual port peripheral configuration interface circuit of claim 1, wherein the communication rate adjustment is facilitated, varies with externally supplied RCK clock rates, and does not require an externally supplied system clock.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108446243A (en) * | 2018-03-20 | 2018-08-24 | 上海奉天电子股份有限公司 | A kind of two-way communication and system based on Serial Peripheral Interface (SPI) |
| CN108681513A (en) * | 2018-07-19 | 2018-10-19 | 上海艾为电子技术股份有限公司 | I2C is from address generating device and chip |
| CN111385250A (en) * | 2018-12-28 | 2020-07-07 | 浙江宇视科技有限公司 | Safe access method and system for equipment port |
| CN112114875A (en) * | 2020-08-27 | 2020-12-22 | 中国科学院计算技术研究所 | Superconducting parallel register file device |
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| US20110258506A1 (en) * | 2004-12-10 | 2011-10-20 | Texas Instruments Incorporated | Reduced signaling interface method & apparatus |
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| US20110258506A1 (en) * | 2004-12-10 | 2011-10-20 | Texas Instruments Incorporated | Reduced signaling interface method & apparatus |
| CN1928878A (en) * | 2006-08-17 | 2007-03-14 | 电子科技大学 | Software and hardware synergism communication method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108446243A (en) * | 2018-03-20 | 2018-08-24 | 上海奉天电子股份有限公司 | A kind of two-way communication and system based on Serial Peripheral Interface (SPI) |
| CN108446243B (en) * | 2018-03-20 | 2021-11-26 | 上海奉天电子股份有限公司 | Bidirectional communication method and system based on serial peripheral interface |
| CN108681513A (en) * | 2018-07-19 | 2018-10-19 | 上海艾为电子技术股份有限公司 | I2C is from address generating device and chip |
| CN108681513B (en) * | 2018-07-19 | 2023-09-19 | 上海艾为电子技术股份有限公司 | I2C slave address generating device and chip |
| CN111385250A (en) * | 2018-12-28 | 2020-07-07 | 浙江宇视科技有限公司 | Safe access method and system for equipment port |
| CN111385250B (en) * | 2018-12-28 | 2022-07-19 | 浙江宇视科技有限公司 | Safe access method and system for equipment port |
| CN112114875A (en) * | 2020-08-27 | 2020-12-22 | 中国科学院计算技术研究所 | Superconducting parallel register file device |
| CN112114875B (en) * | 2020-08-27 | 2023-06-02 | 中国科学院计算技术研究所 | Superconducting parallel register file device |
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