CN108681513A - I2C is from address generating device and chip - Google Patents
I2C is from address generating device and chip Download PDFInfo
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- CN108681513A CN108681513A CN201810796957.XA CN201810796957A CN108681513A CN 108681513 A CN108681513 A CN 108681513A CN 201810796957 A CN201810796957 A CN 201810796957A CN 108681513 A CN108681513 A CN 108681513A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The embodiment of the present invention provides a kind of I2C from address generating device and chip.The I2C includes input terminal, clock end, data terminal, rising edge shift register, failing edge shift register and dynamic address generation unit from address generating device, and input terminal is selectively connect with clock end, data terminal, ground terminal or power end；The clock signal that rising edge shift register is inputted according to clock end carries out shift LD processing to the data that input terminal inputs and exports to the first registered data；The clock signal that failing edge shift register is inputted according to clock end carries out shift LD processing to the data that input terminal inputs and exports to the second registered data；Dynamic address generation unit determines the connecting object of input terminal according to the first registered data and the second registered data, and is generated from address according to the corresponding pattern decoding of connecting object.The I2C can solve the problems, such as input pin deficiency from address generating device.
Description
Technical field
The present embodiments relate to technical field of electricity more particularly to a kind of I2C from address generating device and chip.
Background technology
Input buffer is widely used in audio-frequency power amplifier, turns as indispensable basic module in integrated circuit
In parallel operation, radio frequency, sensor and power management chip.As shown in Figure 1, I2C address choices input buffer in the prior art,
When incoming level is higher than threshold voltage, output logic level becomes high from low；When incoming level is less than threshold voltage, output
Logic level becomes low from height；The input buffer can only export two kinds of Different Logic states.
But as IC complexity increases, the input pin number needed sharply increases, but with manufacturing process and
Encapsulation advanced optimizes so that chip area reduces, and for the encapsulation such as WLCSP, the total number of pins provided is instead
It is reducing so that the number of pin for the chip produced is insufficient, input pin number deficiency.
For example audio frequency power amplifier chip needs that a variety of different I2C register address are arranged, to realize the applied field of multichannel
Scape.And since pin resource is at full stretch, there are not distributing multiple pins as input pin, causes existing sound
Frequency power amplifier chips cannot satisfy the use demand.
Invention content
It generates and fills from address in view of this, one of the technical issues of embodiment of the present invention is solved is to provide a kind of I2C
It sets and chip, to overcome the problems, such as the input pin lazy weight of prior art chips.
The embodiment of the present invention provides a kind of I2C from address generating device comprising input terminal, clock end, data terminal, rising
Along shift register, failing edge shift register and dynamic address generation unit, input terminal selectively with clock end, data
End, ground terminal or power end connection；Rising edge shift register inputs input terminal according to the clock signal that clock end inputs
Data carry out shift LD processing and export to the first registered data；The clock that failing edge shift register is inputted according to clock end
Signal carries out shift LD processing to the data that input terminal inputs and exports to the second registered data；Dynamic address generation unit root
The connecting object of input terminal is determined according to the first registered data and the second registered data, and is decoded according to the corresponding pattern of connecting object
It generates from address.
Optionally, pre-stored data corresponding with the decoding of each pattern, each pre-stored data are preset in dynamic address generation unit
It is corresponding with a connecting object.
Optionally, pre-stored data includes the first data and/or the second data.
Optionally, dynamic address generation unit determines matched first data according to the first registered data, and/or, according to
Second registered data determines matched second data, with according to matched first data and/or the determination pair of matched second data
The connecting object answered.
Optionally, there is rising edge shift register the first clock end, rising edge shift register to pass through the first clock end
It is connect with clock end, and incoming clock signal；Failing edge shift register has second clock end, failing edge shift register logical
It crosses second clock end to connect with clock end, and phase inverter is provided between clock end and second clock end, keep second clock end defeated
Enter the inversion signal of clock signal.
Optionally, I2C further includes bit counters from address generating device, and bit counters are connect with clock end, and to from
The high level for the clock signal that clock end obtains is counted.
Optionally, I2C further includes controller from address generating device, and controller is connect with bit counters, and is counted in bit
When the count value of number device reaches predetermined value, control dynamic address generation unit is true according to the first registered data and the second registered data
Determine the connecting object of input terminal.
Optionally, I2C further includes selector from address generating device, and the control terminal of selector passes through the first amplifier ground
Or connect power supply, the first input end of selector is connect by the second amplifier with input terminal, the second input terminal of selector with it is dynamic
State scalar/vector connects, and when control terminal is high level, selector is according to the input value output state code of input terminal；Work as control
When end processed is low level, selector decodes output state code according to the output of dynamic address generation unit.
Optionally, I2C is generated according to conditional code and preset supplemental code from address from address generating device.
According to another aspect of the present invention, a kind of chip is provided, chip includes above-mentioned I2C from address generating device.
By above technical scheme as it can be seen that the I2C of the embodiment of the present invention passes through selectivity from the input terminal of address generating device
Ground is connect with one in clock end, data terminal, ground terminal and power end, to make an input terminal that four kinds of differences may be implemented
Connection type, to enable input terminal have there are four types of data input.Rising edge shift register and failing edge shift LD
Device is used to carry out shift LD to the data that input terminal inputs according to clock signal, and exports to the first registered data and second and post
Deposit data.Since input terminal can be connected from different connecting objects, and then there can be different input datas, so using rising
Along shift register and failing edge shift register the data of input are carried out with shift LD processing after can export different the
One registered data and the second registered data.Dynamic address generation unit is used for true according to the first registered data and the second registered data
Determine the connecting object of input terminal, and then is generated from address, with this according to the determining corresponding pattern decoding of different connecting objects
Four kinds of different purposes from address are generated realize using input terminal solve that existing chip input pin is insufficient to ask
Topic.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments described in inventive embodiments can also obtain according to these attached drawings for those of ordinary skill in the art
Obtain other attached drawings.
Fig. 1 is the I2C of the embodiment of the present invention from the structural schematic diagram of address generating device；
Fig. 2 be the embodiment of the present invention I2C from the input end grounding of address generating device when sequence diagram；
Fig. 3 is the sequence diagram when I2C of the embodiment of the present invention terminates clock end from the input of address generating device；
Fig. 4 be the embodiment of the present invention I2C from the input terminal data terminal of address generating device when sequence diagram；
Fig. 5 be the embodiment of the present invention I2C from address generating device input termination power when sequence diagram.
Reference sign：
10, rising edge shift register；20, failing edge shift register；30, dynamic address generation unit；40, bit is counted
Number device；50, the first amplifier；60, the second amplifier；70, selector；80, data shift register.
Specific implementation mode
Certainly, implementing any technical solution of the embodiment of the present invention must be not necessarily required to reach simultaneously above all excellent
Point.
In order to make those skilled in the art more fully understand the technical solution in the embodiment of the present invention, below in conjunction with the present invention
Attached drawing in embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described reality
It is a part of the embodiment of the embodiment of the present invention to apply example only, instead of all the embodiments.Based on the implementation in the embodiment of the present invention
Example, the every other embodiment that those of ordinary skill in the art are obtained should all belong to the range of protection of the embodiment of the present invention.
Embodiment specific implementation is further illustrated the present invention with reference to attached drawing of the embodiment of the present invention.
As shown in Figs. 1-5, according to an embodiment of the invention, I2C from address generating device include input terminal (AD_ in Fig. 1
PIN), clock end (Sclk in Fig. 1), data terminal (SDA in Fig. 1), rising edge shift register 10, failing edge shift register 20
With dynamic address generation unit 30, input terminal is selectively connect with clock end, data terminal, ground terminal or power end；Rising edge
The clock signal that shift register 10 is inputted according to clock end carries out shift LD processing to the data that input terminal inputs and exports
To the first registered data；The data that the clock signal that failing edge shift register 20 is inputted according to clock end inputs input terminal into
Row shift LD is handled and is exported to the second registered data；Dynamic address generation unit 30 is posted according to the first registered data and second
Deposit data determines the connecting object of input terminal, and is generated from address according to the corresponding pattern decoding of connecting object.
The I2C (Inter-Integrated Circuit) from the input terminal of address generating device by selectively with when
A connection in Zhong Duan, data terminal, ground terminal and power end, to make an input terminal that four kinds of different connections may be implemented
Mode, to enable input terminal to have, there are four types of data to input.Rising edge shift register 10 and failing edge shift register 20
For carrying out shift LD to the data that input terminal inputs according to clock signal, and exports to the first registered data and second and deposit
Data.Since input terminal can be connected from different connecting objects, and then there can be different input datas, so using edge is risen
Shift register 10 and failing edge shift register 20 are different to that can be exported after the data progress shift LD processing of input
First registered data and the second registered data.Dynamic address generation unit 30 is used for according to the first registered data and the second deposit number
It is generated from address according to the connecting object for determining input terminal, and then according to the determining corresponding pattern decoding of different connecting objects,
Four kinds of different purposes from address are generated realize using an input terminal it is insufficient to solve existing chip input pin with this
The problem of.
In the present embodiment, pre-stored data corresponding with the decoding of each pattern is preset in dynamic address generation unit 30, respectively
Pre-stored data is corresponding with a connecting object.Pre-stored data is data corresponding from different connecting objects.According to connection pair
The difference of elephant may include the first data and/or the second data in pre-stored data.
For example, when connecting object is ground, input end grounding, the first data that pre-stored data includes can be rising edge
Shift register 10 carries out shift LD treated data to the data when data of input are ground connection.Second data can be
Failing edge shift register 20 carries out shift LD treated data to the data when data of input are ground connection.Specifically such as：
First data are " 6 ' h00 ", the second data are " 6 ' h00 ".
When connecting object is clock end, input termination clock end, on the first data that pre-stored data includes can be
Rise along shift register 10 to the data of input are clock signal when data carry out shift LD treated data.Second number
According to can be failing edge shift register 20 to the data of input are clock signal when data carry out shift LD treated
Data.Specifically such as：First data are " 6 ' h00 ", the second data are " 6 ' h3f ".
When connecting object is data terminal, input termination data terminal can only include the first data or the in pre-stored data
Two data, it is of course also possible to all include.To include the first data instance, the first data can be when the data of input are data
When the data at end, rising edge shift register 10 carries out it shift LD treated data.Specifically such as：First data are
“6’h1b”。
When connecting object is power supply, termination power is inputted, the first data in pre-stored data can be the number when input
When according to data to connect power supply, rising edge shift register 10 carries out it shift LD treated data.Second data can
To be when the data of input are the data for connecing power supply, failing edge shift register 20 carries out it shift LD treated number
According to.Specifically such as：First data are " 6 ' h3f ", the second data are " 6 ' h3f ".
Different pattern decoding can be set for different connecting objects.For example, corresponding mould when connecting object is ground
Formula decoding can be " 00 "；The decoding of corresponding pattern can be " 01 " when connecting object is clock end；Connecting object is data terminal
When the decoding of corresponding pattern can be " 10 "；The decoding of corresponding pattern can be " 11 " when connecting object is power supply.
Certainly, in other embodiments, the corresponding pattern decoding of connecting object can be other decodings.Such as, connecting object
For ground when the decoding of corresponding pattern can be " 11 ".
When dynamic address generation unit 30 determines the connecting object of input terminal, dynamic address generation unit 30 can be according to the
One registered data determines the first data matching in pre-stored data.And/or it is determined according to the second registered data matching
The second data, to determine corresponding connecting object according to matched first data and/or matched second data.
For example, as shown in Fig. 2, when input end grounding, in the input data such as Fig. 2 of input terminal shown in AD_IN=GND.
The rising edge of each clock signal, rising edge shift register 10 all can once move the data obtained from input terminal AD
Position, in the clock tic for carrying out match, the first registered data that rising edge shift register 10 exports is " 6 ' h00 ".When each
The failing edge of clock signal, failing edge shift register 20 all can once shift the data obtained from input terminal AD, into
The clock tic of row match, the second registered data that failing edge shift register 20 exports are " 6 ' h00 ".Dynamic address generates single
After member 30 obtains first registered data and the second registered data, by it compared with preset each pre-stored data, and determine with
Matched pre-stored data, and then determine the decoding of corresponding pattern.
It should be noted that the clock tic of the present embodiment refers to a cycle of clock signal, i.e., it is shown in Fig. 2, when
One high level of clock signal and a low level are a clock cycle.
In the present embodiment, rising edge shift register 10 includes multiple d type flip flops.Certainly, in other embodiments, on
It rises and can be realized by other structures along shift register 10.
As shown in Figure 1, rising edge shift register 10 has the first clock end, for passing through first clock end and I2C
It is connected from the clock end (Sclk) of address generating device, and incoming clock signal, with according to the clock signal, in clock signal
Rising edge shifts the data of input by d type flip flop.The ends D of first d type flip flop of rising edge shift register 10
For being connect with input terminal, to obtain the data of input.The latter d type flip flop of the rising edge shift register 10 touches previous D
The data for sending out device output carry out shift LD processing.
Similarly, failing edge shift register 20 can also include multiple d type flip flops.Certainly, in other embodiments, under
Drop can be realized along shift register 20 by other structures.
Failing edge shift register 20 have second clock end, failing edge shift register 20 by second clock end and when
Clock end connects, to obtain clock signal, and according to the clock signal, clock signal failing edge by d type flip flop to input
Data shifted.The ends D of first d type flip flop of failing edge shift register 20 with input terminal for connecting, to obtain
The data of input.The latter d type flip flop of the failing edge shift register 20 carries out displacement to the data that previous d type flip flop exports and posts
Deposit processing.
In the present embodiment, it is provided with phase inverter between clock end and second clock end, makes second clock end input clock
The inversion signal of signal, the failing edge shift register 20 allow in this way is identical with the structure of rising edge shift register 10,
But the two may be implemented rising edge shift register 10 and be carried out at shift LD to the data of input in the rising edge of clock signal
Reason is believed so realizing it in clock simultaneously as the acquisition of failing edge shift register 20 is the inversion signal of clock signal
Number failing edge shift LD processing is carried out to the data of input.
Optionally, I2C further includes bit counters 40 from address generating device, and bit counters 40 are connect with clock end, and
The high level of clock signal to being obtained from clock end counts, to export count value ([3 bitcnt shown in Fig. 1:
0]).After the count value of bit counters 40 is stop value, the count value of bit counters is removed, since initial value again
It counts.Initial value can be 0 or 1 etc., be set as needed.For example, when initial value is 0, when the first high electricity of clock signal
When flat arrival, the count value of bit counters 40 is 1, and when second high level arrives, the count value of bit counters 40 adds 1 again,
And so on, until after the count value of bit counters 40 reaches stop value, its count value is purged, and from initial value
Start to count again.
In the present embodiment, I2C further includes controller from address generating device, and controller is connect with bit counters 40, and
When the count value of bit counters 40 reaches predetermined value, control dynamic address generation unit 30 is according to the first registered data and the
Two registered datas determine the connecting object of input terminal.
For example, as shown in Fig. 2, when the count value of bit counters 40 is equal to 7, controller controls dynamic address and generates list
The second of the first registered data and failing edge shift register 20 output that member 30 is exported according to rising edge shift register 10 is posted
Deposit data determines the current connecting object of input terminal, and exports corresponding pattern decoding.
In the present embodiment, in order to promote robustness, I2C from address generating device further include selector, the control of selector
End processed is grounded or is connect power supply by the first amplifier 50, and the first input end of selector is connected by the second amplifier 60 with input terminal
It connects, the second input terminal of selector is connect with dynamic address generation unit 30, and when control terminal is high level, selector is according to defeated
Enter the input value output state code at end；When control terminal is low level, selector is according to the output of dynamic address generation unit 30
Decode output state code.
For example, in use, if there is a situation where, dynamic address is unstable under use occasion, in order to adapt to this feelings
Condition is formed by selector 70, the first amplifier 50 and the second amplifier 60 and is bypassed, and 2 stable dynamic address are realized with this
Output.
, can be by making the first amplifier 50 connect power supply when use environment is unstable, selector 70 is operated in control terminal
Output for the state of high level, selector 70 is exported according to the data of input terminal.For example, the data of input terminal pass through
It is input in selector 70 after the amplification of two amplifiers 60, selector 70 is exported according to the data of the input terminal.
When the dynamic address of use environment is relatively stable, it is low level state, choosing that selector 70, which is operated in control terminal,
The pattern decoding that the output of device 70 is exported according to dynamic address generation unit 30 is selected to be exported.
Optionally, I2C is generated according to conditional code and preset supplemental code from address from address generating device.
Optionally, in the present embodiment, I2C further includes data shift register 80 from address generating device, and data shift
Register 80 with data terminal for connecting, and the data to being obtained from data terminal carry out shift LD processing, generates shifted data
(shi[6:0])。
When generation is consistent with the data that data shift register 80 exports from address, then the slave that is directed toward from address
(slave) it is responded, it is on the contrary then be not responding to.
The each output signal for connecting different connecting objects to input terminal below illustrates：
As shown in Fig. 2, when input end grounding, in the data waveform such as Fig. 2 of input terminal input shown in AD_IN=GND.When
In clock signal such as Fig. 2 shown in SCL.In the data-signal of input such as Fig. 2 shown in SDA.In the count value such as Fig. 2 of Bit counters 40
bitcnt[3：0] shown in.Shi_pos [5 in first registered data such as Fig. 2:0].Shi_neg [5 in second registered data such as Fig. 2:
0] shown in.
When the first amplifier 50 is grounded, the control terminal of selector 70 is low level, the output shape of the output of selector 70
State code dev_addr_in [1：0] pattern exported with dynamic address generation unit 30 decodes dev_addr2 [1:0] identical, at this time
Pattern decodes dev_addr2 [1:0] it is " 00 ", output state code dev_addr_in [1：0] also it is " 00 ".Output state code with
Preset supplemental code is formed from address dev_addr [6:0], in the present embodiment, 5 ' b01101 of supplemental code, the slave ground of generation
Location dev_addr [6:0] it is 7 ' b0001101, is converted to 16 into being made as 0x34.
As shown in figure 3, when input end grounding clock end, AD_IN=SCL in the data waveform such as Fig. 3 of input terminal input
It is shown.In clock signal such as Fig. 3 shown in SCL.In the data-signal of input such as Fig. 3 shown in SDA.The count value of Bit counters 40
Such as bitcnt [3 in Fig. 3：0] shown in.Shi_pos [5 in first registered data such as Fig. 3:0].In second registered data such as Fig. 3
shi_neg[5:0] shown in.
When the first amplifier 50 is grounded, the control terminal of selector 70 is low level, the output shape of the output of selector 70
State code dev_addr_in [1：0] pattern exported with dynamic address generation unit 30 decodes dev_addr2 [1:0] identical, at this time
Pattern decodes dev_addr2 [1:0] it is " 01 ", output state code dev_addr_in [1：0] also it is " 01 ".Output state code with
Preset supplemental code is formed from address dev_addr [6:0], in the present embodiment, 5 ' b01101 of supplemental code, the slave ground of generation
Location dev_addr [6:0] it is 7 ' b0101101, is converted to 16 into being made as 0x35.
As shown in figure 4, when input terminates data terminal, AD_IN=SDA institutes in the data waveform such as Fig. 4 of input terminal input
Show.In clock signal such as Fig. 4 shown in SCL.In the data-signal of input such as Fig. 4 shown in SDA.The count value of Bit counters 40 is such as
[3 bitcnt in Fig. 4：0] shown in.Shi_pos [5 in first registered data such as Fig. 4:0].Shi_ in second registered data such as Fig. 4
neg[5:0] shown in.
When the first amplifier 50 is grounded, the control terminal of selector 70 is low level, the output shape of the output of selector 70
State code dev_addr_in [1：0] pattern exported with dynamic address generation unit 30 decodes dev_addr2 [1:0] identical, at this time
Pattern decodes dev_addr2 [1:0] it is " 10 ", output state code dev_addr_in [1：0] also it is " 10 ".Output state code with
Preset supplemental code is formed from address dev_addr [6:0], in the present embodiment, 5 ' b01101 of supplemental code, the slave ground of generation
Location dev_addr [6:0] it is 7 ' b1001101, is converted to 16 into being made as 0x36.
As shown in figure 5, when input terminates power end, AD_IN=VDD institutes in the data waveform such as Fig. 5 of input terminal input
Show.In clock signal such as Fig. 5 shown in SCL.In the data-signal of input such as Fig. 5 shown in SDA.The count value of Bit counters 40 is such as
[3 bitcnt in Fig. 5：0] shown in.Shi_pos [5 in first registered data such as Fig. 5:0].Shi_ in second registered data such as Fig. 5
neg[5:0] shown in.
When the first amplifier 50 is grounded, the control terminal of selector 70 is low level, the output shape of the output of selector 70
State code dev_addr_in [1：0] pattern exported with dynamic address generation unit 30 decodes dev_addr2 [1:0] identical, at this time
Pattern decodes dev_addr2 [1:0] it is " 11 ", output state code dev_addr_in [1：0] also it is " 11 ".Output state code with
Preset supplemental code is formed from address dev_addr [6:0], in the present embodiment, 5 ' b01101 of supplemental code, the slave ground of generation
Location dev_addr [6:0] it is 7 ' b1101101, is converted to 16 into being made as 0x37.
It should be noted that supplemental code can determine as needed, however it is not limited to the value enumerated in the present embodiment.
If the first amplifier 50 is connect with power supply, the control terminal of selector 70 is in high level, and connector 70 is defeated at this time
Do well yard dev_addr_in [1：0] determined according to input terminal, for example, input terminal be low level when, output state code dev_
addr_in[1：0] it is " 00 ", conversely, when input terminal is low level, output state code dev_addr_in [1：0] it is " 11 ", this
Sample can ensure I2C can guarantee in the case where address is unstable to carry out from address generating device 2 stable stable states from
Address exports, to the robustness of lifting device.
According to another aspect of the present invention, a kind of chip is provided, chip includes above-mentioned I2C from address generating device.
The I2C of the chip from address generating device can by an input terminal selectively with ground terminal, power end, when
Clock end or data terminal connection, it is different from address to generate four kinds, to solve the problems, such as input terminal deficiency.
The I2C terminates the different existing pin of chip exterior, dynamic generation four from address generating device according to single input
Kind of I2C from address, the I2C for solving single-chip in the prior art needs to need two input pins when four addresses
Problem.Further, since rising edge, the displacement of shift register of failing edge, comparative approach has been used to generate four kinds of addresses, simultaneously
And there is bypass to design, it is ensured that chip can be in the work under four stable addresses or double address pattern.
It is designed by bypassing, increases the robustness of address, once in chip operation in more adverse circumstances, four addresses of dynamic
Comparison have unstable situation and occur, more simple and quick can make double address scheme into, this design can bypass all shiftings
The four address logical construction (such as rising edge shift register, failing edge shift register) of generation is latched and compared in position, leads to
The ground connection of AD_PIN is crossed, power supply is connect and supplies to obtain stable double address (AD_PIN=0, AD_PIN=1).
Due to the use of rising edge, the displacement of the shift register of failing edge, comparative approach come generate four kinds of addresses and
There is bypass to design, it can be ensured that ensure under four address schemes in chip, make more stable double address scheme into, which ensure that core
Piece can be in the work under four stable addresses, double address pattern.Four kinds that different chips are connect according to single pin of the present invention
Pin can reliably export four kinds of different logic states, can save pin resource, to save encapsulation and chip area etc. at
This.
Further, since having used shift register, compared to counter, its cost is lower, smaller.
Those of ordinary skill in the art may realize that lists described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and method and step can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, depends on the specific application and design constraint of technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The range of the embodiment of the present invention.
Embodiment of above is merely to illustrate the embodiment of the present invention, and is not the limitation to the embodiment of the present invention, related skill
The those of ordinary skill in art field can also make various in the case where not departing from the spirit and scope of the embodiment of the present invention
Variation and modification, therefore all equivalent technical solutions also belong to the scope of the embodiment of the present invention, the patent of the embodiment of the present invention
Protection domain should be defined by the claims.
Claims (10)
1. a kind of I2C is from address generating device, which is characterized in that posted including input terminal, clock end, data terminal, rising edge displacement
Storage, failing edge shift register and dynamic address generation unit, the input terminal selectively with the clock end, data
End, ground terminal or power end connection；
The data that the clock signal that the rising edge shift register is inputted according to the clock end inputs the input terminal into
Row shift LD is handled and is exported to the first registered data；
The data that the clock signal that the failing edge shift register is inputted according to the clock end inputs the input terminal into
Row shift LD is handled and is exported to the second registered data；
The dynamic address generation unit determines the input terminal according to first registered data and second registered data
Connecting object, and generated from address according to the connecting object corresponding pattern decoding.
2. I2C according to claim 1 is from address generating device, which is characterized in that in the dynamic address generation unit
It is preset with pre-stored data corresponding with each pattern decoding, each pre-stored data is corresponding with a connecting object.
3. I2C according to claim 2 is from address generating device, which is characterized in that the pre-stored data includes the first number
According to and/or the second data.
4. I2C according to claim 3 is from address generating device, which is characterized in that the dynamic address generation unit root
Matched first data are determined according to first registered data, and/or, it is determined according to second registered data matched
Second data, to determine corresponding connection pair according to matched first data and/or matched second data
As.
5. I2C according to claim 1 is from address generating device, which is characterized in that
There is the rising edge shift register the first clock end, the rising edge shift register to pass through first clock end
It is connect with the clock end, and accesses the clock signal；
There is the failing edge shift register second clock end, the failing edge shift register to pass through the second clock end
It is connect with the clock end, and phase inverter is provided between the clock end and the second clock end, make the second clock
End inputs the inversion signal of the clock signal.
6. I2C according to claim 1 is from address generating device, which is characterized in that the I2C from address generating device also
Including bit counters, the bit counters are connect with the clock end, and the clock signal to being obtained from the clock end
High level is counted.
7. I2C according to claim 6 is from address generating device, which is characterized in that the I2C from address generating device also
Including controller, the controller is connect with the bit counters, and reaches predetermined value in the count value of the bit counters
When, it controls the dynamic address generation unit and the input terminal is determined according to first registered data and the second registered data
Connecting object.
8. I2C according to claim 1 is from address generating device, which is characterized in that the I2C from address generating device also
Including selector, the control terminal of the selector by the first amplifier ground or connects power supply, the first input of the selector
End is connect by the second amplifier with the input terminal, the second input terminal of the selector and the dynamic address generation unit
Connection,
When the control terminal is high level, the selector is according to the input value output state code of the input terminal；
When the control terminal is low level, the selector decodes output shape according to the output of the dynamic address generation unit
State code.
9. I2C according to claim 8 is from address generating device, which is characterized in that the I2C is from address generating device root
It is generated according to the conditional code and preset supplemental code described from address.
10. a kind of chip, which is characterized in that the chip includes that the I2C described in any one of claim 1-9 is generated from address
Device.
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