CN108446243B - Bidirectional communication method and system based on serial peripheral interface - Google Patents
Bidirectional communication method and system based on serial peripheral interface Download PDFInfo
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- CN108446243B CN108446243B CN201810228292.2A CN201810228292A CN108446243B CN 108446243 B CN108446243 B CN 108446243B CN 201810228292 A CN201810228292 A CN 201810228292A CN 108446243 B CN108446243 B CN 108446243B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The purpose of the application is to provide a bidirectional communication method and system based on a serial peripheral interface, which are used for communication between microcontrollers, wherein a first microcontroller works in a master device mode, and a second microcontroller works in a slave device mode; the method comprises the following steps: when the second microcontroller has first data to be transmitted which needs to be sent to the first microcontroller, chip-selecting the first microcontroller; chip selecting the second microcontroller; the first microcontroller sends a serial clock signal to the second microcontroller which is selected by the chip; the second microcontroller sends the first data to be transferred to the first microcontroller via the MISO line based on the serial clock signal. The method and the system realize the bidirectional active communication of the master device and the slave device in an unconventional 4-wire system mode, and solve the problem that the data transmission of a non-response mechanism is unreliable.
Description
Technical Field
The present application relates to the field of communications, and more particularly, to a technique for bidirectional communication between two or more microcontrollers.
Background
SPI is a Serial Peripheral Interface (SPI), which is a three-wire synchronous bus communication technology proposed by Motorola corporation, and has communication characteristics of high speed, full duplex, and synchronous communication. Both parties of the communication operate in a master-slave manner, typically with a master device and one or more slave devices. Referring to fig. 1, In the SPI communication technique, data is transmitted In the form of data bits through a switching form, a master device generates an SCK (serial clock) clock pulse and transmits the data to a Slave device through an mosi (master Out Slave In) line, the Slave device transmits the data to the master device through a miso (master In Slave Out) line In response to the SCK signal, the data changes at a rising edge or a falling edge of a clock and is read at an immediately following falling edge or rising edge. The slave device has a chip select pin, which is set by the master device, and when the master device needs to communicate with the slave device, taking the chip select pin CS of fig. 1 as effective at low voltage as an example, the chip select pin of the slave device is first set low.
The SPI communication technology enables the micro control chip to have the function of synchronous communication with peripheral equipment or other micro controllers, the hardware function of the micro controllers is expanded, the software design related to the SPI is simplified, and the utilization rate of a CPU is reduced.
However, the existing SPI communication technology has technical defects that the data flow control is not directional, no response mechanism is used to confirm whether data is received, and the slave device cannot actively transmit information to the master device, which causes great limitation in the application field of the SPI technology.
Disclosure of Invention
In view of the defects of the prior art, an object of the present application is to provide a bidirectional communication method based on a serial peripheral interface to control the data flow direction when the master device and the slave device communicate, and to implement a bidirectional active and highly reliable unconventional 4-wire communication mode between the master device and the slave device.
According to one aspect of the application, a bidirectional communication method based on a serial peripheral interface is provided for communication between microcontrollers. Wherein the first microcontroller operates in a master mode and the second microcontroller operates in a slave mode; the first microcontroller sends data bits to the second microcontroller via a MOSI line, and the second microcontroller sends data bits to the first microcontroller via a MISO line. The method comprises the following steps:
s100, when the second microcontroller has first data to be transmitted which needs to be sent to the first microcontroller, chip-selecting the first microcontroller;
s200, chip selecting the second microcontroller;
s300, the first microcontroller sends a serial clock signal to the second microcontroller;
s400 the second microcontroller sends the first data to be transferred to the first microcontroller via the MISO line based on the serial clock signal.
According to an embodiment of the present invention, the step S100 includes:
and when the buffer of the second microcontroller has first data to be transmitted which needs to be sent to the first microcontroller, chip-selecting the first microcontroller.
According to an embodiment of the present invention, the step S300 includes:
and the first microcontroller sends a serial clock signal to the second microcontroller and sends second data to be transmitted to the second microcontroller through the MOSI line.
According to an embodiment of the invention, the method further comprises:
s310, when the first to-be-transmitted data is transmitted, the first microcontroller is deselected.
According to an embodiment of the invention, the method further comprises:
s320, when the first microcontroller is not chip-selected and third data to be transmitted which needs to be sent to the second microcontroller exists in the first microcontroller, the first microcontroller sends a serial clock signal to the second microcontroller and sends the third data to be transmitted to the second microcontroller through the MOSI line.
According to one embodiment of the invention, the first data to be transmitted comprises first data bits and at least one first check bit, the at least one first check bit being generated based on the first data bits and a check algorithm;
the method further comprises the following steps:
s500, the first microcontroller checks the first data to be transmitted based on the checking algorithm and the first check bit;
s600, when the first data to be transmitted passes the verification, the first microcontroller sends a first response signal to the second microcontroller.
According to an embodiment of the invention, the method further comprises:
the second microcontroller sends the first data to be transmitted to the first microcontroller through the MISO line based on the serial clock signal sent by the first microcontroller until the second microcontroller receives the first acknowledgement signal.
According to an embodiment of the present invention, the second data to be transmitted includes second data bits and at least one second parity bit, the at least one second parity bit being generated based on the second data bits and a parity algorithm;
the method further comprises the following steps:
s301, the second microcontroller checks the second data to be transmitted based on the checking algorithm and the second checking bit;
s302, when the second data to be transmitted passes the verification, the second microcontroller sends a second response signal to the first microcontroller.
According to an embodiment of the invention, the method further comprises:
and the first microcontroller sends a serial clock signal to the second microcontroller and sends the second data to be transmitted to the second microcontroller through the MOSI line until the first microcontroller receives the second response signal.
According to another aspect of the present application, there is provided a serial peripheral interface-based bidirectional communication system, comprising:
a first microcontroller including a first chip select pin and operating in a master mode;
the second microcontroller comprises a second chip selection pin and works in a slave device mode; and
and a communication control module, wherein a first control output end of the communication control module is connected with the first chip selection pin, a second control output end of the communication control module is connected with the second chip selection pin, and the communication control module is configured according to the bidirectional communication method.
According to the bidirectional communication method based on the serial peripheral interface, under the condition that the master device detects that new data are sent to the slave device, the master device can actively send a clock signal to the slave device for data transmission, and sends the data in the master device to the slave device, and the chip selection signal of the master device does not need to be operated in the process; and under the condition that the slave device detects that new data is sent to the master device, the slave device actively selects the master device in an unconventional 4-wire system mode, the master device detects that a chip selection signal of the master device is effective, a clock signal is sent to the slave device, and the slave device carries out data transmission to the master device, so that the purpose that the slave device actively sends the data to the master device is achieved. On the basis, after the slave equipment receives the data, the slave equipment waits for an ACK (acknowledgement) response signal of the master equipment, after the slave equipment receives the ACK response signal, the data transmission is finished, the chip selection master equipment is cancelled, and otherwise, the data is retransmitted; and after receiving the ACK response signal sent by the slave equipment, the master equipment finishes data transmission, otherwise, the data is retransmitted.
Generally, the SPI chip connection mode is that an I/O pin of the master device sends a chip select signal, a slave device chip select pin receives the chip select signal, and the chip select determines that data sent by the slave device can be received by the master device; the scheme provides an unconventional SPI communication mode, a chip selection pin of a slave device is used as an I/O port to output a chip selection signal, and an I/O pin of a master device is used as a party for receiving the chip selection signal, so that the master device actively sends the chip selection signal, the slave device passively receives the chip selection signal, the chip selection signal is converted into the slave device and can also actively send the chip selection signal, and the master device can also receive the chip selection signal and receive new data of the slave device. Compared with the prior art, the method and the device can control the direction of the data stream when the master device and the slave device communicate, and realize the bidirectional active communication of the master device and the slave device, thereby solving the problems that the data stream is uncontrollable and the slave device end cannot actively send data in the SPI communication; one end of the transmitted data sends an ACK (acknowledgement) response signal after receiving the data, so that the receiving equipment can be confirmed to receive the data, and the problem that the data transmission is unreliable by a non-response mechanism is solved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 illustrates a master-slave device communication principle based on SPI;
FIG. 2 shows two microcontrollers communicating bi-directionally, according to one embodiment of the present application;
fig. 3 shows a flow diagram of a method of two-way communication according to one embodiment of the present application.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present application is described in further detail below with reference to the attached figures.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. Where certain terms are used in the description and claims to refer to particular components, those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not intend to distinguish between components that differ in name but not function. The terms "including" and "comprising" as used throughout this specification and claims are open-ended terms that should be interpreted to mean "including, but not limited to. Further, the term "coupled" is intended to include any direct or indirect electrical connection. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.
Fig. 2 shows two microcontrollers, a first microcontroller 100 and a second microcontroller 200, respectively, communicating bi-directionally according to one aspect of the present application. The first microcontroller 100 and the second microcontroller 200 perform data transmission through MOSI lines and MISO lines, and an I/O interface of the second microcontroller 200 is connected to a Chip Select (CS) interface of the first microcontroller 100 and controls a chip select signal of the first microcontroller 100 through the I/O interface, wherein the I/O interface or the chip select signal is based on a software and/or hardware configuration. The following description will be given by taking the example that the chip selection signals of the first microcontroller 100 and the second microcontroller 200 are both low-potential signals; in some embodiments, the chip select signal of the first microcontroller 100 or the second microcontroller 200 is active at a high level, and the level of the corresponding level can be adjusted according to actual conditions to implement the bidirectional communication method disclosed in the present application, but still included in the scope of the present application.
The method includes step S100 (not shown), step S200 (not shown), step S300 (not shown), and step S400 (not shown), which are described in detail below.
After the communication preparation is completed, in step S100, when there is a first data to be transmitted in the second microcontroller 200, which needs to be sent to the first microcontroller 100, the chip select first microcontroller 100 pulls down the chip select interface level of the first microcontroller 100, for example, through the I/O interface of the second microcontroller 200. To establish a communication relationship between the first microcontroller 100 and the second microcontroller 200, the second microcontroller 200 is chip selected in step S200. Subsequently in step S300, the first microcontroller 100 sends a serial clock Signal (SCK) to the second microcontroller 200 that is chip selected. In step S400, the second microcontroller 200 receives the serial clock Signal (SCK), and then sends data to the first microcontroller 100 via the MISO line, wherein the data sending operation is performed according to the serial clock Signal (SCK) sent by the first microcontroller 100, for example, one data bit of the first data to be transmitted may be transmitted on each rising edge or falling edge of the serial clock signal.
Therein, in some embodiments, the second microcontroller 200 determines whether data needs to be sent to the first microcontroller 100 by checking whether there is data in its buffer in step S100. For example, when there is data (first data to be transferred) in the buffer of the second microcontroller 200, the second microcontroller 200 writes the first data to be transferred to its register. Taking the example that the second microcontroller 200 starts to transmit the data in the register from the MSB (Most Significant Bit) to the first microcontroller 100, the MSB of the data in the register of the second microcontroller 200 is transmitted to the lsb (least Significant Bit) of the register of the first microcontroller 100 via the MISO line, and the first microcontroller 100 retrieves the data in the register to the buffer, so that the data transmission from the second microcontroller 200 to the first microcontroller 100 is completed. The first microcontroller 100 operates in a master state, and the second microcontroller 200 operates in a slave state, so that the above method realizes that the slave actively transmits data to the master.
In some embodiments, the second microcontroller 200 actively and unidirectionally transmits valid data to the first microcontroller 100. When the first microcontroller 100 sends a serial clock Signal (SCK) to the second microcontroller 200 that is selected, dummy data is also sent to the second microcontroller 200 through the MOSI line, and the second microcontroller 200 can discard the dummy data after receiving the dummy data. For example, as in the previous example, the dummy data is padded to the LSB of the second microcontroller 200. In particular, the dummy data may be null data.
In other embodiments, while the second microcontroller 200 transmits data to the first microcontroller 100, the first microcontroller 100 may also send data to the second microcontroller 200, so as to implement bidirectional communication between a master device and a slave device, thereby improving communication efficiency. For example, in the above method, in step S300, there is also data (second data to be transmitted) that needs to be sent to the second microcontroller 200 in the buffer of the first microcontroller 100, and at this time, the first microcontroller 100 sends the second data to be transmitted to the second microcontroller 200 through the MOSI line in addition to sending the serial clock signal to the second microcontroller 200. Still taking the example that the second microcontroller 200 transmits the data in the register from the MSB (Most Significant Bit) to the first microcontroller 100, the first microcontroller 100 sends the second data to be transmitted to the second microcontroller 200 into its register, and transmits the MSB of the data in the register to the LSB of the second microcontroller register through the MOSI line, where the registers of the first microcontroller 100 and the second microcontroller 200 are both shift registers, and the exchange process of the data bits forms a closed loop.
In some embodiments, after the second microcontroller 200 transmits to the first microcontroller 100, the method further includes step S310 (not shown). In step S310, when the first to-be-transmitted data is completely transmitted, the chip selection of the first microcontroller is cancelled, for example, the level of the chip selection interface of the first microcontroller 100 is pulled up through the I/O interface of the second microcontroller 200, and the communication process between the first microcontroller 100 and the second microcontroller 200 is finished; if the first microcontroller 100 operating in the master state is also connected to another microcontroller operating in the slave state, the first microcontroller 100 may perform data transmission or data exchange with the other microcontroller. Whether the data transmission from the second microcontroller 200 to the first microcontroller 100 is completed or not can be determined according to whether there is data in the buffer of the second microcontroller 200, for example, when there is no data in the buffer of the second microcontroller 200, the transmission process is completed.
Wherein, in some embodiments, the method further comprises step S320 (not shown). In step S320, when the first microcontroller 100 is not chip-selected and the first microcontroller 100 has third data to be transmitted that needs to be sent to the second microcontroller 200, the first microcontroller 100 sends a serial clock signal to the second microcontroller 200, and sends the third data to be transmitted to the second microcontroller 200 through the MOSI line.
Because the existing SPI communication device has the defect that no response mechanism is used to confirm whether data is received, once an error occurs in the data transmission process, a large amount of data may need to be retransmitted, which seriously reduces the communication efficiency. To overcome this drawback, in some embodiments, the process of the first microcontroller 100 transmitting data to the second microcontroller 200 is provided with an ack (acknowledgement) acknowledgement mechanism, wherein the data transmitted from the first microcontroller 100 to the second microcontroller 200 is a data frame. For convenience of description, the data frame transmitted from the first microcontroller 100 to the second microcontroller 200 is referred to as a first data frame. Wherein each first data frame end comprises at least one check bit, and the check bit is generated based on a check algorithm according to the data bits of the first data frame. After the data bits of the first data frame are completely transmitted, the first microcontroller 100 waits for an ACK response signal returned by the second microcontroller 200; the second microcontroller 200 calculates a check result according to the data portion in the first data frame based on the same check algorithm as the first microcontroller 100, compares the check result with one or more check bits sent by the first microcontroller 100, if the check result is the same as the check result, the second microcontroller 200 sends an ACK response character (response signal) to the buffer, which represents that the first data frame sent by the second microcontroller 200 has been successfully received; the ACK response character is transmitted to the second microcontroller 200, and the second microcontroller 200 starts transmission of the next data frame after receiving the ACK response character. If the check fails, the first microcontroller 100 discards the first data frame and waits for the next transmission by the second microcontroller 200; the second microcontroller 200 does not receive the ACK character, and retransmits the first data frame to the first microcontroller 100 in the next transmission cycle until the ACK character transmitted by the first microcontroller 100 is received, and the transmission is successful, and transmission of the next data frame is prepared. Therefore, once the transmission is in error, only the data frame in error needs to be retransmitted, and the whole batch of data does not need to be retransmitted.
Similar to the above process, an ACK response mechanism may also be set when the first microcontroller 100 transmits the data frame to the second microcontroller 200, and the execution flow is similar to that described above and is not described again and is included herein by way of reference. FIG. 3 illustrates a serial peripheral interface based bi-directional communication method including an ACK acknowledgement mechanism.
The check bits used to verify the validity of the data frames transmitted between the microcontrollers may be based on a single check bit, for example, using a parity check, or hamming check. In order to improve the probability of successful receiving of a receiving party in the information transmission process as much as possible so as to improve the transmission efficiency, Cyclic Redundancy Check (CRC) with certain error correction capability can be adopted for a data frame, and accordingly the data frame comprises a data section (consisting of useful information codes) and a Check section (consisting of the information codes and generated according to a generating polynomial), and the Check section is the checksum of the data section. The cyclic redundancy check has an error correction capability of 1 bit. After the data frame is successfully checked or the error correction is successful, the receiving party sends an ACK character to the sending party to indicate that the transmission is successful; otherwise, the receiving party enters a delay mode and waits for the sending party to retransmit the error data frame.
According to another aspect of the present application, there is also disclosed a bidirectional communication system based on a serial peripheral interface, comprising:
a first microcontroller including a first chip select pin and operating in a master mode;
the second microcontroller comprises a second chip selection pin and works in a slave device mode; and
and a communication control module, wherein a first control output end of the communication control module is connected with the first chip selection pin, a second control output end of the communication control module is connected with the second chip selection pin, and the communication control module is configured according to the method.
The communication control module can be implemented based on software and/or hardware.
The foregoing detailed description of the preferred embodiments of the present application.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware, for example, implemented using Application Specific Integrated Circuits (ASICs), general purpose computers or any other similar hardware devices. In one embodiment, the software programs of the present application may be executed by a processor to implement the steps or functions described above. Likewise, the software programs (including associated data structures) of the present application may be stored in a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. Additionally, some of the steps or functions of the present application may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.
In addition, some of the present application may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or techniques in accordance with the present application through the operation of the computer. Those skilled in the art will appreciate that the form in which the computer program instructions reside on a computer-readable medium includes, but is not limited to, source files, executable files, installation package files, and the like, and that the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Computer-readable media herein can be any available computer-readable storage media or communication media that can be accessed by a computer.
Communication media includes media by which communication signals, including, for example, computer readable instructions, data structures, program modules, or other data, are transmitted from one system to another. Communication media may include conductive transmission media such as cables and wires (e.g., fiber optics, coaxial, etc.) and wireless (non-conductive transmission) media capable of propagating energy waves such as acoustic, electromagnetic, RF, microwave, and infrared. Computer readable instructions, data structures, program modules, or other data may be embodied in a modulated data signal, for example, in a wireless medium such as a carrier wave or similar mechanism such as is embodied as part of spread spectrum techniques. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. The modulation may be analog, digital or hybrid modulation techniques.
By way of example, and not limitation, computer-readable storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory such as random access memory (RAM, DRAM, SRAM); and non-volatile memory such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic/ferroelectric memories (MRAM, FeRAM); and magnetic and optical storage devices (hard disk, tape, CD, DVD); or other now known media or later developed that can store computer-readable information/data for use by a computer system.
An embodiment of the present application comprises an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the apparatus to perform a method and/or a solution according to the aforementioned embodiments of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (9)
1. A bidirectional communication method based on a serial peripheral interface is used for communication between microcontrollers, wherein a first microcontroller works in a master device mode, and a second microcontroller works in a slave device mode; the first microcontroller sends data bits to the second microcontroller via a MOSI line, the second microcontroller sends data bits to the first microcontroller via a MISO line; it is characterized by comprising:
s100, when the second microcontroller has first data to be transmitted which needs to be sent to the first microcontroller, chip-selecting the first microcontroller; the first data to be transmitted comprises first data bits and at least one first check bit, and the at least one first check bit is generated based on the first data bits and a check algorithm;
s200, chip selecting the second microcontroller;
s300, the first microcontroller sends a serial clock signal to the second microcontroller which is selected by a chip;
s400 the second microcontroller sends the first data to be transferred to the first microcontroller via the MISO line based on the serial clock signal;
s500, the first microcontroller checks the first data to be transmitted based on the checking algorithm and the first check bit;
s600, when the first data to be transmitted passes the verification, the first microcontroller sends a first response signal to the second microcontroller;
the data frame transmitted from the first microcontroller to the second microcontroller is called a first data frame;
the end of each first data frame comprises at least one check bit, and the check bit is generated based on a check algorithm according to the data bits of the first data frame;
after the data bits of the first data frame are completely transmitted, the first microcontroller waits for an ACK (acknowledgement) response signal returned by the second microcontroller;
the second microcontroller calculates a checking result according to the data part in the first data frame based on the same checking algorithm as the first microcontroller, compares the checking result with one or more checking bits sent by the first microcontroller, if the checking result is the same as the checking result, the second microcontroller sends an ACK response character to the buffer to represent that the first data frame sent by the second microcontroller is successfully received;
the ACK response character is transmitted to the second microcontroller, and the second microcontroller starts to transmit the next data frame after receiving the ACK response character;
if the check fails, the first microcontroller discards the first data frame and waits for the next transmission of the second microcontroller; and the second microcontroller does not receive the ACK character, and resends the first data frame to the first microcontroller in the next transmission period until the ACK character sent by the first microcontroller is received, and the transmission is successful, and the next data frame is prepared for transmission.
2. The method of claim 1, wherein the S100 comprises:
and when the buffer of the second microcontroller has first data to be transmitted which needs to be sent to the first microcontroller, chip-selecting the first microcontroller.
3. The method of claim 1, wherein the S300 comprises:
and the first microcontroller sends a serial clock signal to the second microcontroller and sends second data to be transmitted to the second microcontroller through the MOSI line.
4. The method of claim 1, further comprising:
s310, when the first to-be-transmitted data is transmitted, the first microcontroller is deselected.
5. The method of claim 4, further comprising:
s320, when the first microcontroller is not chip-selected and third data to be transmitted which needs to be sent to the second microcontroller exists in the first microcontroller, the first microcontroller sends a serial clock signal to the second microcontroller and sends the third data to be transmitted to the second microcontroller through the MOSI line.
6. The method of claim 1, wherein the method further comprises:
the second microcontroller sends the first data to be transmitted to the first microcontroller through the MISO line based on the serial clock signal sent by the first microcontroller until the second microcontroller receives the first acknowledgement signal.
7. The method of claim 3, wherein the second data to be communicated comprises second data bits and at least one second parity bit, the at least one second parity bit generated based on the second data bits and a parity algorithm;
the method further comprises the following steps:
s311, the second microcontroller checks the second data to be transmitted based on the checking algorithm and the second checking bit;
s312, when the second data to be transmitted passes the verification, the second microcontroller sends a second response signal to the first microcontroller.
8. The method of claim 7, wherein the method further comprises:
and the first microcontroller sends a serial clock signal to the second microcontroller and sends the second data to be transmitted to the second microcontroller through the MOSI line until the first microcontroller receives the second response signal.
9. A bi-directional communication system based on a serial peripheral interface, comprising:
a first microcontroller including a first chip select pin and operating in a master mode;
the second microcontroller comprises a second chip selection pin and works in a slave device mode; and
a communication control module having a first control output connected to the first chip select pin and a second control output connected to the second chip select pin, and configured according to the method of any one of claims 1 to 8.
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| CN111490920A (en) * | 2019-01-29 | 2020-08-04 | 杭州海康汽车技术有限公司 | SPI-based data transmission method, system and device |
| CN110798269B (en) * | 2019-09-24 | 2021-12-10 | 深圳震有科技股份有限公司 | Method and system for realizing PCM slave function based on GPIO |
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