JPH0419731B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method for transmitting data in frames between exchanges, between CPUs, etc., and more specifically, to a method for transmitting data in frames, such as between exchanges or between CPUs. This relates to data transmission methods. [Prior art and its problems] There are two basic transmission error control methods in data transmission systems, namely ARQ (automatic-
repeat-request) method and FEC (forward-error-
correction) method, but the ARQ method is widely used due to its simplicity and reliability. The ARQ method is also called the ACK/NAK method, and if there is no error in the received frame, it will receive an "ACK" (acknowledgement).
is sent back to the sender, and if there is an error, a NAK (negative acknowledgment or retransmission request) is sent back.
There are three types of ARQ methods: standby ARQ, continuous retransmission ARQ, and selective retransmission ARQ, depending on the operation from the transmitting side transmitting one frame to receiving a response thereto. In continuous retransmission type ARQ and selective retransmission type ARQ, the transmitting side continuously sends multiple frames to the receiving side, and the receiving side sends a response signal to these frames, that is, ACK if there is no error in the frame, and ACK if there is no error in the frame. If you do, send a NAK. When a continuous repeat ARQ transmitter receives a NAK, it returns to the corresponding frame and retransmits all the frames that were sent up to the time it received the NAK. Furthermore, when the transmitting side of selective retransmission type ARQ receives a NAK, it retransmits only the corresponding block. All of these methods are efficient in transmission systems with long round-trip transmission times, but require buffering of multiple frames and are complicated to control. Therefore, in a transmission system with a relatively short round-trip transmission time,
It is not suitable when trying to realize a simple system. In standby ARQ, after transmitting one frame, the transmitter waits until it receives a response signal, and if the response signal is ACK, it transmits the next frame, and if it is NAK, it retransmits the previous frame. This is the method to do it. FIG. 7 to FIG. 9 are diagrams for explaining the state of transmission of standby type ARQ. FIG. 7 shows a case where there is no signal error or signal loss, and one frame transmission is completed in one round-trip transmission time, and efficient transmission can be performed when the round-trip transmission time is short. FIG. 8 shows a case where there is an error in the transmitted signal, and it takes two round trip transmission times to transmit one frame, resulting in a considerable drop in transmission efficiency. FIG. 9 shows a case where the transmitted signal is lost or the response signal is lost, and in either case, the response signal does not reach the transmitting side. In this case, the sending side monitors the non-response time, sends an "ENQ (response prompt)" after a certain period of time, and waits for a response again. Generally, the non-response time is sufficiently long compared to the round-trip transmission time, so the transmission efficiency is extremely reduced. As described above, standby ARQ is simpler than other methods, has short round-trip transmission time, and is efficient when there are no errors in the transmission path, but when there is an error in the transmission path, The disadvantage is that the transmission efficiency is extremely reduced. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transmission system in which transmission efficiency is less reduced even when errors occur. [Means for Solving the Problems] In order to solve the above problems and achieve the above objects, the present invention includes first main data, error check data, and identification data of the first main data. repeatedly transmitting a first frame containing a plurality of frames from a first transmitting/receiving circuit to a second transmitting/receiving circuit in frame units;
receiving a frame, and determining whether or not the first main data has been received without error using the error check data; and the first main data is received without error by the determination. If confirmed, a response signal (ACK) corresponding to the identification signal is formed, this response signal (ACK) is transmitted to the first transmitting/receiving circuit, and after this, the second transmitting/receiving circuit discarding the received first main data and extracting only one error-free first main data as valid data; and sending the response signal (ACK) in the first transmitting/receiving circuit.
When the response signal (ACK) is detected, stopping the transmission of the first frame from the first transmitting/receiving circuit to the second transmitting/receiving circuit, and transmitting the second main data and error check. transmitting a second frame including identification data of the second main data from the first transmitting/receiving circuit to the second transmitting/receiving circuit multiple times in frame units; Determining data reception errors;
A response signal (ACK) corresponding to the second main data
This relates to a data transmission system characterized in that the formation, transmission, and detection of the data are performed in the same manner as in the case of the first main data. [Operation] In the above invention, the same main data is sent multiple times until a response signal (ACK) is obtained.
Therefore, if an error occurs in the first transmission, valid data can be selected from the second and subsequent transmission data. Therefore, even if an error occurs in data transmission, there is little reduction in transmission efficiency. Also,
Returns a response signal (ACK) corresponding to the identification signal,
Since this is a method for controlling transmission, the system configuration is simple, similar to conventional standby ARQ. [Embodiment] Next, a data transmission system according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 shows full-duplex digital data in which a first transmitting/receiving circuit 1a and a second transmitting/receiving circuit 1b exchange data via a data transmission circuit 2 consisting of first and second transmission paths 3 and 4. A transmission system is shown. The first transmitting/receiving circuit 1a has a transmitting buffer memory 5, a frame synthesizing circuit 6, and a parity adding circuit 7 in sequence on the transmitting side, and a parity error detecting circuit 8, a frame separating circuit 9 on the receiving side. ,
and reception buffer memory 10 in sequence. Further, a transmission control section 11 and a reception control section 12 are provided. The second transmitting/receiving circuit 1b is configured exactly the same as the first transmitting/receiving circuit 1a. Therefore,
A dash is attached to the reference numerals indicating each part of the second transmitting/receiving circuit 1b, and a detailed explanation of each part is omitted. In addition,
The transmission circuit 2 generally includes modulation and demodulation circuits, exchanges, etc., but these are omitted and only the first and second transmission lines 3 and 4 are shown. The data format of the unit frame in the first and second transmission lines 3 and 4 in FIG. 1 is as shown in FIG. This format is a response signal (hereinafter simply referred to as
Consists of 2 bits in which the ACK (called ACK) is written.
ACK field C ₁ and a 1-bit field in which data indicating whether the main data included in this frame is an odd or even number (hereinafter referred to as NS) is written.
NS field _C2 , a 1-bit DF field _C3 in which data indicating the presence or absence of transmission data (hereinafter referred to as DF) is written, a multi-bit data field _C4 , and a 1-bit parity bit field, that is, P. Field C consists of ₅ . In the ACK field _C1 , [00] or [11] is written if there is no ACK, [01] is written if the ACK is for odd number data, and [10] is written if the ACK is for even number data. written. NS field C ₂ contains data for identifying the main data in the case of odd-numbered transmission data.

[0]
is written, and [1] is written in the case of even-numbered transmission data. DF field C ₃ has no data to send.

[0] is written, and if there is transmission data, [1] is written. In addition, if the presence or absence of transmission data (main data) can be determined based on the contents of data field _C4 ,
DF field C ₃ may not be present. For example, all the data in data field C ₄ is

This is a case where the data in the data field is defined so that transmission is invalid when it is [0] and valid otherwise. The even parity of the data from the ACK field _C1 to the data field _C4 is written to the P field _C5 . Note that, instead of using parity for error detection, a CRC check may be used to further ensure error detection. [Operation] The transmission buffer memory 5 reads transmission data (first main data) from a data source such as a CPU (not shown), and temporarily holds it. This holding time is when the first main data currently being transmitted is sent to the second transmitting/receiving circuit 1b on the other side, an ACK is sent back from the second transmitting/receiving circuit 1b to the first transmitting/receiving circuit 1a, and this is confirmed. Until then. The first main data of the transmission buffer memory 5 is
It is read out under the control of the transmission control section 11 and sent to the frame synthesis circuit 6. The frame synthesis circuit 6 uses the ACK sent from the reception control section 12, the DF and NS sent from the transmission control section 11, and the first main data sent from the transmission buffer memory 5 to create the P of the format shown in FIG. field C ₅
Achieve the arrangement of data for fields C ₁ to _{C 4} other than the above. Note that DF is determined by checking the presence or absence of data in the transmission buffer memory 5 by the transmission control section 11. The transmission control unit 11 sends an NS indicating odd-numbered first main data at the start of data transmission.
=0, then sends NS=1 when sending the second main data (even-numbered data), and sends NS=0 again when sending the next odd-numbered main data. From the reception control unit 12 to the frame synthesis circuit 6
The ACK given to the second transmitter/receiver circuit 1b is determined by NS and DF in the data format sent from the second transmitter/receiver circuit 1b to the first transmitter/receiver circuit 1a.
Now, when DF=1 indicating the presence of main data and NS=0 indicating odd-numbered main data are given from the frame separation circuit 9 of the first transmitting/receiving circuit 1a to the receiving control circuit 12, ACK is sent. =01 is given to the frame synthesis circuit 6 and written to the ACK field _C1 . The parity addition circuit 7 determines even parity from the ACK field _C1 to the data field _C4 , and writes it into the parity bit field _C5 . As a result, the format for one frame shown in FIG. 5 is completed, and is sent to the second transmitting/receiving circuit 1b via the first transmission path 3. By the way, in the data transmission system according to the present invention, main data (frames) with the same content are sent multiple times. FIG. 3 shows a multiple transmission situation according to the invention in the case of no errors. Now, after sending out the first main data from the first transmitting/receiving circuit 1a in t ₀ to t ₁ , the same first main data is sent out in the intervals t ₁ to t ₂ , t ₂ to _{t 3} , and t ₃ to t _{4 .} Send out the th main data. That is, the same data is sent without waiting for (reception of ACK) in response to the transmission. This multiple data transmission is an ACK
is carried out until it is obtained. The data transmitted from t ₀ to _{t 1} in FIG. 3 is received by the second transmitting/receiving circuit 1b from t ₁ to t ₂ . When data is input to the second transmitting/receiving circuit 1b in the format shown in FIG. 2, a parity check is performed by a parity error detection circuit 8'. If a parity error is detected, the data of this frame is discarded. When there is no error, data in fields other than parity field _C5 is sent to frame separation _circuit 9'. The frame separation circuit 9' is the second
From ACK field C ₁ in the format shown in the figure
Extracts the ACK and outputs it to the transmission control unit 11', and sends it to the NS
Field C ₂ and DF Field C ₃ to NS and
DF is extracted and outputted to the reception control section 12', and data field _C4 is extracted and outputted to the reception buffer 10'. Transmission control section 1 in second transmission/reception circuit 1b
1' replaces the data in the transmission buffer memory 5' with new data when an ACK is obtained from the frame separation circuit 9'. The reception control section 12' forms an ACK based on the DF and NS obtained from the frame separation circuit 9', and outputs it to the frame synthesis circuit 6'. In the case of FIG. 3, since the first (odd numbered) data is received between _t1 and _t2 , ACK=01 is given to the frame synthesis circuit 6'. In the frame synthesizing circuit 6', the data format sent from the second transmitting/receiving circuit 1b to the first transmitting/receiving circuit 1a is formed in the same manner as in the case of the first transmitting/receiving circuit 1a, and furthermore, the parity adding circuit 7' formats the data to be sent to the first transmitting/receiving circuit 1a. The signal is added and sent to the first transmitting/receiving circuit 1a during the period from _t2 to _t3 in FIG. The first transmitting/receiving circuit 1a transmits _{the second}
Similarly to the transmitting/receiving circuit 1b, parity error detection,
and frame separation. The transmission control unit 1 confirms that ACK=01 is obtained from the frame separation circuit 9.
1 is confirmed, the transmission of the first main data (first frame) is completed. As a result, the transmission of the first main data from the first transmitting/receiving circuit 1a to the second transmitting/receiving circuit 1b is reliably performed, so that the transmitting buffer memory 5 is
It becomes unnecessary to maintain the th main data. Therefore, the second (even-numbered) main data is read into the transmission buffer memory 5 and sent out to the second transmission/reception circuit 1b from t ₄ to t ₅ . In the case of the second main data, NS = 1 indicating an even number is NS
It is sent in the format written in field _C2 . When transmitting the third main data
Write NS=0 to NS field _C2 and send.
If error-free transmission is occurring, ACK=10 is returned in response to the second data transmission. Also in response to the third data transmission
ACK=01 is returned. What is extremely important in the data transmission method according to the present invention is that even though the method uses only ACK without using NAK, the first transmission of the first main data occurs between t ₀ and _{t 1} . t ₁ ~ t ₂ , t ₂ ~ after
At t ₃ , from t ₃ to _{t 4} , the second of the first main data,
This is to perform the third and fourth transmissions. That is, the first main data is transmitted to the second transmitting/receiving circuit 1b.
response signal (ACK) indicating that it has been reliably received by
The same main data continues to be sent repeatedly a plurality of times until it is sent back to the first transmitting/receiving circuit 1a.
Note that the data in the ACK field within a frame is not necessarily constant during repeated transmission. In the case of FIG. 3, since the first transmission was performed without error, the second, third, and fourth received data obtained from t ₂ to t ₅ are discarded. Second transmitter/receiver circuit 1
In b, whether or not to discard the received data is determined by the detection of NS. From the first transmitting/receiving circuit 1a to the second transmitting/receiving circuit 1
If an error occurs in the first transmission of main data to b, the operation is as shown in FIG.
If the first (odd numbered) data is sent from t ₀ to _{t 1} in FIG. 4, and an error is detected by the parity check in the parity error detection circuit 8' from t ₁ to t ₂ , The main data of this frame is discarded. The first main data is also transmitted from t ₁ to t ₂ without waiting for a response signal (ACK) thereto. Therefore, the second transmitting/receiving circuit 1b receives the main data from the second transmission from _t2 to _t3 . If there is no error in the frame containing this main data, ACK=01 is sent back to the first transmitting/receiving circuit 1a from _t3 to _t4 . The first transmitting/receiving circuit 1a is
When ACK=01 is detected from t ₄ to _{t 5} , transmission of the first main data is stopped, and from t ₅ to t ₆ , the second main data is sent. Therefore, if an error occurs in the first data transmission, the same data will be transmitted five times. Now, if one frame transmission time is T, the minimum necessary round trip transmission time when no error occurs is 4T, and the data required when an error occurs between t ₀ and t ₁ in Figure 3. The transmission time will be 5T. Therefore, even if an error occurs in data transmission, the data transmission time only increases by one frame transmission time T. In Fig. 4, the second main data is transmitted from _t5 to _t6 , reception is confirmed from _t6 to _t7 , second transmission is performed from _t6 to _t7 , and from _t7 to _t8 . If it is confirmed that there is an error, the second main data will not be transmitted more than five times since error-free reception has already been completed from _t6 to _t7 . The second main data transmission ends when a response of ACK=10 based on the first data transmission is obtained between _t8 and _t9 . From the first transmitting/receiving circuit 1a to the second transmitting/receiving circuit 1
If a frame is lost in the transmission to b, or if there is an error in the transmission of ACK from the second transmitting/receiving circuit 1b to the second transmitting/receiving circuit 1a,
If the ACK is lost, the desired ACK cannot be obtained, so the transmission of the same data is repeated until the desired ACK is obtained. The transmission control section 11 and the reception control section 12 are composed of a CPU. FIG. 5 is a flowchart showing the operating procedure according to a predetermined program in the CPU. At the start of data transmission, the step
In _P1 , the data to be written in the DF field _C3 , ie, DF, is set to 0, and the data to be written in the NS field _C2 is set to _F1 =0. After completing the initial settings in step _P1 , proceed to step P1.
Input the transmission data (main data) into the transmission buffer memory 5 at _P2 . Next, in step _P3 , NS=0 is created indicating that the main data number held in the transmission buffer memory 5 is an odd number, and at the same time, DF is created indicating that there is transmission data.
=1 and give these to the frame synthesis circuit 6. As a result, the same data transmission is performed multiple times as shown in FIGS. 3 and 4, and the data is transmitted from the second transmitting/receiving circuit 1b to the first transmitting/receiving circuit 1a.
An ACK will be sent back. Therefore, the transmission control section 1
1, for the data currently being sent
Step _P4 waits for ACK to be obtained from the frame separation circuit 9. Then, in step _P4 , the contents of the ACK are decoded. If ACK=
01, in step P ₅ , step P ₃
ACK to flag F ₁ indicating the NS set and output in
Determine whether =01 corresponds. Now step
Flag F ₁ at initial setting in P ₁ indicates odd number

If it is [0] and ACK is [01] indicating an odd number, the correspondence between ACK and flag F ₁ is correct, so
A YES output is obtained from step _P5 , the transmission of the odd numbered data is completed, and the DF is temporarily turned off in step _P7 for the transmission of the second main data.

It is set to [0], and the contents of the flag _F1 , that is, the contents of NS, are inverted. That is, if flag _F1 is data indicating an odd number in step _P5 , step _P7
A flag F ₁ (NS=1) indicating an even number is set. When ACK=10 occurs from step _P4 ,
In step _P6 , it is determined whether ACK=10 corresponds to flag _F1 set in step _P3 . During the first (odd numbered) data transmission, flag F ₁ is

Since it is [0], it does not correspond to ACK = 10, which indicates an even numbered data, so the output is NO.If the flag _F1 of step _P3 is [1], which indicates an even numbered data, ACK = 10, so it generates a YES output and the next step P ₇
Move to. If ACK = 00 or 11 is determined in step P ₄ , or if the outputs of steps P ₅ and P ₆ are NO, this indicates an error or loss in data transmission, so proceed to step P ₄ . Return, wait for ACK for the second and subsequent data transmissions, and input
Decipher the contents of ACK. Then, when a correct ACK is obtained, the output of step _P5 or _P6 is YES.
, and transmission of the next main data begins. FIG. 6 is a flowchart showing the operation of the reception control section 12. First, flag _F2 is set in step _P11 . That is, from the second transmitting/receiving circuit 1b to the first
NS indicating the odd and even data to be sent to the transmitter/receiver circuit 1a is set. In the initial state, a flag F ₁ =NS (0) indicating the first (odd numbered) main data is set. next,
In step _P12 , it is determined whether the DF (data presence/absence signal) given from the frame separation circuit 9 is [1] indicating that data is present. If NO,
Wait until DF=1, and if [1]
YES and go to the next step _P13 . step
At _P13 , it is determined whether NS=1 or NS=0. If NS=0, _ACK =
01, if NS=1, ACK= at step _P15 .
10 is output to the frame synthesis circuit 6. Note that from the reception control section 12 to the frame synthesis circuit 6,
When an ACK is given and data transmission accompanied by this is performed once, the transmission/reception control unit 12
ACK is cleared to [00]. In step _P16 , the contents of NS obtained from the frame separation circuit 9 and the flag _F2 set in step _P11 or _P17 are
It is determined whether or not the contents match. For example, for receiving the first data, the step
Flag F ₂ indicates odd number at P ₁₁

[0], and the NS data of NS field _C2 in the received format is also

If it is [0], YES is output and reception is completed. That is, only when the parity error detection circuit 8 detects that there is no parity error, an NS is obtained from the frame separation circuit 9, and if this NS is correct, it means that there is no error after all, and reception is completed. Therefore, in the next step _P17 the flag
_F2 is inverted and preparations are made for reception of the second main data. Further, in step _P18 , the data in the receiving buffer memory 10 is outputted, and then the process returns to step _P12 . In addition, in step _P12
If a NO output is obtained because NS and flag _F2 do not match, this means that data to be discarded has been input, and the process returns to step _P12 . [Modifications] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example. (a) It is also applicable when using CRC as error check data. (b) Transmission control section 11 and reception control section 12 are connected to a common
It may also be configured to use a CPU. (c) It is also applicable to data transmission between terminal devices. (d) It is also applicable when the transmission circuit 2 is configured as a time division multiplexing, frequency multiplexing, or other type of transmission circuit. [Effects of the Invention] As is clear from the above, according to the present invention, even if an error occurs in transmission, the reduction in transmission efficiency is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transmission system according to an embodiment of the present invention, FIG. 2 is a diagram showing the format of a unit frame, FIG. 3 is a diagram showing data exchange when there is no transmission error, and FIG. Figure 4 is a diagram showing the exchange of data when there is a transmission error, Figure 5 is a flowchart showing the operation procedure of the transmission control section, and Figure 6 is a diagram showing the exchange of data in the case of a transmission error.
Figure 7 is a flowchart showing the operation procedure of the reception control unit, Figure 7 is a diagram showing data exchange when there is no error in the conventional standby type ARQ method, and Figure 8 is a diagram showing the conventional standby type ARQ method.
FIG. 9 is a diagram showing data exchange when an error occurs in the ARQ method. FIG. 9 is a diagram showing data exchange when data is lost in the conventional standby ARQ method. 1a...First transmitting/receiving circuit, 1b...Second transmitting/receiving circuit, 2...Transmission circuit, 5...Transmission buffer memory, 6...Frame synthesis circuit, 7...Parity addition circuit, 8...Parity error detection circuit, 9
... Frame separation circuit, 10 ... Reception buffer memory, 11 ... Transmission control section, 12 ... Reception control section.

Claims (1)

[Claims] 1. A first frame including first main data, error check data, and identification data of the first main data is sent from a first transmitting/receiving circuit to a second transmitting/receiving circuit in frame units. repeating the transmission a plurality of times; receiving the first frame in the second transmitting/receiving circuit; and using the error check data to determine whether the first main data has been received without error; If the determination confirms that the first main data has been received without error, a response signal (ACK) corresponding to the identification signal is formed, and this response signal (ACK) is transmitted to the first main data. transmits to the transmitter/receiver circuit of
and discarding the first main data received by the second transmitting/receiving circuit after this, and extracting only one error-free first main data as valid data; detecting a signal (ACK); when the response signal (ACK) is detected, stopping the transmission of the first frame from the first transmitting/receiving circuit to the second transmitting/receiving circuit; repeatedly transmitting a second frame including data, error check data, and identification data of the second main data from the first transmitting/receiving circuit to the second transmitting/receiving circuit in frame units a plurality of times; Determination of reception error of the second main data, formation, transmission, and detection of a response signal (ACK) corresponding to the second main data are performed in the same manner as in the case of the first main data. data transmission method. 2. The first main data is odd-numbered data, the identification data of the first main data is data indicating odd-numbered data, and the response signal corresponding to the first main data is a response indicating odd-numbered data. is a signal,
The second main data is even-numbered data,
The data transmission system according to claim 1, wherein the identification data of the second main data is data indicating an even number, and the response signal corresponding to the second main data is a response signal indicating an even number. .