CN110635985A - FlexRay-CPCIe communication module - Google Patents
FlexRay-CPCIe communication module Download PDFInfo
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- CN110635985A CN110635985A CN201911105902.0A CN201911105902A CN110635985A CN 110635985 A CN110635985 A CN 110635985A CN 201911105902 A CN201911105902 A CN 201911105902A CN 110635985 A CN110635985 A CN 110635985A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
Abstract
The invention discloses a FlexRay-CPCIe communication module, which comprises: the system comprises an FPGA minimum system, a FlexRay bus communication unit and a CPCIe communication unit; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external communication bus network; the CPCIe communication unit executes PCIe bus standard to realize data exchange between the computer and the communication module; the FPGA minimum system is used as a bridge of a FlexRay communication protocol and a PCIe bus standard, and data exchange between a PCIe system bus and a FlexRay high-speed external bus is realized. The invention realizes the data exchange between two communication protocols of the computer through the PCIe system bus and the FlexRay high-speed external bus and develops, simulates and tests the FlexRay bus network based on the computer operating system.
Description
Technical Field
The invention belongs to the technical field of network communication, and relates to a FlexRay-CPCIe communication module which is used for realizing data communication between a computer and a FlexRay high-speed external bus through a PCIe system bus.
Background
Bus communication is widely applied to various industrial control networks, mainly aims to solve the problem of communication among different electronic devices, and is particularly embodied in the fields of aerospace, automobile manufacturing, navigation, automatic control, process industry and the like. At present, the external bus communication technology with long application time and mature technical development comprises a CAN bus, a 1553B bus and the like, and has the characteristics of high reliability, high certainty, high fault tolerance and the like. However, with the continuous development of scientific technology, the increasing data volume and the higher real-time communication requirement have gradually challenged the conventional external bus communication technology, and a new generation of high-speed external bus technology FlexRay bus is beginning to be applied in the related field.
As a new generation high-speed serial external bus protocol, FlexRay has obvious advantages in the aspects of communication speed/reliability, flexibility and the like compared with the traditional bus. The FlexRay bus is only applied to vehicle-mounted bus communication networks of a few brands at present, and has a great application prospect. Compared with the data transmission rate of 1Mbps highest for the CAN bus and the 1553B bus, the data transmission rate of a single channel of the FlexRay bus supports 10Mbps highest, and the total transmission rate of the two channels CAN reach 20Mbps highest, so that the communication requirements of large data volume and high real-time performance CAN be met; the two channels can realize three working modes of single-channel working, double-channel working and redundant working. In addition, the FlexRay bus network has flexible topological structure and supports various structures such as point-to-point, bus type, active star type and the like. In the aspect of a communication mechanism, a FlexRay bus adopts cycle communication, a data frame is supported to 254 frames at most, and a receiving node can be ensured to predict the arrival time of a message in advance by reasonably configuring a communication cycle and the message length.
In a system bus communication network, a third generation I/O bus-PCIe bus gradually replaces a second generation I/O bus-PCI bus technology due to its characteristics of supporting serial differential transmission, flexible bandwidth, high transmission rate, and the like, and is widely applied to a computer backplane interface to implement data communication among a CPU, a memory, and other board cards. Compared with the common PCIe interface, the CPCIe interface is more widely applied to the fields of military industry, measurement and control, aerospace and the like due to the characteristics of strong electromagnetic compatibility, good oxidation resistance and the like. Because computers have the advantages of human-computer interactivity, strong system operability and the like, the computers are generally used as upper computers or network nodes to take charge of receiving and sending commands and collecting and monitoring data. The communication between the board cards or the board cards and the computer is realized by installing the board cards with different functions on a computer backboard with a CPCIe interface. When the computer needs to communicate with an external bus, a bus communication module based on a CPCIe interface is added in the case aiming at a specific external communication bus protocol.
However, the two communication protocols of the PCIe system bus and the FlexRay high-speed external bus are not compatible with each other, which restricts the application range of the FlexRay high-speed bus while the computer functions in the FlexRay bus communication network.
Disclosure of Invention
Objects of the invention
The purpose of the invention is: aiming at the problem that two communication protocols of a PCIe system bus and a FlexRay high-speed external bus are incompatible with each other, a FlexRay-CPCIe communication module is provided, and the functions of taking a computer as an upper computer or a network node, communicating with the FlexRay bus, receiving and sending commands to the FlexRay high-speed bus, and collecting and monitoring data are realized.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a FlexRay-CPCIe communication module, comprising: the system comprises an FPGA minimum system, a power circuit unit, a FlexRay bus communication unit and a CPCIe communication unit; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external communication bus network; the CPCIe communication unit executes PCIe bus standard to realize data exchange between the computer and the communication module; the FPGA minimum system is used as a bridge of a FlexRay communication protocol and a PCIe bus standard, and data exchange between a PCIe system bus and a FlexRay high-speed external bus is realized; the power circuit unit supplies power to each unit of the communication module; the communication module is arranged on a CPCIe back plate in a computer case, and the functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.
The FPGA minimum system comprises an FPGA chip, and a clock circuit, a configuration interface and a program storage chip which are connected with the FPGA chip, wherein the FPGA chip adopts an XC6SLX100 chip of spark-6 series of Xilinx company, and the chip is provided with 338 user-defined I/O pin interfaces and a plurality of configuration modes; the clock circuit adopts an external crystal oscillator; the configuration interface simultaneously meets a debugging JTAG mode and a bit peripheral interface BPI mode; the program storage chip adopts a StrataFlash chip.
The FlexRay bus communication unit adopts a FlexRay bus node framework of a communication controller and bus drivers, and comprises the communication controller and the two bus drivers respectively; the communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080; the CPCIe communication unit is connected with the FPGA by adopting a bridging chip of PCIe bus protocol, and the bridging chip adopts PEX 8311.
The CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a CPCIe quasi interface, so that data transmission between the communication module and the computer is realized.
The FPGA and the MFR4310 are connected in an asynchronous memory interface mode and comprise a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal and a reset signal, and the MFR4310 and TJA1080 are connected with a receiving/transmitting enable signal through data signals; the FPGA and the PEX8311 adopt a C mode, and the connecting signals comprise a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal, an operation completion signal, a local bus application signal, a local bus use response signal, a bus access effective address starting signal and a bus access last bit transmission signal.
The power supply module adopts a multi-output DC/DC chip and provides power supply requirements for a FlexRay bus communication unit, a CPCIe communication unit and an FPGA minimum system.
Wherein the FPGA is powered by 1.2V, 1.5V and 3.3V, MFR4310 and PEX8311 are powered by 3.3V, and TJA1080 is powered by 5V.
The FPGA chip comprises a clock management module, a FlexRay data transceiver module and a CPCIe data transceiver module; in the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA through a global clock pin; the FlexRay data transceiver module comprises a FlexRay protocol control module, a channel control module, an interrupt interface module and a data cache module which are compiled by Verilog language; the CPCIe data transceiver module comprises a PCIe protocol control module, an interrupt interface module and a data cache module which are written by verilog language.
The FlexRay protocol control module completes initialization configuration and protocol operation configuration, the initialization configuration comprises FlexRay global parameters and communication mode setting, and the protocol operation configuration comprises conversion and control of each state in the FlexRay communication process; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.
The CPCIe protocol control module completes initialization configuration and data transmission and protection; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the sending and receiving of PCIe data.
(III) advantageous effects
The FlexRay-CPCIe communication module provided by the technical scheme can be freely installed in a CPCIe standard interface on a backboard of a computer case, the FPGA is used as a core processor of the module to realize the transceiving control of two buses, the exchange of data between two communication protocols of a computer through a PCIe system bus and a FlexRay high-speed external bus is realized, the development, simulation and test of a FlexRay bus network are further realized through an operating system based on the computer, and the convenience of the application of the FlexRay bus is improved.
Drawings
FIG. 1 is a schematic diagram of a FlexRay-CPCIe communication module of the present invention;
FIG. 2 is a schematic diagram of the FPGA minimal system of the present invention;
FIG. 3 is a schematic diagram of a FlexRay bus communication unit and a CPCIe communication unit according to the present invention;
FIG. 4 is a schematic diagram of a power module of the present invention;
FIG. 5 is a functional diagram of the internal logic of the FPGA of the present invention;
FIG. 6 is a functional diagram of the asynchronous FIFO logic of the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Fig. 1 is a schematic diagram of a FlexRay-CPCIe communication module according to the present invention, which includes an FPGA minimum system, a power circuit unit, a FlexRay bus communication unit, and a CPCIe communication unit; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external communication bus network; the CPCIe communication unit executes PCIe bus standard to realize data exchange between the computer and the communication module;
the core processor of the communication module adopts an FPGA minimum system, and the FPGA plays a role of a bridge for information exchange between two different communication protocols by designing an IP core in an FPGA chip, so that data exchange between a PCIe system bus and a FlexRay high-speed external bus is realized; and the power circuit unit supplies power to each unit of the communication module. The communication module can be arranged on a CPCIe back plate in a computer case, so that the functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.
FIG. 2 is a schematic diagram of the minimum system of the FPGA of the present invention. The FPGA minimum system comprises an FPGA chip, a clock circuit, a configuration interface and a program storage chip. The FPGA chip adopts XC6SLX100 chips of spark-6 series of Xilinx company, and the chip has up to 338 user-defined I/O pin interfaces and various configuration modes, so that the design flexibility is improved; the clock adopts a high-precision external crystal oscillator; in order to enhance the configuration efficiency of the FPGA chip, the configuration interface can simultaneously meet a debugging action group (JTAG) mode and a Bit Peripheral Interface (BPI) mode; the program storage chip adopts a StrataFlash chip.
Fig. 3 is a schematic diagram of a FlexRay bus communication unit and a CPCIe communication unit according to the present invention. The FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and bus drivers, and comprises the communication controller and the two bus drivers respectively. The communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080; the CPCIe communication unit is connected with the FPGA by adopting a bridging chip of PCIe bus protocol, and the bridging chip adopts PEX 8311.
The CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a CPCIe quasi interface, so that data transmission between the communication module and the computer is realized.
The FPGA and the MFR4310 are connected in an Asynchronous Memory Interface (AMI) mode and comprise a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal and a reset signal, and the MFR4310 and the TJA1080 are connected with a receiving/sending enable signal through the data signal; the FPGA and the PEX8311 adopt a C mode (the data line and the address line of a local bus are not multiplexed) design, and connection signals mainly comprise clock signals, data signals, address signals, read/write enable signals, interrupt signals, operation completion signals, application use local bus signals, local bus use response signals, start signals of effective addresses of bus access and transmission signals of the last bit of bus access.
Fig. 4 is a schematic diagram of a power module of the present invention, which uses a multi-output DC/DC chip to provide power supply requirements for a FlexRay bus communication unit, a CPCIe communication unit, and a minimum FPGA system. The FPGA is powered by 1.2V, 1.5V and 3.3V, MFR4310 and PEX8311 are powered by 3.3V, and TJA1080 is powered by 5V.
Fig. 5 is a functional diagram of the internal logic of the FPGA of the present invention, which is composed of a clock management module, a FlexRay data transceiver module, and a CPCIe data transceiver module.
In the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA from a special global clock pin (GCLK). In order to improve the driving capability of the clock signal, a global clock buffer (IBUFG) is needed first. In order to ensure clock precision, a clock management module (DCM) is used for adjusting the frequency of a clock signal output by the IBUFG, the output of the DCM is connected to a global Buffer (BUFG), and a stable single-ended clock signal is obtained and is used for being called by a FlexRay data transceiver module and a CPCIe data transceiver module.
The FlexRay data transceiver module comprises a FlexRay protocol control module written by Verilog language, a channel control module, an interrupt interface module and a data cache module. The FlexRay protocol control module completes initialization configuration and protocol operation configuration, the initialization configuration comprises the setting of FlexRay global parameters and a communication mode, and the protocol operation configuration comprises the conversion and control of each state in the FlexRay communication process; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.
The CPCIe data transceiver module comprises a PCIe protocol control module, an interrupt interface module and a data cache module which are written by verilog language. The CPCIe protocol control module completes initialization configuration and data transmission and protection; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the sending and receiving of PCIe data.
FIG. 6 is a functional diagram of the asynchronous FIFO logic of the present invention. Due to the fact that clock rates of the FlexRay data transceiver module and the CPCIe data transceiver module are different, in order to avoid data loss, an asynchronous FIFO is adopted in the FPGA for caching data. The asynchronous FIFO mainly comprises a double-port RAM, a read/write address generator and an empty/full signal generator. And for the FlexRay data transceiver module and the CPCIe data transceiver module, the working modes of asynchronous FIFO are consistent. The transmission of the signal is controlled by a write clock and write enable (transmission enable), and when the non-full signal is valid, transmission data and an address are written into the RAM; the data and address are then sent to the corresponding communication protocol, controlled by the read clock and read enable (communication protocol receive enable). The receiving of the signal is controlled by a write clock and a write enable (communication protocol transmission enable), and when the non-full signal is effective, the received data and the address are written into the RAM; then controlled by the read clock and read enable (receive enable), extracts the data and address, and performs the subsequent operations.
According to the technical scheme, the FPGA minimum system serves as a core processor of the communication module to respectively control the PCIe bus protocol bridge chip and the FlexRay communication controller chip, data of the FlexRay bus are processed by the FPGA and then are sent to a computer through the CPCIe communication unit, and meanwhile, commands issued by the computer are sent to a designated terminal on the bus through the CPCIe communication unit and the FlexRay bus after being processed by the FPGA. The functions of receiving and sending commands to the FlexRay high-speed bus, and collecting and monitoring data by using the computer as an upper computer or a network node are realized.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A FlexRay-CPCIe communications module, comprising: the system comprises an FPGA minimum system, a power circuit unit, a FlexRay bus communication unit and a CPCIe communication unit; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external communication bus network; the CPCIe communication unit executes PCIe bus standard to realize data exchange between the computer and the communication module; the FPGA minimum system is used as a bridge of a FlexRay communication protocol and a PCIe bus standard, and data exchange between a PCIe system bus and a FlexRay high-speed external bus is realized; the power circuit unit supplies power to each unit of the communication module; the communication module is arranged on a CPCIe back plate in a computer case, and the functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.
2. The FlexRay-CPCIe communication module of claim 1, wherein the FPGA minimal system comprises an FPGA chip and a clock circuit, a configuration interface and a program storage chip connected thereto, the FPGA chip employs XC6SLX100 chip of Spartan-6 series from xilinx corporation, the chip has 338 user-defined I/O pin interfaces and a plurality of configuration modes; the clock circuit adopts an external crystal oscillator; the configuration interface simultaneously meets a debugging JTAG mode and a bit peripheral interface BPI mode; the program storage chip adopts a StrataFlash chip.
3. FlexRay-CPCIe communication module according to claim 2, wherein the FlexRay bus communication unit employs a FlexRay bus node framework of communication controllers and bus drivers, comprising one communication controller and two bus drivers, respectively; the communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080; the CPCIe communication unit is connected with the FPGA by adopting a bridging chip of PCIe bus protocol, and the bridging chip adopts PEX 8311.
4. The FlexRay-CPCIe communication module according to claim 3, wherein the CPCIe communication unit is connected with the CPCIe interface in the computer case by using a CPCIe quasi interface to realize data transmission between the communication module and the computer.
5. The FlexRay-CPCIe communication module according to claim 4, wherein the FPGA is connected with the MFR4310 by an asynchronous memory interface, and comprises a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal and a reset signal, and the MFR4310 and TJA1080 are connected with a receiving/transmitting enable signal by a data signal; the FPGA and the PEX8311 adopt a C mode, and the connecting signals comprise a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal, an operation completion signal, a local bus application signal, a local bus use response signal, a bus access effective address starting signal and a bus access last bit transmission signal.
6. The FlexRay-CPCIe communication module according to claim 5, wherein the power module employs a multi-output DC/DC chip to provide power supply requirements for the FlexRay bus communication unit, the CPCIe communication unit and the FPGA minimum system.
7. FlexRay-CPCIe communication module according to claim 6, characterised in that the FPGA is involved with 1.2V, 1.5V and 3.3V supply, MFR4310 and PEX8311 are 3.3V supply and TJA1080 is 5V supply.
8. The FlexRay-CPCIe communication module according to claim 7, wherein the FPGA chip comprises a clock management module, a FlexRay data transceiver module and a CPCIe data transceiver module; in the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA through a global clock pin; the FlexRay data transceiver module comprises a FlexRay protocol control module, a channel control module, an interrupt interface module and a data cache module which are compiled by Verilog language; the CPCIe data transceiver module comprises a PCIe protocol control module, an interrupt interface module and a data cache module which are written by verilog language.
9. The FlexRay-CPCIe communication module according to claim 8, wherein the FlexRay protocol control module performs initialization configuration and protocol operation configuration, the initialization configuration includes setting of global parameters of FlexRay and communication mode, the protocol operation configuration includes conversion and control of each state in the FlexRay communication process; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.
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| CN113676253A (en) * | 2021-09-18 | 2021-11-19 | 天津津航计算技术研究所 | FlexRay bus optical fiber communication module based on FPGA |
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| CN115550098B (en) * | 2022-09-16 | 2023-05-05 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
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