CN111723033A

CN111723033A - Multifunctional serial communication interface equipment and method thereof

Info

Publication number: CN111723033A
Application number: CN201910203033.9A
Authority: CN
Inventors: 叶焱枭
Original assignee: Huada Semiconductor Co ltd
Current assignee: Xiaohua Semiconductor Co.,Ltd.
Priority date: 2019-03-18
Filing date: 2019-03-18
Publication date: 2020-09-29

Abstract

According to the present invention, a multifunctional serial communication interface and a method thereof are provided. Wherein the multi-function serial communication interface includes a multi-function configuration register to selectively provide communication protocol data corresponding to a current communication protocol of the multi-function serial communication interface; and the multifunctional serial communication protocol controller is used for controlling the multifunctional serial communication interface to communicate according to the current communication protocol according to the communication protocol data from the multifunctional register.

Description

Multifunctional serial communication interface equipment and method thereof

Technical Field

The present invention relates to the field of communications, and in particular, to a multifunctional serial Communication interface (MSC) device and method thereof.

Background

In the field of communications, communication interfaces with single functions, such as Universal Asynchronous Receiver/transmitter (uart), Serial Peripheral Interface (SPI), Integrated Circuit bus (I-Integrated Circuit), are commonly used²C) Etc.). When the communication interface is needed to be used, only a few fixed communication interfaces can be used, and the flexibility is low.

Disclosure of Invention

An object of the present invention is to provide a multifunctional serial communication interface and method.

In accordance with one aspect of the present invention, a multi-function serial communication interface is provided, wherein the multi-function serial communication interface includes a multi-function configuration register for selectively providing communication protocol data corresponding to a current communication protocol of the multi-function serial communication interface; and the multifunctional serial communication protocol controller is used for controlling the multifunctional serial communication interface to communicate according to the current communication protocol according to the communication protocol data from the multifunctional register.

The multifunction serial communication interface according to the above aspect of the present invention, wherein the multifunction serial communication protocol controller includes a dedicated baud rate generator for dividing a clock corresponding to the current communication protocol according to the communication protocol data from the multifunction register to generate a clock-divided baud rate corresponding to the current communication protocol.

The multi-function serial communication interface according to any one of the above aspects of the present invention, wherein the multi-function serial communication protocol controller includes a plurality of controllers respectively corresponding to a plurality of communication protocols of the multi-function serial communication interface, and a controller corresponding to a current communication protocol among the plurality of controllers performs serial interface control corresponding to the current communication protocol according to the communication protocol data from the multi-function configuration register.

The multi-function serial communication interface according to any of the above aspects of the present invention, wherein said multi-function register supplies an enable signal and a configuration signal corresponding to a current communication protocol to a controller corresponding to a current communication protocol among said plurality of controllers to cause said controller to start said serial interface control corresponding to a current communication protocol.

The multi-function serial communication interface according to any of the above aspects of the present invention, wherein said dedicated baud rate generator sets a reload value corresponding to a current communication protocol according to said clock divided baud rate, and selects a dedicated baud rate according to said reload value.

The multifunctional serial communication interface according to any of the above aspects of the present invention, wherein said dedicated baud rate generator is further configured to divide said clock corresponding to the current communication protocol according to the selected dedicated baud rate to obtain the serial clock.

The multifunctional serial communication interface according to any of the above aspects of the present invention, wherein the plurality of controllers comprises a UART controller, a SPI controller and/or I²And C, a controller.

The multi-function serial communication interface according to any of the above aspects of the present invention, wherein the multi-function serial communication protocol controller further comprises a serial protocol state machine for obtaining serial transmission data and/or chip select transmission data of the SPI corresponding to the parallel transmission data according to the current communication protocol, according to serial interface control performed by the controller corresponding to the current communication protocol.

The multi-function serial communication interface according to any of the above aspects of the present invention, wherein said multi-function serial communication protocol controller further comprises a parallel input output controller for obtaining said parallel transmission data.

The multi-function serial communication interface according to any of the above aspects of the invention, wherein said multi-function serial communication protocol controller further comprises a serial input output controller for transmitting one or more of said serial transmission data, chip select transmission data of said SPI, and said serial clock.

The multifunctional serial communication interface according to any of the above aspects of the present invention, wherein said special baud rate generator comprises a reload counter for dividing a clock corresponding to a current communication protocol according to said reload value set by said special baud rate generator to obtain a special baud rate.

In accordance with one aspect of the present invention, there is provided a method for a multifunctional serial communications interface, comprising selectively providing communication protocol data corresponding to a current communication protocol of the multifunctional serial communications interface; and controlling the multifunctional serial communication interface to communicate according to the current communication protocol according to the data from the communication protocol.

The method according to the above aspect of the present invention further comprises dividing the clock corresponding to the current communication protocol according to the communication protocol data to generate a clock divided baud rate corresponding to the current communication protocol.

The method according to any one of the above aspects of the invention, further comprising performing serial interface control corresponding to a current communication protocol in accordance with the communication protocol data.

The method according to any of the above aspects of the invention, further comprising initiating the serial interface control corresponding to the current communication protocol in accordance with the enable signal and the configuration signal corresponding to the current communication protocol.

The method according to any of the above aspects of the invention further comprises setting a reload value corresponding to a current communication protocol based on the clock-divided baud rate, and selecting a dedicated baud rate based on the reload value.

The method according to any of the above aspects of the invention further comprises dividing said clock corresponding to the current communication protocol according to the selected dedicated baud rate to obtain the serial clock.

The method according to any one of the above aspects of the present invention further comprises obtaining serial transmission data and/or chip select transmission data of the SPI corresponding to the parallel transmission data according to the current communication protocol based on the serial interface control.

The method according to any of the above aspects of the invention, further comprising transmitting one or more of the serial transmit data, chip select transmit data of the SPI, and the serial clock.

The method according to any of the above aspects of the invention, further comprising dividing a clock corresponding to a current communication protocol according to the override value set by the dedicated baud rate generator to obtain the dedicated baud rate.

Drawings

FIG. 1 is a schematic block diagram of a multifunction serial protocol controller in accordance with one embodiment of the present invention;

FIG. 2 is a schematic block diagram of a dedicated baud rate generator according to one embodiment of the present invention;

FIG. 3 is a diagram illustrating bi-directional communication connections in UART mode 0 according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a bi-directional communication connection in UART mode 0 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a bi-directional communication flow according to one embodiment of the present invention;

FIG. 6 is a diagram illustrating a host/slave communication connection on a UART according to one embodiment of the present invention;

FIG. 7 is a schematic flow diagram of master/slave communication in accordance with one embodiment of the present invention;

FIG. 8 is a schematic block diagram of an SPI interface connection for bi-directional communication in accordance with one embodiment of the present invention;

FIG. 9 is a schematic flow chart diagram of bi-directional communication in SPI mode of operation in accordance with one embodiment of the present invention;

FIG. 10 shows a schematic diagram of a circuit I²A schematic diagram of a starting condition of the C bus;

FIG. 11 shows an embodiment of the present invention²A schematic diagram of a stop condition for the C bus;

FIG. 12 shows a schematic diagram of a circuit I²C, schematic diagram of the repeated starting condition of the bus;

FIG. 13 shows a diagram of I according to an embodiment of the present invention²C schematic diagram of an example of a communication flow;

FIG. 14 shows an embodiment of the present invention²C schematic diagram of an example of a communication flow; and

FIG. 15 shows a schematic diagram of a circuit I²C schematic diagram of an example of communication flow.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

According to one embodiment of the invention, the multifunctional serial communication interface can select any one of the following communication modes according to the setting of the working mode:

(1) UART0 (asynchronous standard serial interface)

(2) UART1 (asynchronous multiprocessor interface)

(3) SPI (Serial peripheral interface/clock synchronous communication)

(4)I²C(I²C bus interface

(5) Special baud rate module for generating clock and baud rate of serial port

(6) 1-3 waiting time can be inserted between the receiving and sending of continuous data in SPI

Table 1 shows an example of interface mode switching according to an embodiment of the present invention. In communication through each Serial communication interface, before starting communication, an interface operation Mode may be set using a Serial Mode Register (SMR) shown in table 1.

TABLE 1

FIG. 1 shows a schematic block diagram of one example of a multifunction serial interface 100 in accordance with one embodiment of the present invention. As shown in FIG. 1, the multi-function serial interface 100 may include a multi-function serial protocol controller 110 for selecting one interface operation mode from one or more interface operation modes, such as those described in Table 1 above, and an Input/Output (I/O) interface 130 for data transfer to and from the multi-function serial protocol controller 130²C) The controller 108 may include a chip select output, such as SPI.

The multi-function serial protocol controller 110 includes a bus interface 102, a multi-function configuration register 104, a baud rate controller 106, a parallel input output controller 108, a serial transmission protocol state machine 112, a serial output control 114, a serial input control 116, a UART module 118, an SPI module 120, and/or an I²And C a module 122. For example, the baud rate controller 106 may include a dedicated baud rate generator. Although a UART controller 118 is shown in FIG. 1,SPI controller 120, I²C-controller 122, which in other embodiments may also include control modules based on other communication protocols. The serial output control 114 and serial input control 116 may include chip select outputs of the SPI.

Referring to FIG. 1, a bus interface 102 may be used to connect the inputs and/or outputs of a bus and/or other modules. Multi-function configuration register 104 may be used to select a current communication protocol according to Table 1 above, e.g., multi-function configuration register 104 may provide an enable signal and/or a configuration signal corresponding to the selected communication protocol to a selected control module, UART controller 118, SPI controller 120, or I²C a controller 122. According to one embodiment, the enable signal and the configuration signal may refer to UART operation/SPI operation/I²C description of operation.

Fig. 2 illustrates an example of the dedicated baud rate generator 106 of fig. 1 in accordance with one embodiment of the present invention. According to one embodiment of the present invention, the dedicated baud rate generator 106 may include a baud rate generator register 202, a first multiplexer 206, a reload counter 208, first and second baud

rate count comparators

210 and 212, a controller 214, and/or a second multiplexer 216. For example, the baud rate generator register 202 may include a first register BRS1 and a second register BRS 0. The baud rate generator register 202 may be coupled to an Advanced Peripheral Bus (APB).

The first multiplexer 206 may multiplex the Peripheral Clock (PCLK) and the System Clock (SCLK) according to a counter external clock select bit (e.g., brs1.ext) set in the baud rate generator register 202 and selectively transmit to the reload counter 208. The reload counter 208 may use a clock clk (e.g., an external clock or an internal clock) from the first multiplexer 206 as an operating clock. The reload counter 208 may receive the baud rate coefficient 204 (timer reload value) from the baud rate generator register 202. The reload counter 208 may include a first counter register BGR1 and a second counter register BGR0 for dividing the operating clock clk of the first multiplexer 206 by a set value (e.g., a reload value) in the baud rate generator registers (BRS1 and BRS0) and outputting the divided result to the first and second baud

rate count comparators

210 and 212, respectively.

According to one embodiment, the first baud rate count comparator 210 may comprise an 1/2 baud rate count comparator. The second baud rate count comparator 212 may comprise a baud rate count comparator. The first baud rate count comparator 210 may compare the baud rate comparator count value (cnt data) with the 1/2 baud rate coefficient and generate a first comparison value Sel1 according to the comparison result. For example, if the baud rate comparator count value cnt _ data is equal to 1/2 baud rate coefficients, the first comparison value Sel1 may be a logic "1". The second baud rate count comparator 212 may compare the baud rate comparator count value (cnt data) with 0 and generate a second comparison value Sel0 according to the comparison result. For example, if the baud rate comparator count value cnt _ data is 0, the second comparison value Sel0 may be a logic "1". The first and second baud

rate count comparators

210 and 212 may output a first comparison value Sel1 and a second comparison value Sel0, respectively, to the controller 214. The second baud rate count comparator 212 may return the reload baud rate coefficient value to the reload counter 208.

The controller 214 may set the transmit clock (tclk) to-tclk (e.g., invert the input clock to generate a divided clock according to the reload value as described below) when Sel1 is 1 (e.g., cnt data is 1/2 baud rate coefficient), and set tclk to cinv (serial clock flip bit) when Sel0 is 1 (e.g., cnt data is 0). The controller 214 may transfer the derived clock tclk to the second multiplexer 216, and then the second multiplexer 216 multiplexes the transfer clock tclk or the system clock sclk for transfer to the serial protocol state machine 112 as t1 as shown in fig. 1. According to one embodiment, in the UART mode, the baud rate obtained by dividing the internal clock by the dedicated baud rate generator 106 (e.g., the reload counter 208) may be set to a 15-bit reload value in the baud rate generator register 202 (e.g., BRS1, BRS0) to select the baud rate. Each reload counter 208 may divide the internal clock by the set value. A clock source may be provided in the baud rate generator register 202 to select the internal clock (e.g., BRS1: EXT ═ 0).

For example, the special baud rate generator 106 (e.g., the reload counter 208) may use the external clock as a clock source for the reload counter 208 for the baud rate obtained by dividing the external clock. An external clock is input from a System Clock (SCLK) 232. After setting the 15-bit reload value in the baud rate generator register 202(BRS1 and BRS0), the baud rate can be selected. Each reload counter 208 overrides the external clock by the set value. A clock source is set, and an external clock and a baud rate generator clock (e.g., BRS1: EXT ═ 1) are selected for use.

According to another embodiment, in the SPI mode, the setting method of the dedicated baud rate generator in the master mode and the slave mode may be different for the selection of the baud rate of the SPI.

For example, in the host operation mode, the internal clock frequency is divided using the dedicated baud rate generator 106, and the divided frequency is selectively output. The dedicated baud rate generator 106 may provide, for example, two reload counters 208 for generating serial clocks for receive and transmit operations, respectively. The 15-bit reload value may be set by configuring the baud rate generator register 202(BRS1 and BRS 0). The internal clock frequency may be divided by the set override value to obtain the serial clock and output the serial clock to the serial protocol state machine 112 via the second multiplexer 216. For the slave mode of operation, the dedicated baud rate is disabled in the slave mode (e.g., CR: MSS ═ 1), the external clock may be input directly through the clock input pin SCK, and/or as an output to the serial protocol state machine 112 via the second multiplexer 216.

According to another embodiment, in I²In the C mode, the dedicated baud rate generator 106 (reload counter 208) may divide the baud rate obtained by the internal clock, and use the first and second baud rate generator registers (BRS1 and BRS0) to set the 15-bit reload value to select the baud rate. The reload counter 208 may divide the internal clock by the set value.

As shown in fig. 1, a parallel input output controller 108 may be connected to the bus interface 102 to obtain transmitted data and received data.

The serial transport protocol state machine 112 may derive control logic behavior to perform serial output and SPI chip select output of the transport data obtained by the parallel input output controller 108 according to the currently selected communication protocol.

The serial output control 114 and the serial input control 116 are used to obtain serial output data and serial input data, respectively, to input data and clock control outputs to the I/O port 130, respectively, and to control whether the output inputs are inverted.

UART controller 118, SPI controller 120, and I²C-controller 122 may receive respective enable signals and/or configuration signals from multi-function configuration register 104 to obtain control logic behavior.

As shown in FIG. 1, in one embodiment, multifunction configuration register 104 may selectively provide communication protocol data corresponding to a current communication protocol of the multifunction serial communication interface 100. The multi-function serial communication protocol controller 110 may control the multi-function serial communication interface 100 to communicate according to the current communication protocol based on the communication protocol data from the multi-function configuration register 104.

In one embodiment, the dedicated baud rate generator 106 is configured to divide the clock (internal or external) corresponding to the current communication protocol based on the communication protocol data from the multi-function configuration register 104 to generate a clock-divided baud rate corresponding to the current communication protocol.

According to one embodiment, the UART controller 118, the SPI controller 120 and the I²The controller of the C controller corresponding to the current communication protocol may perform serial interface control corresponding to the current communication protocol according to the communication protocol data from the multi-function configuration register 104.

In one embodiment, the multi-function configuration register 104 may provide the enable signal and the configuration signal corresponding to the current communication protocol to the one of the plurality of

controllers

118, 120, and 122 corresponding to the current communication protocol to cause the controller to initiate the serial interface control corresponding to the current communication protocol.

In one embodiment, the dedicated baud rate generator 106 may set an override value corresponding to the current communication protocol based on the clock divided baud rate and select the dedicated baud rate based on the override value.

In one embodiment, the dedicated baud rate generator 106 may divide the clock corresponding to the current communication protocol according to a selected dedicated baud rate to obtain a serial clock.

In one embodiment, the serial protocol state machine 112 may obtain serial transmission data and/or chip select transmission data of the SPI corresponding to the parallel transmission data according to the current communication protocol based on the serial interface control performed by the controller corresponding to the current communication protocol.

In one embodiment, the parallel input output controller 108 may be used to obtain parallel transfer data.

In one embodiment, the serial output controller 116 and the serial input controller 114 may control the output/input of one or more of the serial transmission data, the chip select transmission data of the SPI, and the serial clock, respectively, and may control the output/input to be inverted.

In one embodiment, the reload counter 208 may divide the clock corresponding to the current communication protocol according to the reload value set by the dedicated baud rate generator to obtain the dedicated baud rate.

In UART operation, one or more (asynchronous serial interface) functions may be implemented as shown in Table 2 below.

TABLE 2

In one embodiment, in UART mode, a UART register list as described in Table 3 below may be used.

TABLE 3

In one embodiment, the dedicated baud rate generator 106 may operate as follows. For example, the clock source of the UART transmission/reception may select an internal clock of the dedicated baud rate generator 106 (the reload counter 208) or an external clock input to the dedicated baud rate generator 106 (the reload counter 208). The dedicated baud rate generator 106 may select the baud rate as described below.

In one example, the dedicated baud rate generator 106 (reload counter 208) may divide the internal clock to obtain the baud rate. For example, a reload value of 15 bits may be set in the first and second baud rate generator registers BRS1 and BRS0 to select the baud rate. Each reload counter 208 (e.g., first counter register BGR1 and second counter register BGR0) may divide the internal clock by the set value to obtain the baud rate. A clock source may be provided to select an internal clock (e.g., BRS1: EXT ═ 0).

In another example, the dedicated baud rate generator 106 (reload counter 208) may divide the frequency of the external clock to obtain the baud rate. For example, an external clock may be used as a clock source for reload counter 208. For example, an external clock may be input from SCLK 232. A 15-bit override value may be set in the first and second baud rate generator registers BRS1 and BRS0 to select the baud rate. Each reload counter 208 (e.g., first and second counter registers BGR1 and BGR0) may divide the external clock by the set value to obtain the baud rate. A clock source may be provided to select the use of an external clock and a baud rate generator clock (e.g., BRS1: EXT ═ 1). In one embodiment, the mode may be used in the case of a non-standard frequency oscillator.

If the external clock is selected (BRS1: EXT ═ 1), the reload counter 208 may be paused (BGR1/0 ═ 15' h 00). If the external clock is selected (BRS1: EXT ═ 1), its HIGH (HIGH) level and LOW (LOW) level may be at least two bus clock wide.

According to one embodiment, the dedicated baud rate generator 106 may calculate the baud rate as described below. For example, baud rate generator registers 202(BRS1 and BRS0) may be used to set a 15-bit reload counter.

In one embodiment, the reload value may be represented by the following formula (1):

v phi/b-1 formula (1)

Where V denotes a reload value, b denotes a baud rate, and phi denotes a bus clock frequency or an external clock frequency.

For example, if the bus clock is a 16MHz internal clock, the baud rate is set to 19200bps, and the reload value may be set as: v ═ 832 (16 × 1000000)/19200-1 ═ 832, then the actual (current) baud rate is: the baud rate (calculated) (16 × 1000000)/(832+1) 19218 (bps).

If a 20MHz bus clock and a 153600bps baud rate are set, the reload value may be set as: when V is (20 × 1000000)/153600-1 is 129, the baud rate (calculated) is (20 × 1000000)/(129+1) is 153846 (bps).

The baud rate error can be calculated as follows:

error (%) ═ (count value-target value)/target value × 100 formula (2)

In one embodiment, if the reload value is set to "0," the reload counter is stopped. In another embodiment, if the reload value is an even number, the LOW level "L" within one period of the receiving serial clock is wider than the HIGH level ("H"). If the reload value is an odd number, the HIGH level and the LOW level of the serial clock are the same width.

In one embodiment, the reload value may be greater than 3, but in some embodiments, the data may not be received properly due to the baud rate error and the setting of the reload value. If the reload value is set to less than 3, the transmission can be improved in cooperation with the baud rate compensation function. For example, if the system frequency is 32KHz, for a baud rate of 9.6K, the accuracy of data transmission and reception can be realized by matching with the baud rate compensation function.

In yet another embodiment, in the case that the reloading value is larger than 3, the baud rate compensation function can be matched to obtain more accurate baud rate.

Table 4 below shows the corresponding reload and baud rate for each bus clock frequency (where the reload is the setting (decimal) of the BRS1/0 register and the error is the baud rate error (%):

TABLE 4

FIG. 3 shows an example of two Central Processing Units (CPUs) interconnected according to one embodiment of the present invention. In one embodiment, the multifunctional serial communication interface may enable a CPU to CPU connection in UART operating mode 0 (asynchronous normal mode). In UART operating mode 0, for example, two-way communication may be selected.

As shown in fig. 3, the first CPU 310 and the second CPU320 may perform bidirectional communication in the UART operating mode 0. The first CPU 310 may include one or more pins or ports, such as a Serial Output Terminal (SOT) 312, a Serial Input (SIN) 314, and/or a System Clock (SCK) 316. The second CPU320 may include a SOT 322, a SIN 324, and/or a SCK 326. In one embodiment, the first CPU 310 may be a master CPU and the second CPU320 may be a slave CPU, or vice versa.

The master CPU 310 may send data to the SIN pin 324 of the slave CPU320 via the SOT pin 312. The slave CPU320 may send data to the master CPU 310 via the SOT pin 312 and the master CPU 310 may receive data from the slave CPU320 via the SIN pin 314.

One example of a CPU pin is shown in fig. 3, and other embodiments may include other pin arrangements. Further, other embodiments may also include multiple master CPUs and/or multiple slave CPUs.

In one embodiment, the bi-directional communication connection disables flow control in the UART operating mode 0 shown in FIG. 3. Fig. 4 shows an example of a bi-directional communication connection in UART mode 0 with flow control according to an embodiment of the invention.

As shown in fig. 4, the first CPU410 and the second CPU430 can perform bidirectional communication in the UART operating mode 0. The first CPU410 and the second CPU430 may include one or more pins or ports, such as a Master Output Slave Input (MOSI), a Master Input Slave Output (MISO), an SCK, a Clear To Send (CTS), and/or a Request To Send (RTS)). In one embodiment, first CPU410 may be a master CPU and second CPU 420 may be a slave CPU, or vice versa.

As shown in fig. 4, master CPU410 may send data to slave CPU430 via MOSI pin 412 and receive data from slave CPU430 via MISO pin 414. Master CPU410 may send data to CTS pin 438 of slave CPU430 via RTS pin 420 and receive data from slave CPU430 via CTS pin 418. Similarly, the slave CPU430 may send data to the master CPU410 via the MOSI pin 432 and receive data from the master CPU410 via the MISO pin 434. Slave CPU430 may send data to CTS pin 418 of master CPU410 via RTS pin 440 and receive data from master CPU410 via CTS pin 438.

One example of a CPU pin is shown in fig. 4, and other embodiments may include other pin arrangements.

Fig. 5 shows an example of bi-directional communication in UART mode 0 according to an embodiment of the present invention. For example, the flowchart shown in fig. 5 may utilize the example of the bi-directional communication connection in the UART operating mode 0 shown in fig. 3 or 4.

As shown in fig. 5, at block 502, the first CPU at the transmitting end may set an operation mode, such as UART mode 0. At block 512, the second CPU at the receiving end may set the corresponding operating mode such that its operating mode matches the setting of the transmit test, e.g., the second CPU may set the operating mode to UART mode 0.

At block 504, the first CPU may set the first data, e.g., 1 byte, in a transmit data register (TXDR) and initiate communication to transmit the first data to the second CPU. If the first data sent by the first CPU from the transmitting end is received, the second CPU at the receiving end may determine that RDEF is equal to 1 (decision block 514). If the second CPU determines that the received data full flag bit (RDFF) is 1, the first data received is read and processed (block 516). At block 518, the second CPU sends the second data (ANS), e.g., 1 byte, to the first CPU and returns to decision block 514 to determine whether data from the first CPU was received via RDFF. Conversely, if the second CPU determines at decision block 514 that RDFF is not equal to 1 (the first data from the first CPU was not received), the second CPU continues to determine at decision block 514 whether RDFF is equal to 1 until the first data is received.

At decision block 506, if the second data is received from the second CPU, the first CPU reads and processes the received second data (block 508) and returns to block 504 to continue sending data to the second CPU.

Conversely, if it is determined at decision block 506 that RDFF is not equal to 1, e.g., no second data (ANS) is received from the second CPU, the first CPU continues the determination of RDFF at decision block 906 until RDFF is determined to be 1 (second data received from the second CPU).

Fig. 6 shows an example of communication connection in UART operation mode 1 (asynchronous multiprocessing mode) according to an embodiment of the present invention. For example, in the master/slave communication shown in fig. 6, the communication system may be configured with first and second

common communication lines

630 and 640 to connect with the master CPU 610 and one or more slave CPUs 620A/620B and the like. In one embodiment, the UART may function as a master or slave.

Master CPU 610 may send data from first common communication line 630 to MISO pins 624A/624B of slave CPUs 620A/620B, respectively, via MOSI pin 312. The slave CPUs 620A/620B can send data from the second common communication line 640 to the master CPU 610 via MOSI pins 622A/622B, respectively, and the master CPU 610 can receive data from the slave CPUs 620A/620B via MISO pin 614.

One example of a CPU pin is shown in fig. 6, and other embodiments may include other pin arrangements. Further, other embodiments may also include multiple master CPUs and/or multiple slave CPUs.

In one embodiment, in UART mode 1, master/slave function selection may be performed as described in Table 5. Table 5 shows the selection of communication functions, such as operating mode and/or data transmission system selection, in the master/slave communication.

TABLE 5

In one embodiment, in UART mode of operation 1, transmit/receive data (TXDR/RXDR) operates in a word access mode.

Fig. 7 shows an example of communication in the UART operation mode 1 (multiprocessor mode) according to an embodiment of the present invention. In one embodiment, the communication is initiated when the host CPU sends address data. The address data is a data set with D8 bit 1, and is used for selecting a slave CPU for communication. Each slave CPU judges an address according to fig. 7, and if the address matches the assigned address, communicates with the master CPU.

As shown in fig. 7, at block 702, the master CPU may set an operating mode, such as UART mode 1. At block 732, the slave CPU may set the corresponding operating mode to match its operating mode with the operating mode of the master CPU, e.g., the slave CPU may set the operating mode to UART mode 1.

At block 704, the master CPU may set the MISO pin as a serial data input and the MOSI pin as a serial data output. At block 706, the master CPU may set the 7 or 8 bit data bit and set the 1 or 2 bit stop bit. At block 708, the master CPU may set the D8 bit to "1". At block 710, the master CPU may enable transmit/receive operations. At block 712, the master CPU may communicate the slave address to the slave CPU.

At block 734, the slave CPU may set the MISO pin as a serial data input. At block 736, the slave CPU may set the 7 or 8 bit data bit and set the 1 or 2 bit stop bit. At block 738, the slave CPU enables the transmit/receive operation. The slave CPU receives the master CPU transmitted byte at block 740 and determines whether the D8 bit of the received byte is 1 at decision block 742. If the slave CPU determines that the D8 bit is a "1," then at decision block 744 it is determined whether the slave address from the master CPU matches its own assigned address. Conversely, if the slave CPU determines at decision block 742 that the D8 bit is not a "1," the slave CPU returns to block 740 to continue receiving slave addresses from the master CPU and determines at decision block 744 whether the slave addresses match. If it is determined at decision block 744 that the slave address from the master CPU matches its assigned address, the slave CPU sets the MOSI pin to serial data output at block 746. Otherwise, the slave CPU returns to block 738.

After transmitting the slave address, the master CPU may set D8 to "0" at block 714. At block 716, the master CPU communicates with the slave CPU whose address matches. Accordingly, at block 748, the slave CPU communicates with the master CPU. Until it is determined at decision blocks 718 and 750 that the communication is complete. If the communication is not complete, the master CPU and slave CPU return to

blocks

716 and 748, respectively, to continue the communication.

If the master CPU determines at decision block 718 that communication with the slave CPU is complete, the master CPU determines at decision block 720 whether the master CPU is in communication with other slave CPUs. If a determination is made to communicate with other slave CPUs, the master CPU disables transmit/receive operations at block 722 and returns to block 702 for communication with other slave CPUs. In contrast, if the master CPU determines not to communicate with other slave CPUs at decision block 720, the master CPU ends the operation, thereby completing the communication.

According to another embodiment of the present invention, the multi-function serial communication interface may implement SPI operation. Table 6 shows an example of the SPI function.

TABLE 6

Table 7 shows an example of a list of SPI registers, according to one embodiment.

TABLE 7

In one embodiment, the dedicated baud rate generator in the SPI mode of operation is only active in the host mode. For the SPI baud rate selection, the setting method of the dedicated baud rate generator in the master mode and the slave mode is different.

In one example, in the host mode of operation, the internal clock frequency may be divided down using the dedicated baud rate generator 106 and the division selected output.

The dedicated baud rate generator 106 may provide two reload counters 208 to generate serial clocks for receive and transmit operations, respectively. The 15-bit reload value may be set by configuring the baud rate generator registers (BRS1 and BRS 0). The internal clock frequency can be divided by the set heavy duty value to obtain the serial clock frequency.

In another example, in the slave mode of operation, the dedicated baud rate is disabled in the slave mode (CR: MSS ═ 1) (e.g., the external clock may be directly input through the clock input pin SCK).

In accordance with one embodiment of the present invention, in SPI mode, two 15-bit reload counters 208 are set by baud rate generating registers (BRS1 and BRS 0).

In one embodiment, the reload value may be represented by the following equation (3):

v phi/b-1 formula (3)

Where V represents the reload value, b represents the baud rate, and phi represents the bus frequency.

For example, if the bus clock is a 16MHz internal clock, the baud rate is set to 19200bps, and the reload value may be set as: when V is (16 × 1000000)/19200-1 is 832, the actual baud rate is: the baud rate (calculated) (16 × 1000000)/(832+1) 19218 (bps).

The baud rate error can be calculated as follows:

error (%) ═ (count value-target value)/target value × 100 formula (4)

In one embodiment, if the reload value is set to "0," the reload counter is stopped. In another embodiment, if the reload value is an even number, the width of the low level "L" and the width of the high level "H" of the serial clock are related to the settings of MR: CINV and CR: SPIMODE. If the reload value is an odd number, the width of the high level "H" and the width of the low level "L" of the serial clock are the same.

When the serial clock detection level is at the high level "H" (MR: CINV ═ 0) in the no-chip select transmission mode (for example, CR: spiode ═ 0), or when the serial clock detection level is at the low level "L" (MR: CINV ═ 1) in the chip select transmission mode (CR: spiode ═ 1), the width of the high level "H" of the serial clock will be longer than the width of the low level "L" by 1 bus clock period.

When the serial clock detection level is at the low level "L" (MR: CINV ═ 1) in the no chip select transmission mode (CR: spiode ═ 0), or the serial clock detection level is at the high level "H" (MR: CINV ═ 0) in the chip select transmission mode (CR: spiode ═ 1), the width of the low level "L" of the serial clock will be 1 bus clock cycle longer than the width of the high level "H".

In another embodiment, the reload value is set to 3 or more. Table 8 shows the reload and baud rates for each bus clock frequency in SPI mode, according to an embodiment of the present invention.

TABLE 8

FIG. 8 shows an example of an SPI interface for bi-directional communication, according to one embodiment of the invention. The master CPU 810 and the slave CPU 820 may communicate bi-directionally in SPI mode of operation as shown in fig. 8. For example, master CPU 810 can send data to slave CPU 820 via MOSI pin 812 and receive data from slave CPU 820 via MISO pin 814. The master CPU 810 may send a clock signal 830 to the SCK pin 826 of the slave CPU 820 via the SCK pin 816.

One example of a CPU pin is shown in fig. 8, and other embodiments may include other pin arrangements. Further, other embodiments may also include multiple master CPUs and/or multiple slave CPUs.

FIG. 9 illustrates an example of bi-directional communication in SPI mode in accordance with an embodiment of the present invention. As shown in fig. 9, at block 902, a master CPU at the host end may set a mode of operation, such as SPI mode. At block 912, the slave CPU on the slave side may set the corresponding mode of operation to correspond to the mode of operation on the host side. For example, the slave CPU may set the operation mode to the SPI mode.

At block 904, the master CPU may write a first byte of data in a transmit data register (TXDR) and the communication begins. The master CPU sends the first byte of data to the slave CPU. If the first byte of data sent from the master CPU is received, the slave CPU may determine that RDEF is equal to 1 (decision block 914). If the slave CPU determines that RDFF is 1, the received first byte of data is read and processed (block 916). At block 918, the slave CPU sends a second data (ANS), e.g., 1 byte, to the master CPU and returns to decision block 914 to determine whether data from the master CPU is received via RDFF.

Conversely, if the slave CPU determines at decision block 914 that the RDFF is not equal to 1 (no first byte of data from the master CPU is received), the slave CPU continues to determine at decision block 914 whether the RDFF is equal to 1 until the first byte of data is received.

At decision block 906, if second data is received from the slave CPU, the master CPU determines RDFF is 1 to read and process the second data from the slave CPU at block 908 and returns to block 904 to continue sending data to the slave CPU.

In contrast, if it is determined at the decision block 906 that RDFF is not equal to 1, for example, the second data (ANS) from the slave CPU is not received, the master CPU continues the determination of RDFF at the decision block 906 until it is determined that RDFF is 1 (the second data from the slave CPU is received).

In accordance with yet another embodiment of the present invention, the multifunctional serial communication interface may implement I²And C, operation. Table 9 below shows I according to one embodiment of the present invention²An example of a C function.

TABLE 9

Table 10 below shows I according to one embodiment of the present invention²An example of a C register list.

Watch 10

According to one embodiment of the invention, a dedicated baud rate generator 106 may be used to set the serial clock frequency. For example, the selection of the baud rate may use the baud rate obtained by the dedicated baud rate generator 106 (reload counter 208) dividing the internal clock.

The 15-bit reload value may be set using first and second baud rate generator registers 1 and 0(BRS1/BRS0) to select the baud rate. The reload counter 208 may divide the internal clock by a set value.

In one embodiment, two registers (BRS1 and BRS0) may be utilized to set the baud rate setting of the 15-bit reload counter. For example, the weight value is calculated according to the following equation (5):

v phi/b-1 formula (5)

Where V represents the reload value, b represents the baud rate, and phi represents the bus clock frequency. In one embodiment, if at I²And C, if the rising edge time of the signal of the bus does not generate the preset baud rate, adjusting the heavy load value.

If the bus clock is 16MHz, the reloading value when the baud rate is 400bps is: v ═ 16 × 1000000)/400000-1 ═ 39, the actual baud rate is: b (16 × 1000000)/(39+1) 400 (bps).

For example, the baud rate generator register 1 and the baud rate generator register 0 are write-accessed in units of 16 bits (BRS1, BRS 0). The baud rate generator register is set when the slave mask enable bit (SAMSK: EN) of the slave address mask register (SAMSK) is "0". In I²In C mode, bus clock is not lower than 8MHz, and setting exceeding 400kbp is prohibiteds baud rate generator. When the reload value is "0", the reload counter stops working.

Table 11 shows the reload values and baud rates for each bus clock frequency.

TABLE 11

As shown in Table 11, the numerical value is I²The Serial Clock Line (SCL) of the C bus rises to 0 s. I is²When the serial clock line SCL of the C bus rises and delays, the baud rate is delayed than the above value. If not, it can be set with reference to equation (5).

In one embodiment, I²The C bus may include a Serial Data line (SDA) and a Serial clock line SCL. FIGS. 10-12 show I according to an embodiment of the invention²An example of a C bus operation. FIG. 10 shows I²An example of a start-up condition for the C bus. As shown in FIG. 10, if the serial data line 1010 transitions from high to low while the serial clock line 1020 is high (block 1030), I²And C, starting the bus.

FIG. 11 shows I²An example of a stop condition for the C bus. As shown in FIG. 11, if the serial data line 1010 transitions from low to high while the serial clock line 1020 is high (block 1130), I²The C bus is stopped.

FIG. 12 shows I²An example of a repetitive start condition for the C bus. As shown in FIG. 12, after the serial clock line 1020 sends out the acknowledge signal (ACK 1240) and the serial clock line 1020 transitions high, if the serial data line 1010 transitions from high to low (block 1230), I²The C bus is repeatedly started.

FIG. 13 shows a diagram illustrating I according to another embodiment of the present invention²An example of an operation flow. The CPU may execute I using the flow shown in FIG. 13²C bus operation. For example, fig. 13 may be applicable to the master mode.

As shown in fig. 13, in frame1302, the CPU may perform initial settings, such as Baud Rate (BRS), Slave Address (SA), slave mask setting (SAMSK), and/or I²C enable (SAMSK: EN ═ 1), and the like. At decision block 1304, the CPU may determine whether it is in master mode. If it is determined at decision block 1304 that it is not master mode, flow may proceed to slave mode (1400), such as shown in FIG. 14.

Conversely, if the master mode is determined at decision block 1304, then transmit data (TXDR) is written at block 1306 and/or the master mode is set (e.g., master slave select bits BCR: MSS ═ 1). At decision block 1308, the CPU may determine whether the interrupt flag clear bit (BCR: INTF) is 1. If it is determined at decision block 1308 that BCR INTF is not 1, then flow returns to decision block 1308. Conversely, if at decision block 1308 it is determined that BCR: INTF is 1, flow proceeds to decision block 1310. Referring to fig. 13, 14, and 15, the flow of fig. 14 or 15 may proceed from circle a (1420) to decision block 1308 shown in fig. 13.

At decision block 1310, the CPU may determine whether the bus error bit (BCR: BERF) is zero. If it is determined at decision block 1310 that BCR BERF is not zero, flow proceeds to block 1312. At block 1312, the CPU performs bus error handling and the flow ends. Conversely, if it is determined at decision block 1310 that BCR: BERF is 0, flow proceeds to decision block 1314 to determine whether the repeatedly-started set bit (BCR: OF ITS) is 1. At decision block 1314, if the CPU determines that BCR: OFITS is not 1, flow proceeds to block 1316 to perform arbitration loss processing, and flow ends. Conversely, if it is determined at decision block 1314 that BCR: OFITS is 1, flow proceeds to decision block 1318.

At decision block 1318, the CPU may determine whether the master slave select bit (BCR: MSS) is 1. If it is determined at decision block 1318 that the BCR MSS is not 1, flow proceeds to slave mode (1400). If instead it is determined at decision block 1318 that the BCR: MSS is 1, flow proceeds to decision block 1320. At decision block 1320, the CPU may determine whether the reserved address detection bit (IBSR: RAD) is zero. If it is determined at decision block 1320 that IBSR: RAD is not 0, flow proceeds to block 1322 to reserve the address. Conversely, if it is determined at decision block 1320 that IBSR: RAD is 0, flow proceeds to decision block 1324.

At decision block 1324, the CPU may determine whether the acknowledge flag bit (IBSR: ACKF) is 0. If it is determined at decision block 1324 that IBSR: ACKF is not 0, flow proceeds to decision block 1342 to determine whether to perform a repeat boot. Conversely, if it is determined at decision block 1324 that IBSR: ACKF is 0, flow proceeds to decision block 1326. At decision block 1326, the CPU may determine whether the data direction bit (IBSR: TRX) is 1. If it is determined at decision block 1326 that IBSR: TRX is not 1, flow proceeds to decision block 1332 to determine whether the repetitive start condition flag (BS: FBB) is 0. Conversely, if it is determined at decision block 1326 that IBSR: TRX is 0, flow proceeds to decision block 1328.

At decision block 1328, the CPU may determine whether the transmission is complete. If it is determined at decision block 1328 that the transmission is not complete, flow proceeds to decision block 1342 to determine whether to perform a reboot. If instead, at decision block 1328, it is determined that the transmission is complete, flow proceeds to block 1330. At block 1330, the CPU may perform write-send data (TXDR), wait-to-set (BCR: WTSEL), acknowledge ACK set (BCR: ACK), and/or interrupt flag clear (BCR: INTF ═ 0). Flow may then return to decision block 1308.

At decision block 1332, the CPU may determine whether the repetitive start condition bit (BS: FBB) is 0. If it is determined at decision block 1332 that FBB is not 0, flow proceeds to decision block 1336. Conversely, if it is determined at decision block 1332 that FBB is 0, the CPU may read the received data (RXDR) at block 1334. At decision block 1336, the CPU may determine whether the reception is complete. If it is determined at decision block 1336 that reception is not complete, the CPU may perform a wait setting (BCR: WTSEL ═ 1), an acknowledge ACK setting (BCR: ACK ═ 1), and/or an interrupt flag clear (BCR: INTF ═ 0) at block 1338. Flow then returns to decision block 1308. If, instead, it is determined at decision block 1336 that reception is complete (no acknowledgement (NACK)) then flow proceeds to block 1340.

In block 1340, the CPU may perform a wait setting (BCR: WTSEL) and/or an acknowledge ACK setting (BCR: ACK ═ 0). Flow then proceeds to decision block 1342. Referring to fig. 13 and 15, the flow of fig. 15 may proceed from circle B (1530) of fig. 15 to decision block 1342 of fig. 13. At decision block 1342, the CPU may determine whether to repeatedly boot. If it is determined at decision block 1342 that no iterative boot is to be performed, flow proceeds to block 1346. At block 1346, the CPU may perform a stop setting (BCR: MSS ═ 0), an acknowledge ACK setting (BCR: ACK), and/or an interrupt flag clear (BCR: INTF ═ 0). Then, the flow ends. If, instead, it is determined at decision block 1342 that an iterative boot is performed, flow proceeds to block 1344. At block 1344, the CPU may perform write transmit data, repeat start setting (BCR: MSS ═ 1), acknowledge ACK setting (BCR: ACK), and/or interrupt flag clear (BCR: INTF ═ 0). Flow then returns to decision block 1308.

FIG. 14 shows a diagram of I according to another embodiment of the present invention²An example of an operation flow. The CPU may execute I using the flow shown in FIG. 14²C bus operation. For example, fig. 14 may be applied to the slave mode of the CPU.

As shown in fig. 14, at block 1402, the CPU may execute a slave mode. At decision block 1404, the CPU may determine whether the reserved address detection bits (BSR: RAD) are zero. If it is determined in decision block 1404 that RAD is not zero, then flow proceeds to decision block 1422. Conversely, if it is determined at decision block 1404 that FBB is 1, then flow proceeds to decision block 1406.

At decision block 1406, the CPU may determine whether the data direction bit (BSR: TRX) is equal to 0. If it is determined at decision block 1406 that the BSR is such that TRX is not 0, flow proceeds to decision block 1414. Conversely, if it is determined at decision block 1406 that TRX is 0, then flow proceeds to decision block 1408.

At decision block 1408, the CPU may determine whether the toggle condition flag (BSR: FBB) is 0 if it is determined at decision block 1408 that the BSR: FBB is not 0, flow proceeds to block 1412. Conversely, if it is determined at decision block 1408 that FBB is 0, then flow proceeds to block 1410 to read the received data in the received data register (RXDR). Flow then proceeds to block 1412. At block 1412, the CPU may perform a wait setting (BCR: WTSEL), an acknowledge ACK setting (BCR: take), and/or clear an interrupt flag (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

At decision block 1414, the CPU may determine whether the acknowledge flag bit (BSR: ACKF) is 0. If it is determined at decision block 1414 that the BSR is ACKF not 0, flow proceeds to block 1418. At block 1418, the CPU may execute an interrupt flag clear (BCR: INTF ═ 0). Then, the flow ends. Conversely, if it is determined at decision block 1414 that the BSR: ACKF ═ 0, flow proceeds to block 1416. At block 1416, the CPU may perform a write to send data (send data register (TXDR)), wait setting (BCR: WTSEL), and/or interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

At decision block 1422, the CPU may determine whether the repeated start condition flag (BSR: FBB) is 1. if it is determined at decision block 1422 that the BSR: FBB is not 1, then flow proceeds to decision block 1426. Conversely, if it is determined at decision block 1422 that FBB is 1, then flow proceeds to block 1424 to read the received data in the received data register (RXDR). Flow then proceeds to decision block 1426.

At decision block 1426, the CPU may determine whether to perform a slave operation. If it is determined at decision block 1426 that no slave operation is to be performed, flow proceeds to block 1430 to perform ACK-ACK setting (BCR: ACK ═ 0) and/or clear interrupt flag (BCR: INTF ═ 0). Then, the flow ends. Conversely, if it is determined at decision block 1426 that a slaved operation is to be performed, flow proceeds to decision block 1428.

At decision block 1428, the CPU may determine whether the data direction bit (BSR: TRX) is 1. If it is determined at decision block 1428 that the BSR is that TRX is not 1, flow proceeds to decision block 1434. Conversely, if it is determined at decision block 1428 that the BSR: TRX ═ 1, flow proceeds to block 1432. At block 1432, the CPU may perform write-send data (TXDR), wait-to-set (BCR: WTSEL), acknowledge ACK setting (BCR: ACK ═ 0), and/or interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

At decision block 1434, the CPU may determine whether the repeatedly enabled conditional flag bit (BSR: FBB) is 1 if it is determined at decision block 1434 that the BSR: FBB is not 1, flow proceeds to block 1436 to read the received data in the received data register (RXDR). Conversely, if it is determined at decision block 1434 that FBB is 1, then flow proceeds to block 1438. At block 1438, the CPU may perform a wait setting (BCR: WTSEL), an acknowledge ACK setting (BCR: ACK ═ 1), and/or an interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

FIG. 15 shows a diagram of I according to another embodiment of the present invention²An example of an operation flow. The CPU may execute I using the flow shown in FIG. 15²C bus operation. For example, FIG. 15 may be applicable to a reserved address operation.

As shown in FIG. 15, at block 1502, the CPU may perform a reserve address operation. At decision block 1504, the CPU may determine whether the repetitive start conditional flag (BSR: FBB) is 1. If it is determined at decision block 1504 that FBB is not 1, flow proceeds to decision block 1512. Conversely, if it is determined at decision block 1504 that FBB is 1, then flow proceeds to decision block 1506.

At decision block 1506, the CPU may determine whether there are multiple master CPUs. If it is determined at decision block 1506 that there are no multiple master CPUs, flow proceeds to block 1510. At block 1510, the CPU may perform read receive data (RXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: ACK), and/or interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13. If, instead, it is determined at decision block 1506 that there are multiple master CPUs, flow proceeds to block 1508. At block 1508, the CPU may perform reading the received data (RXDR), wait setting (BCR: WTSEL), acknowledge ACK setting (BCR: ACK ═ 1), and/or clear the interrupt flag (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

At decision block 1512, the CPU may determine whether the data direction bit (BSR: TRX) is 1. If it is determined at decision block 1512 that TRX is not 1, flow proceeds to block 1524. Conversely, if it is determined at decision block 1512 that TRX is 1, then flow proceeds to decision block 1514.

At decision block 1514, the CPU may determine whether the received data full flag (SSR: RDFF) is 1 if it is determined at decision block 1514 that SSR: RDFF is not 1, then flow proceeds to decision block 1518. Conversely, if it is determined at decision block 1514 that RDFF is 1, flow proceeds to block 1516. At decision block 1516, the CPU may read the received data. Flow then proceeds to decision block 1518.

At decision block 1518, the CPU may determine whether the receive reply flag (BSR: RACK) is 0. If it is determined at decision block 1518 that the BSR: RACK is not 0, flow proceeds to circle A (1420) to perform the corresponding operations as shown in FIG. 13. Conversely, if it is determined at decision block 1518 that the BSR: RACK is 0, flow proceeds to decision block 1520.

At decision block 1520, the CPU may determine whether the transmission is complete. If it is determined at decision block 1520 that the transmission is complete, flow proceeds to circle B (1530) to perform the corresponding operations as shown in FIG. 13. Conversely, if it is determined at decision block 1518 that the transmission is not complete, flow proceeds to block 1522. At block 1522, the CPU may perform write-send data (TXDR), wait-to-set (BCR: WTSEL), acknowledge ACK setting (BCR: ACK ═ 0), and/or interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

At block 1524, the CPU may read the receive data (RXDR). Flow then proceeds to decision block 1526. At decision block 1526, the CPU may determine whether the transmission is complete. If it is determined at decision block 1526 that the transmission is complete (e.g., a no-acknowledgement (NACK) response is received), flow proceeds to block 1528 to perform a wait setting (BCR: WTSEL) and/or an acknowledgement ACK setting (BCR: ACK ═ 0). The flow then proceeds to circle B (1530) to perform the corresponding operations as shown in fig. 13. Conversely, if it is determined at decision block 1526 that the transmission is not complete, flow proceeds to block 1532 to perform a wait setting (BCR: WTSEL ═ 1), an acknowledge ACK setting (BCR: ACK ═ 1), and/or an interrupt flag clear (BCR: INTF ═ 0). Flow then proceeds to circle a (1420) to perform the corresponding operations as shown in fig. 13.

Flow scheme I of FIGS. 13-15²In other embodiments, error handling and the like may be taken into consideration in accordance with appropriate application requirements.

The multifunctional serial communication interface 100 may enable UART, SPI and I according to embodiments of the present invention²And C, serial port communication shares the same control logic and register setting. UART, SPI and I may be used at the same time²And C, a serial port communication mode is adopted, so that the serial port communication of the chip is more flexibly set.

Claims

1. A multi-function serial communication interface, said multi-function serial communication interface comprising a multi-function configuration register for selectively providing communication protocol data corresponding to a current communication protocol of said multi-function serial communication interface; the multifunctional serial communication protocol controller is used for controlling the multifunctional serial communication interface to communicate according to the current communication protocol according to the communication protocol data from the multifunctional register; the multi-function serial communication protocol controller includes a dedicated baud rate generator for dividing the frequency of the clock corresponding to the current communication protocol according to the communication protocol data from the multi-function register to generate a clock divided baud rate corresponding to the current communication protocol.

2. The multi-function serial communication interface of claim 1 wherein said multi-function serial communication protocol controller comprises a plurality of controllers corresponding to a plurality of communication protocols of said multi-function serial communication interface, respectively, a controller of said plurality of controllers corresponding to a current communication protocol performing serial interface control corresponding to the current communication protocol in accordance with said communication protocol data from the multi-function configuration register.

3. The multi-function serial communication interface of any of the preceding claims wherein said multi-function register provides an enable signal and a configuration signal corresponding to a current communication protocol to a controller of said plurality of controllers corresponding to the current communication protocol to cause said controller to initiate said serial interface control corresponding to the current communication protocol.

4. Multifunctional serial communication interface according to anyone of the preceding claims, characterized in that said dedicated baud rate generator is adapted to set a reload value corresponding to a current communication protocol based on said clock divide baud rate, and to select a dedicated baud rate based on said reload value and/or is further adapted to divide said clock corresponding to a current communication protocol based on said selected dedicated baud rate to obtain a serial clock.

5. Multifunctional serial communication interface according to one of the previous claims, characterised in that said plurality of controlsThe device comprises a UART controller, an SPI controller and/or I²And C, a controller.

6. A multifunctional serial communication interface according to any of the preceding claims, wherein said multifunctional serial communication protocol controller further comprises a serial protocol state machine for obtaining serial transmission data corresponding to parallel transmission data and/or chip select transmission data of SPI according to a current communication protocol, and/or a parallel input output controller for obtaining said parallel transmission data, and/or a serial input output controller for transmitting one or more of said serial transmission data, chip select transmission data of said SPI, and said serial clock, according to serial interface control performed by a controller corresponding to said current communication protocol.

7. The multifunctional serial communication interface of any of the previous claims, wherein said dedicated baud rate generator comprises a reload counter for dividing a clock corresponding to a current communication protocol according to said reload value set by said dedicated baud rate generator to obtain a dedicated baud rate.

8. A method for a multifunctional serial communication interface, comprising selectively providing communication protocol data corresponding to a current communication protocol of the multifunctional serial communication interface; controlling the multifunctional serial communication interface to communicate according to the current communication protocol according to the communication protocol data; and according to the communication protocol data, dividing the frequency of the clock corresponding to the current communication protocol to generate a clock division baud rate corresponding to the current communication protocol.

9. The method of claim 8, further comprising performing serial interface control corresponding to a current communication protocol in accordance with the communication protocol data and/or initiating the serial interface control corresponding to the current communication protocol in accordance with an enable signal and a configuration signal corresponding to the current communication protocol.

10. The method of claim 8 or 9, further comprising setting an override value corresponding to a current communication protocol based on the clock-divided baud rate, and selecting a dedicated baud rate based on the override value.

11. The method of any preceding claim, further comprising dividing the clock corresponding to the current communication protocol according to a selected dedicated baud rate to obtain a serial clock.

12. A method according to any one of the preceding claims, further comprising obtaining serial transmission data and/or chip select transmission data of the SPI corresponding to the parallel transmission data according to the current communication protocol, in accordance with the serial interface control.

13. A method as claimed in any preceding claim, further comprising transmitting one or more of the serial transmit data, chip select transmit data of the SPI and the serial clock.

14. The method of any preceding claim, further comprising dividing a clock corresponding to a current communication protocol by the override value set by the dedicated baud rate generator to obtain a dedicated baud rate.