KR20080013548A - Interface module and method for data communication by synchronizing clock - Google Patents

Abstract

An interface module and a method for synchronizing clock signals and transmitting and receiving data are provided to transmit and receive a control signal between components of the interface module in synchronization with operating clock signals of the components and stabilize data signals when the interface module exchanges the data signals in a slave mode. An interface module includes a transmission controller(211) and a transfer unit(240). The transmission controller operates in response to a first clock signal and outputs data inputted from a central processing unit. The transfer unit operates in response to a second clock signal and sequentially outputs data inputted from the transmission controller to a peripheral device. The transmission controller and the transfer unit respectively include synchronization units(411,241) for converting a control signal transmitted and received between the transmission controller and the transfer unit according to operating clock signals of the transmission controller and the transfer unit.

Description

Interface module and method for synchronizing clock to transmit and receive data

1 is an internal block diagram of an SPI according to the prior art.

2 is a block diagram reconstructing SPI exchanging data in slave mode.

3 is a synchronization unit using two general D-flip-flops.

4 is a diagram illustrating a configuration for transmitting data in a slave mode of an SPI according to an embodiment of the present invention;

5 is a flowchart illustrating a data transmission method of an SPI in a slave mode according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a configuration for transmitting data in a slave mode of an SPI according to an embodiment of the present invention.

7 is a flowchart illustrating a data receiving method of an SPI in a slave mode according to an exemplary embodiment of the present invention.

The present invention relates to an interface module, and more particularly, to an interface module for synchronizing a system clock and a serial clock (hereinafter, referred to as 'SCK') of an interface module.

Generally, Serial Perphal Interface (hereinafter referred to as 'SPI') is an interface that allows data to be exchanged between peripherals by serial communication, one of which becomes a master and the other of which is a master. Operates as a slave. SPI operates in full duplex, which means that data can be delivered in both directions simultaneously. Most SPIs are used in systems that communicate between a central processing unit (CPU) and peripherals, but it is also possible to connect two microprocessors in the form of SPIs. The term was originally coined by Motorola, and it is well known that other types perform similar but different names.

1 is an internal block diagram of an SPI according to the prior art.

Referring to FIG. 1, the clock used by the SPI is largely divided into two types. The first is the serial clock (Serial Clock, hereinafter referred to as 'internal clock' to distinguish it from the system clock) by which the SPI divides the system clock. The second is from the peripheral to the SCK pin on the control logic pin 106. An incoming clock (hereinafter referred to as a clock received from a peripheral device) is referred to as a peripheral clock.

SPI supports two modes, one in master mode and the other in slave mode.

Master mode uses the system clock to generate internal clocks, and exchanges data with external peripherals using internal clocks.

However, the slave mode does not generate a clock and exchanges data using a peripheral clock input from the peripheral device through the SCK pin of the control logic pin 106 from the peripheral device.

Accordingly, in the process of SPI exchanging data bidirectionally, there is a problem that the internal clock used by the master mode and the peripheral clock used in the slave mode may be asynchronous.

For example, if the system clock is 100hz, a delay may occur during the process of generating the internal clock by dividing the system clock in the master mode, and the internal clock may be 99hz due to various factors.

In addition, the peripheral device also operates at a system clock of 100 hz, but in reality, various delays may occur in the internal processing of the peripheral device, and various cracks and distortions may occur on the time axis. Therefore, in the slave mode, the peripheral clock of which the SPI is input to the SCK pin of the control logic pin 106 may be 97hz. As a result, the internal clock and the peripheral clock may be asynchronous.

When the internal clock and the peripheral clock are asynchronous while the SPI exchanges data between the central processing unit and the peripheral device, there is a problem that the data itself may become unstable.

In order to solve the conventional problems as described above, the present invention, in the slave mode (Slave mode) in the process of transmitting and receiving data between the peripheral device, the control signal transmitted and received between the components of the interface module according to each operation clock It proposes an interface module that is synchronized and transmitted and received.

In addition, the present invention proposes an interface module for stabilizing data in the process of exchanging data in slave mode.

Still other objects of the present invention will be readily understood through the following description of the embodiments.

In order to achieve the above object, according to a preferred embodiment of the present invention, the interface module for transmitting data from the central processing unit to the peripheral device in the slave mode, the operation corresponding to the first clock A transmission control unit for outputting data input from the central processing unit; And a transmission unit operating in correspondence with a second clock input from the peripheral device, and sequentially outputting data input from the transmission control unit to the peripheral device, wherein the transmission control unit and the transmission unit are controlled to be transmitted and received to each other. An interface module is provided that includes a synchronizer for converting signals in accordance with respective operating clocks.

The apparatus may further include a clock divider configured to generate the first clock using a system clock input from the CPU.

The apparatus may further include a register unit configured to convert m (arbitrary natural number) bit data input from the CPU to n (arbitrary natural number) bit data and output the n-bit data.

The apparatus may further include a first-in, first-out unit that stores the n-bit data input from the register unit and outputs the n-bit data to the transmission control unit in the stored order.

M may be a number corresponding to the operation bits of the CPU, and n may be a number corresponding to a data bus width between the interface module and the peripheral device.

The transfer unit may include: a multiplexer sequentially outputting data input from the transmission control unit to the peripheral device; A counter unit for generating a multiplexer enable signal for enabling the multiplexer; And a synchronization unit for synchronizing a control signal input from a control signal generation unit included in the transmission control unit to the second clock and transmitting the control signal to the counter unit, wherein the counter unit is configured to generate the multiplexer enable signal. Correspondingly, a flag signal may be generated and provided to the control signal generator.

The transmission control unit may further include a synchronization unit converting the flag signal according to the second clock to correspond to the first clock and providing the control signal to the control signal generator.

According to another aspect of the present invention, an interface module for receiving data from a peripheral device to a central processing unit in slave mode, the interface module operating in correspondence with a second clock input from the peripheral device, A transmission unit for outputting sequentially input data; And a reception control unit operating in correspondence with a first clock and outputting data input from the transmission unit to a central processing unit, wherein the reception control unit and the transmission unit transmit control signals transmitted and received to each other according to respective operation clocks. An interface module is provided that includes a synchronizer for converting.

The apparatus may further include a clock divider configured to generate the first clock using a system clock input from the CPU.

The apparatus may further include a first-in, first-out unit that stores data input from the reception control unit and outputs the data to the central processing unit in the stored order.

The apparatus may further include a register unit configured to convert n (arbitrary natural number) bit data inputted from the reception first-in / first-out unit into m (arbitrary natural number) bit data and output the m-bit arbitrary data.

N is a number corresponding to the data bus width between the interface module and the peripheral device, and m may be a number corresponding to the operation bit of the central processing unit.

The transfer unit includes a reception shift register for sequentially receiving data from the peripheral device and outputting the data; And a counter unit generating a flag signal corresponding to the number of bits received by the reception shift register and providing the flag signal to a control signal generator included in the reception control unit.

The reception control unit may further include a synchronization unit converting the flag signal according to the second clock to correspond to the first clock and providing the control signal to the control signal generator.

According to another aspect of the present invention, an interface method for transmitting data from a central processing unit to a peripheral device in a slave mode, the method comprising: (a) a transmission control unit operating in response to a first clock from the central processing unit; Outputting input data; (b) a transmission unit operating in correspondence with the second clock input from the peripheral device to sequentially output data input from the transmission control unit to the peripheral device, wherein the transmission control unit and the transmission unit transmit and receive mutually. An interface method is provided which converts a control signal to be corresponding to each operation clock.

(c) Generating the first clock using the system clock inputted from the CPU may be further performed before step (a).

(d) The step of converting the m (arbitrary natural number) bit data input from the central processing unit into n (arbitrary natural number) bit data and outputting to the transmission control unit may be further performed before step (a). have.

M may be a number corresponding to the operation bits of the CPU, and n may be a number corresponding to a data bus width to the peripheral device.

(e) The first-in, first-out of the transmission unit may store the n-bit data input from the register unit, and then output the data to the transmission control unit in the stored order between the step (d) and the step (a). .

Step (b) may include: (f) a multiplexer sequentially outputting data input from the transmission control unit to the peripheral device; (g) generating, by a counter unit, a multiplexer enable signal for enabling the multiplexer; And (h) synchronizing a control signal input from a control signal generation unit included in the transmission control unit with the second clock to the counter unit by a first synchronization unit; The counter unit may generate a flag signal corresponding to the number of generations of the multiplexer enable signal and provide the flag signal to the control signal generator.

(i) converting the flag signal according to the second clock into the second signal included in the transmission controller so as to correspond to the first clock, and inputting the flag signal to the control signal generator further after step (h); Can be.

According to another aspect of the invention, in the slave mode (Slave mode) interface method for receiving data from the peripheral device to the central processing unit, (a) a transfer unit operating in response to the second clock input from the peripheral device Outputting data sequentially input from the peripheral device; And (b) a reception control unit operating in correspondence with a first clock to output data input from the transfer unit to the central processing unit, wherein the reception control unit and the transfer unit transmit and receive control signals to and from each other. An interface method is provided which converts corresponding to each operation clock.

 (c) Generating the first clock using the system clock inputted from the CPU may be performed before step (a).

(d) The receiving first-in first-out unit may store data input from the receiving control unit and output the data to the midsole processing apparatus in the stored order after step (b).

(e) converting the n (arbitrary natural number) bit data inputted from the receiving first-in first-out unit into m (arbitrary natural number) bit data and outputting the m-bit arbitrary data to the central processing unit. Can be performed.

N may be a number corresponding to a data bus width to the peripheral device, and m may be a number corresponding to an operation bit of the CPU.

Step (a) may include: (f) receiving shift registers sequentially receiving data from the peripheral device and outputting the data; And (g) generating a flag signal corresponding to the number of bits received by the reception shift register and transmitting the flag signal to a control signal generator included in the reception control unit.

(h) The synchronizing unit included in the reception control unit may convert the flag signal according to the second clock into the control signal generation unit in correspondence with the first clock, after step (g). have.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

The present invention is an interface module for communication between a central processing unit (CPU) and a peripheral device or communication between two microprocessors, and can be universally applied to an interface module capable of operating in master mode and / or slave mode. Self-explanatory However, hereinafter, the interface module is an SPI, and a description will be given mainly on the case of transmitting and receiving data between the CPU and the peripheral device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

2 is a block diagram illustrating an interface module for mediating data transfer in a slave mode. 2, the interface module according to the present invention includes a register unit spiReg 200, a transmission unit 210, a reception unit 220, a clock divider spiClkDiv 230, and a transfer unit spiTRCtrl 240. ).

The register unit spiReg 200 is connected to the central processing unit to exchange data between the central processing unit and the SPI.

The register unit spiReg 200 may include the SPI STATUS REGISTER 101 illustrated in FIG. 103).

The transmission unit 210 may include a transmission control unit spiTxCtrl 211 and a first-in first-out unit spiTxFIFO 212.

Similarly, the reception unit 220 may include a reception control unit spiRxCtrl 221 and a first-in first-out unit spiRxFIFO 222.

Here, in the interface module for mediating data exchange between the CPU and the peripheral device, for convenience of description, the following description will be given of the transmission process of receiving data from the CPU and outputting the data to the peripheral device, and vice versa. Explain.

The clock divider spiClkDiv 230 divides PCLK, which is a system clock input from the CPU, to generate SCLK0, which is an internal clock.

The transfer unit spiTRCtrl 240 is a block that is connected to an external peripheral device and performs serial communication.

Here, pins such as MISO (Master Input Slave Output), MOSI (Master Output Slave Input), SS (Slave Select), SCK (Serial Clock), etc. will be apparent to those skilled in the art, and thus descriptions thereof will be omitted.

In the process of transmitting / receiving data in the slave mode by the interface module (hereinafter, referred to as 'SPI'), when looking at the clock used by the component of the SPI, the boundary of FIG. Can be divided. On the left side of the boundary line, an internal clock (ie, SCLK0 generated by dividing the system clock PCLK by the clock divider 230 in FIG. 2) is operated. In the case of the right side, the transfer unit (spiTRCtrl, 240) is performed. It operates with peripheral clock inputted from peripheral device through SCLK pin of.

As described above, since various delays or other time axis distortions or breaks may occur in the peripheral device, the peripheral clock input through the SCLK pin of the transfer unit spiTRCtrl 240 may be an internal clock. It can be asychronous with.

At this time, when the clock used by the component in the process of transmitting and receiving the control signal between the components of the SPI (asychronous), the transmission and reception of the control signal may not be performed normally. At this time, data exchanged between the CPU and the peripheral device may be unstable.

In the SPI according to the preferred embodiment of the present invention, data can be stabilized by synchronizing and transmitting the control signal to a clock used by the component in transmitting and receiving the control signal between the components. This will be described later with reference to FIGS. 3 and 4.

For convenience of description, the clock generated by the clock divider 230 by dividing the system clock (SCLK0 in FIG. 2) is referred to as an 'internal clock' in the following drawings, and the SCLK pin of the transmitter 240 is changed from a peripheral device. The clock inputted through this is called 'peripheral clock'.

The following briefly describes the operation of the synchronization unit for synchronizing the control signal between the components of the SPI to the clock used by each component, and then the process of transmitting and receiving data will be described in order.

3 is a synchronization unit using two general D-flip-flops.

3 illustrates an operation of two flip-flops 310 and 320 with respect to the input signal In when the synchronization unit operates at the rising edge of the clock.

Since the configuration and the technology for the synchronization unit using the two de-flip-flops are well known techniques, detailed description thereof will be omitted.

In addition, although the synchronization unit using the de-flip-flop is used in the preferred embodiment of the present invention, it is apparent to those skilled in the art that the synchronization unit for synchronizing the internal clock and the peripheral clock can be used regardless of the name.

In addition, the position and function of the synchronization unit used in the present invention will be described in detail in the process of transmitting and receiving data below.

Hereinafter, a case in which an SPI receives data from a central processing unit and transmits data to a peripheral device in slave mode will be described with reference to FIGS. 4 and 5, and vice versa with reference to FIGS. 6 and 7. do.

Hereinafter, the process of exchanging data between the central processing unit and the peripheral device in one embodiment of the present invention will be described as an example, it will be apparent to those skilled in the art that SPI can also be used between peripheral devices.

4 is a diagram illustrating a configuration for transmitting data in a slave mode of an SPI according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating a data transmission method of an SPI in a slave mode according to an embodiment of the present invention. It is a flow chart.

4 is a diagram illustrating the transmitter of FIG. 2 in more detail. Referring to FIG. 4, the register unit 200 includes a bit divider 201, and the first-in first-out unit 212 includes a first input first (FIFO). Ouput, 400).

Also, the transmission control unit 211 includes a transmission data register 421, a transmission shift register 420, a transmission finite state mashine (hereinafter referred to as TxFSM) 410, and a second synchronization unit 411. ).

The transfer unit spiTRCtrl 240 includes a multiplexer 243, a counter unit 424, and a first synchronization unit 241.

The bit divider 201 divides m (random natural number) bits of data input from the central processing unit into n (arbitrary natural numbers) bit data and transmits the data to the first-in first-out part of the SPI (spiTxFIFO) 212.

In this case, m may be an operation bit of the central processing unit, and n may be a number corresponding to the data bus width between the interface module and the peripheral device.

For example, when the CPU is 8051, m may be 8 because it is calculated as 8 bits, and when the CPU is an ARM (Advanced RISC Machine), m may be 32.

In addition, n may be changed according to the data bus width between the peripheral device and the interface module (more specifically, between the transmission unit 240 and the peripheral device). The data bus width is the amount of data that 1 hz can transfer between devices.

However, m and n are not necessarily limited to the above-described meaning, and it will be apparent to those skilled in the art that various changes may be made depending on the process of implementing the present invention or the environment of the interface module and the peripheral device.

Since the first-in-first-out (spiTxFIFO) 212 includes a FIFO (First Input First Output, 400), the data may be stored and then read back in the stored order to output the data to the transmission data register 421 of the SPI. .

More specifically, even if a large amount of data is instantaneously input from the central processing unit, the data can be stored in the FIFO 400 and then read back in the stored order and transferred to the transmission data register 421.

Since the process of transferring the data input from the central processing unit to the transmission shift register 420 through the transmission data register 421 is a technique known to those skilled in the art, a description thereof is omitted here, and the data input from the central processing unit is transmitted. It will be described below after transferring to the shift resist.

Data received from the transmission data register 421 is transmitted from the transmission shift register 420 to the peripheral device through the multiplexer 243.

 In this case, the left side operates using an internal clock on the basis of the boundary line in FIG. 4, and the right side operates using a peripheral clock input from a peripheral device.

Here, the TxFSM 410 and the SPI transmission shift register (SPITSR) 420 and the transmission data register 421 which operate on the left side of the boundary line operate as internal clocks, and the counter unit 242 and the multiplexer 243 are operated. Acts as a peripheral clock. Therefore, since the clock may be asynchronous, the data to be transmitted may become unstable.

According to an exemplary embodiment of the present invention, the control signal output from the TxFSM 410 is synchronized with the peripheral clock from the first synchronization unit 241.

The TxFSM 410 is a predetermined program module, which is a signal for enabling the start signal (counter unit 242) to start transmission (for example, data received from the central processing unit to the peripheral device). ) And a control signal such as a stop signal for ending transmission (a signal for disabling the counter 242) is output to the counter 242. The TxFSM 410 is an example of a control signal generator that generates and outputs a control signal for controlling the start or / and end of data transmission, and all program modules or hardware components capable of performing the same function regardless of its name. It will be apparent to those skilled in the art that all of these can be applied without this limitation. However, in the present specification, it is assumed that the control signal generator is TxFSM.

The interface module receives data from the central processing unit and transmits the data to the peripheral device several times within a short time. That is, the start signal and the stop signal may be transmitted from the TxFSM 410 to the counter unit 242 within a short time. However, since the TxFSM 410 operates using the internal clock and the counter unit 242 operates using the peripheral clock, when the internal clock and the peripheral clock are asynchronous, the data transmission becomes unstable.

Therefore, the control signal output from the TxFSM 410 is synchronized with the peripheral clock from the first synchronization unit 241 according to the preferred embodiment of the present invention is input to the counter unit 242.

For example, when the TxFSM 410 outputs a start signal (a kind of control signal) to start transmission of the interface module, the start signal is synchronized to the peripheral clock in the first synchronization unit 241. Since the process of synchronizing has been described with reference to FIG. 3, duplicate description thereof will be omitted.

The start signal synchronized to the peripheral clock is input to the counter unit 242 to enable the counter unit 242.

The counter unit 242 enables the multiplexer 243 to sequentially transmit data input from the transmission shift register 420 to the multiplexer 243 to the peripheral device.

At this time, the counter unit 242 counts the number of times the multiplexer 243 is enabled, and generates a flag signal when a certain number of times is reached.

For example, when the predetermined number of times corresponding to the data bus width between the transmission unit 240 and the peripheral device is 16, the counter unit 242 generates a flag signal when the number of times the multiplexer 243 is enabled is 16. Create

The TxFSM 410 transmits a control signal called a start command to start the data transmission from the central processing unit to the peripheral device to the counter unit 242, and then receives a flag signal indicating whether data transmission is normally performed. Monitor.

However, as described above, the TxFSM 410 operates as an internal clock, the counter unit 242 operates as a peripheral clock, and a flag signal generated by the counter unit 242 is generated in association with the peripheral clock. Therefore, when the flag signal is directly input to the TxFSM 410, since the interlocked clocks are asynchronous, it is not properly monitored whether the SPI normally transmits data.

According to a preferred embodiment of the present invention, the flag signal generated by the counter unit 242 is synchronized to an internal clock (that is, SCLK0 in FIG. 4) by the second synchronization unit 411 and input to the TxFSM 410. . Therefore, the TxFSM 410 operating as an internal clock can more accurately monitor whether the SPI normally transmits data from the CPU to the peripheral device by receiving a flag signal synchronized with the internal clock.

In addition, as described above, more accurate monitoring is performed in the TxFSM 410, so that a more accurate control command (not shown in FIG. 4) is transmitted from the TxFSM 410 to the transmission data register 421 and the transmission shift register 420. Can transmit

For example, the transmission data register 421 and the transmission shift register 420 may transmit data in units of 16 bits. That is, data can be transmitted in units of 16 bits corresponding to the data bus width between the SPI and the peripheral device.

At this time, when the counter unit 242 enables the multiplexer 243 16 times and generates a flag signal, it means that data in units of 16 bits of the transmission shift register 420 has been transmitted to the peripheral device. Accordingly, the TxFSM 410, which is synchronized with the internal clock and receives a more accurate flag signal, transmits a control signal (for example, read) to the 16-bit unit data from the FIFO 400 to the transmission data register 421. In addition, the transmission shift register 420 may transmit a control signal (for example, read) to receive 16-bit data from the transmission data register 421.

At this time, since the TxFSM 410, the transmission data register 421 and the transmission shift register 420 operate as the internal clock, the control signals to be transmitted and received to each other are linked to the same internal clock, so no special synchronization is necessary.

Therefore, according to a preferred embodiment of the present invention, a more accurate control command (not shown in FIG. 4) can be transmitted from the TxFSM 410 to the transmission data register 421 and the transmission shift register 420.

As described above with reference to FIG. 4, in a process in which the SPI transmits data in the slave mode according to an exemplary embodiment of the present invention, the transmission control unit 211 and the transmission unit 240 control each other to be transmitted and received. The process of synchronizing and transmitting and receiving signals according to respective operating clocks has been described.

However, in the embodiment described with reference to FIG. 4, the counter unit 242 is a 4-bit counter, the multiplexer 243 is a 16: 1 multiplexer, and the first and second synchronizers 241 and 411 are decoded. -D flip-flop (D-flipflop) was used as an example, but not limited to it will be apparent to those skilled in the art.

The data transmission method will now be described with reference to FIG. 5 with reference to a process of transmitting data in the slave mode of the SPI.

Hereinafter, descriptions overlapping with those described with reference to the exemplary embodiment of FIG. 4 will be omitted. For convenience of explanation, the case of a control signal (for example, a start signal) that starts transmission in the TxFSM 410 will be described as an example.

As shown in FIG. 5, in step S510, the control signal output from the TxFSM 410 is synchronized from the first synchronization unit 241 to the peripheral clock, and is input to the counter unit 242 in step S515. Enable.

Subsequently, the counter unit 241 enables the multiplexer in step S540, and the data input from the transmit shift register 420 of the SPI is output through the multiplexer 243 in step S545.

In addition, the counter unit 241 generates a flag signal whenever the number of times the multiplexer 243 is enabled becomes a predetermined number of times (that is, a number corresponding to the data bus width between the transmission unit 240 and the peripheral device). (Step S520). The generated flag signal is synchronized with the internal clock (i.e., SCLK0 in FIG. 4) by the second synchronization unit 411 (step S525), and the TxFSM 410 is sent to the peripheral device with reference to the flag signal synchronized with the internal clock. It is monitored whether the data transmission is normally performed (step S530).

So far, the configuration and method of receiving data from the central processing unit and transmitting the data to the peripheral device in the SPI slave mode have been described. Hereinafter, a configuration and a method of receiving data from a peripheral device in the SPI slave mode and transmitting data to the CPU will be described with reference to FIGS. 6 and 7.

6 is a diagram illustrating a configuration of transmitting data in a slave mode of an SPI according to an embodiment of the present invention, and FIG. 7 is a diagram illustrating a method of receiving data of an SPI in a slave mode according to an embodiment of the present invention. It is a flow chart.

FIG. 6 is a diagram illustrating the receiver of FIG. 2 in more detail. Referring to FIG. 6, the register unit 200 includes a bit combiner 601, and the first-in first-out unit 212 includes a FIFO (First Input). First Output) 602.

In addition, the reception control unit 221 includes a reception data register 607, a reception finite state machine (hereinafter referred to as RxFSM) 606, and a synchronization unit 605.

The transfer unit spiTRCtrl 240 includes a counter unit 604 and a reception shift register 240.

Here, the block diagram shown in FIG. 6 is divided based on the function of each component and the clock used by each component, and it will be apparent to those skilled in the art that the present invention is not limited to the configuration shown in FIG. 6.

As described above with reference to FIGS. 4 and 5, for convenience of description, the interface module will be described below using SPI as an example, and receiving data from a peripheral device in a slave mode as a central processing unit as an example. Explain.

When the peripheral clock (SCLK1 in FIG. 6) is input from the peripheral device to the SCK pin of the transmitter 240 in the slave mode, the reception shift register 603 receives data from the peripheral device.

In this case, in the preferred embodiment of the present invention, when the peripheral clock is input to the SCK pin of the transmitter 240 in the slave mode, the reception shift register 603 starts receiving data from the peripheral device as an example. However, it will be apparent to those skilled in the art that the present invention is not limited thereto.

For example, even when the peripheral clock is input to the SCK pin of the transmitter 240, a control signal (for example, a read) of the RxFSM 606 must be input to the reception shift register 603 to receive data from the peripheral device. It will be apparent to those skilled in the art.

The data input from the peripheral device is input to the reception data register 607 through the reception shift register 603 of the SPI.

At this time, the counter unit 604 counts the number of data bits input to the reception shift register 603 and generates a flag signal when a predetermined number of times is reached. Here, it will be apparent to those skilled in the art that the predetermined number of times may be variously changed in the process of implementing the SPI or depending on the environment with the peripheral device receiving the data.

For example, as described with reference to FIG. 4, it may be a predetermined number of times corresponding to the data bus width between the transfer unit and the peripheral device.

For example, the reception shift register 607 and the reception data register 602 may be a number of times corresponding to a unit of data that can be transmitted at one time.

Hereinafter, it will be described on the assumption that the number corresponding to the data bus width between the transmission unit 240 and the peripheral device is 16 in the same manner as the example described with reference to FIG. 4.

The counter unit 604 generates a flag signal whenever the reception shift register 603 receives 16 bits from the peripheral device, and transmits the generated flag signal to the RxFSM 606 for monitoring whether the SPI reception process is normal. .

At this time, the counter unit 604 and the reception shift register located on the right side of the boundary line operate as peripheral clocks inputted from the peripheral device to the SCK pin. In addition, the reception data register 607 and the RxFSM 606 positioned on the right side of the boundary line have an internal clock generated by the clock divider 230 by dividing the system clock (PCLK in FIG. 6) (ie, in the case of FIG. 6). SCLK0).

Here, since the peripheral clock and the internal clock may be asynchronous (asychronous) has been described with reference to Figure 4, the description thereof will be omitted.

The RxFSM 410 is a predetermined program module that monitors whether a reception (for example, data input from a peripheral device and output to a central processing unit) is normal.

The process of receiving data from the peripherals and outputting the data to the central processing unit can be repeated many times within a short time. In the prior art, the RxFSM 606, which operates on the internal clock, receives control signals from other components of the transfer unit that operates on the peripheral clock to monitor whether the SPI reception process is normal. Therefore, since the clock to which the control signal is interlocked is asynchronous, the RxFSM 606 is not accurately monitored in the process of receiving the signal several times within a short time.

According to a preferred embodiment of the present invention, the flag signal generated by the counter unit 604 is input to the RxFSM 606 which is synchronized with the internal clock in the synchronizer 605 and then operates as an internal clock. Accordingly, by receiving a flag signal synchronized with the internal clock in the RxFSM 606 operating as an internal clock, monitoring of whether the reception process of the SPI is normal is made more accurate.

Further, when the RxFSM 606 receives the flag signal, the RxFSM 606 may transmit a more accurate control signal to the receiving data register 602.

For example, the transmission data register 421 may transmit data in units of 16 bits. That is, data can be transmitted in units of 16 bits corresponding to the data bus width between the SPI and the peripheral device.

In this case, in the case of the embodiment described above with reference to FIG. 6, when the counter unit 604 generates a flag signal, 16-bit data is received by the reception data register 602 from the peripheral device through the reception shift register 607. It means. Accordingly, the RxFSM 606 is synchronized to an internal clock to receive a more accurate flag signal and correspondingly transmit a 16-bit data from the reception data register 602 to the reception first-in, first-out part 222 (for example, for example). , Write) can transmit a control signal (for example, read).

At this time, since the RxFSM 606 and the receiving data register 607 operate with an internal clock, the control signals transmitted and received between the two are interlocked with the same internal clock, so that no special synchronization is required.

Therefore, according to a preferred embodiment of the present invention, a more accurate control command (not shown in FIG. 6) can be transmitted from the RxFSM 606 to the receiving data register 607.

As described above, the RxFSM 606 monitors whether the reception (eg, receiving data from the peripheral device and outputting the data to the central processing unit) from the interface module is normally performed, and generates a control signal accordingly. Can be transmitted to the reception data register 607.

According to another embodiment of the present invention, even when a peripheral clock is input from the peripheral device to the SCK pin of the transmission unit 240 in the slave mode, a control signal (for example, Read) from the RxFSM is transmitted to the reception shift register 603. Receipt can be initiated only after input.

For example, a start signal (a signal enabling the reception shift resist 603) to start reception (receiving data from a peripheral device and outputting the data to a central processing unit) in the RxFSM, and a stop signal to end reception ( A control signal such as a signal for disabling the reception shift resist 603 may be generated and transmitted to the reception shift register 603.

At this time, the RxFSM transmits the above-described control signal to the counter unit 604 so that the counter unit 604 is enabled or disabled, and correspondingly, the counter unit 604 receives the reception shift register. 603 may be enabled or disabled. The RxFSM 606 is an example of a control signal generator that generates and outputs a control signal for controlling a data reception process and / or a start or end of a reception, and all programs capable of performing the same function regardless of its name. It will be apparent to those skilled in the art that any module or hardware configuration can be applied without limitation. However, in the present specification, it is assumed that the control signal generator is an RxFSM.

In addition, according to the preferred embodiment of the present invention with reference to Figure 4 TxFSM (410) generates a control signal in the process of receiving data from the central processing unit and transmits to the peripheral device according to the present invention with reference to FIG. In accordance with a preferred embodiment of the present invention, it is apparent to those skilled in the art that an RxFSM generating a control signal in the process of receiving data from a peripheral device and receiving the data from a peripheral device may be implemented in the same configuration regardless of its name.

The reception first-in first-out unit spiRxFIFO 222 includes a first input first output (FIFO) 602, which stores data input from the reception data register 607, and then reads and rereads the data in the stored order. You can output data with).

More specifically, even if a large amount of data is instantaneously input from the peripheral device, the data can be stored in the FIFO 602, read back in the stored order, and transferred to the register unit 200. FIG.

The bit combiner 601 combines m (random natural number) bits of data input from the first-in first-out unit 222 into n (random natural numbers) bit data and outputs the data to the CPU.

In this case, m may be an operation bit of the CPU, and n may be a number corresponding to the data bus width between the SPI and the peripheral device.

Since this is similar to that described in the description of the bit divider 201 of the transfer unit 200 with reference to FIG. 4, redundant description thereof will be omitted.

In the example described with reference to FIG. 6, the operation bit of the central processing unit is 32 bits, and the number corresponding to the data bus width between the transfer unit 240 and the peripheral device is assumed to be 16.

However, it is apparent to those skilled in the art that m and n are not necessarily limited to the above-described meanings and may be variously changed according to the process of implementing the present invention and the environment of the interface module and the peripheral device.

The data receiving method will be described with reference to FIG. 7 with reference to the configuration for receiving data in the slave mode of the SPI.

Hereinafter, descriptions overlapping with those described with reference to the exemplary embodiment of FIG. 6 will be omitted.

In addition, an example assumed in the embodiment of FIG. 6 will be described with reference to FIG. 7. In other words, the interface module will be described using SPI as an example, and the counter unit 604 will be described below on the assumption that a flag signal is generated every time 16 bits are input to the reception shift register 603.

Referring to FIG. 7, when a peripheral clock (see SCLK1 in FIG. 6) is input from the peripheral device to the SCK pin of the transmitter 240 in the slave mode, the reception shift register 603 receives data from the peripheral device (step S705). ).

Subsequently, in step S710, the counter unit 604 generates a flag signal whenever data input to the reception shift register from the peripheral device is 16 bits.

In this case, the number of bits of data input to the reception shift register, which is a condition for generating a flag signal in the counter unit 604, may be changed according to the process of implementing the present invention or the environment of the interface module and the peripheral device. Has been described with reference to FIG. 6.

In step S715, the flag signal is synchronized from the synchronizer 605 to the internal clock. According to a preferred embodiment of the present invention, since the counter unit 604 operates as a peripheral clock, the flag signal generated by the counter unit 604 is interlocked with the peripheral clock, so that the synchronization unit 605 operating as an internal clock is provided. In order to transmit more accurately, the synchronization unit 605 synchronizes with the internal clock.

Next, in step S720, a flag signal is transmitted from the synchronizer 605 to the RxFSM 606.

In this case, the RxFSM 606 has been described with reference to FIG. 6 that the SPI can monitor whether the SPI normally receives data from the peripheral device using the flag signal input from the synchronizer 605.

6, the RxFSM 606 can send a more accurate control signal to the reception data register 607 using the flag signal input from the synchronization unit 605. FIG.

In response to the control signal from the RxFSM 616 described above in step S725, the data input from the reception shift register 603 is input to the reception data register 607 and then stored in the first-in first-out section spiRxFIFO 222. The data is read back and combined by the bit combiner 601 into n (random natural numbers) bits and transmitted to the CPU. (Not shown in Figure 7)

As described with reference to FIGS. 6 and 7, according to an exemplary embodiment of the present invention, in the process of receiving data from the peripheral device by the SPI in the slave mode, the reception controller 221 and the transmitter 240 mutually interact with each other. It has been described that the control signals transmitted and received are synchronized with each other according to the clock of each operation, and thus, the data received is stabilized.

6 and 7, the counter unit 604 uses a 4-bit counter and the synchronizer 605 uses a D-flipflop as an example. It should be apparent to those skilled in the art that the present invention is not limited thereto.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, the interface module according to the present invention, in the slave mode (Slave mode) in the process of transmitting and receiving data between the central processing unit and the peripheral device, the control signal transmitted and received between the components of the interface module, each operation clock According to the synchronization is transmitted and received, there is an advantage that a more accurate control signal is transmitted and received.

In addition, the interface module according to the present invention has an advantage of stabilizing data in the process of exchanging data in the slave mode.

Claims (28)

An interface module for transmitting data from a central processing unit to a peripheral device in a slave mode, A transmission control unit operating in correspondence with a first clock and outputting data input from the central processing unit; And A transmission unit operating in correspondence with a second clock input from the peripheral device and sequentially outputting data input from the transmission control unit to the peripheral device; The transmission control unit and the transfer unit interface module comprising a synchronization unit for converting control signals transmitted and received between each other according to the operation clock The method of claim 1, Interface module further comprises a clock divider for generating the first clock using the system clock input from the central processing unit The method of claim 1, And a register unit converting the m (arbitrary natural number) bit data input from the central processing unit into n (arbitrary natural number) bit data and outputting the bit data to the transmission control unit. The method of claim 3, wherein And a transmission first-in, first-out unit for storing the n-bit data input from the register unit and outputting the n-bit data to the transmission control unit in the stored order. The method of claim 3, wherein M is a number corresponding to the operation bit of the CPU, N is a number corresponding to a data bus width between the interface module and the peripheral device. The method of claim 1, The delivery unit, A multiplexer sequentially outputting data input from the transmission control unit to the peripheral device; A counter unit for generating a multiplexer enable signal for enabling the multiplexer; And A synchronization unit for synchronizing a control signal input from a control signal generation unit included in the transmission control unit with the second clock and transmitting the control signal to the counter unit, And the counter unit generates a flag signal corresponding to the number of generations of the multiplexer enable signal and provides the flag signal to the control signal generator. The method of claim 6, The transmission control unit further comprises a synchronization unit converting the flag signal according to the second clock to correspond to the first clock and providing the control signal to the control signal generator. An interface module for receiving data from a peripheral device to a central processing unit in a slave mode, A transfer unit operating in correspondence with a second clock input from the peripheral device, and outputting data sequentially input from the peripheral device; And A reception control unit which operates in response to a first clock and outputs data input from the transfer unit to a central processing unit; And the reception control unit and the transfer unit include a synchronization unit for converting control signals transmitted and received to each other according to operation clocks. The method of claim 8, And a clock divider configured to generate the first clock using a system clock input from the CPU. The method of claim 8, And receiving first-in, first-out unit for storing the data inputted from the reception control unit and outputting the data to the central processing unit in the stored order. The method of claim 10, And a register unit for converting the n (arbitrary natural number) bit data inputted from the receiving first-in first-out unit into m (arbitrary natural number) bit data and outputting the m-bit arbitrary data. The method of claim 11, N is a number corresponding to a data bus width between the interface module and the peripheral device, M is the number corresponding to the operation bit of the central processing unit. The method of claim 8, The delivery unit, A reception shift register sequentially receiving data from the peripheral device and outputting the data; And And a counter unit generating a flag signal corresponding to the number of bits received by the reception shift register and providing the flag signal to a control signal generator included in the reception control unit. The method of claim 13, The reception control unit further comprises a synchronization unit for converting the flag signal according to the second clock corresponding to the first clock to provide to the control signal generator. An interface method for transmitting data from a CPU to a peripheral device in a slave mode, (a) outputting data input from the central processing unit by a transmission controller operating in response to a first clock; (b) a step of sequentially transmitting data input from the transmission control unit to the peripheral device, the transfer unit operating in correspondence with the second clock input from the peripheral device, And the transmission control unit and the transfer unit convert control signals transmitted and received to each other according to each operation clock. The method of claim 15, (c) generating a first clock using a system clock inputted from the CPU by a clock divider; Interface method characterized in that it is further performed before step (a). The method of claim 15, (d) converting the m (arbitrary natural number) bit data inputted from the central processing unit into n (arbitrary natural number) bit data inputted from the CPU, and outputting the bit to the transmission control unit Interface method characterized in that it is further performed before step (a). The method of claim 17, M is a number corresponding to the operation bit of the CPU, And n is a number corresponding to a data bus width to the peripheral device. The method of claim 17, (e) transmitting first-in first-out unit to store the n-bit data input from the register unit, and then outputting to the transmission control unit in the stored order is further performed between step (d) and step (a). Interface method. The method of claim 15, In step (b), (f) a multiplexer sequentially outputting data input from the transmission control unit to the peripheral device; (g) generating, by a counter unit, a multiplexer enable signal for enabling the multiplexer; And (h) synchronizing a control signal input from a control signal generation unit included in the transmission control unit with the second clock to the counter unit by a first synchronization unit; And the counter unit generates a flag signal corresponding to the number of generations of the multiplexer enable signal and provides the flag signal to the control signal generator. The method of claim 20, (i) converting the flag signal according to the second clock into the second signal included in the transmission controller so as to correspond to the first clock, and inputting the flag signal to the control signal generator further after step (h); Interface method characterized in that. An interface method for receiving data from a peripheral device to a CPU in a slave mode, (a) outputting data sequentially input from the peripheral device by a transfer unit operating in response to a second clock input from the peripheral device; And (b) outputting data input from the transmission unit to the central processing unit by a reception controller operating in response to a first clock, And the reception control unit and the transfer unit convert control signals transmitted and received to each other in correspondence with respective operation clocks. The method of claim 22, (c) generating a first clock using a system clock inputted from the CPU by a clock divider; Interface method characterized in that performed before step (a). The method of claim 22, and (d) storing the data input from the reception control unit by the first-in first-out unit and outputting the data to the midsole processing apparatus in the stored order after step (b). The method of claim 24, (e) converting the n (arbitrary natural number) bit data inputted from the receiving first-in first-out unit into m (arbitrary natural number) bit data and outputting the m-bit arbitrary data to the CPU, after step (d). Interface method, characterized in that performed. The method of claim 25, N is a number corresponding to the data bus width to the peripheral device, M is a number corresponding to the operation bits of the CPU. The method of claim 22, In step (a), (f) receiving and outputting data sequentially from the peripheral device by a reception shift register; And (g) a counter unit generating a flag signal corresponding to the number of bits received by the reception shift register and transmitting the flag signal to a control signal generation unit included in the reception control unit. The method of claim 27,  (h) the synchronizing unit included in the reception control unit converting the flag signal according to the second clock corresponding to the first clock and inputting the flag signal to the control signal generator is further performed after step (g). Characterized by the interface method.

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