CN108932210B - Data transmission device and data receiving device of serial peripheral interface - Google Patents
Data transmission device and data receiving device of serial peripheral interface Download PDFInfo
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 36
- 239000000872 buffer Substances 0.000 claims abstract description 115
- 230000004044 response Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses a data transmission device and a data receiving device of a serial peripheral interface, wherein the data transmission device comprises an output buffer, a selection unit and a control unit; the output buffer is operated in an internal clock domain corresponding to an internal clock signal and is used for receiving a plurality of first digital data of parallel data and outputting the plurality of first digital data, and the control unit controls the selection unit to sequentially select one of the plurality of first digital data to be output according to a serial clock signal. The data receiving device comprises a control unit which controls an input buffer to store a plurality of digital data of serial data, and the input buffer is provided with a plurality of output ends for outputting the plurality of digital data.
Description
Technical Field
The present invention relates to data transmission devices, and particularly to a serial data transmission device.
Background
Serial Peripheral Interface (SPI) is widely used. The serial peripheral interface includes four terminals, which are serial clock terminals sck (serial clock): the Master outputs a Slave Input signal terminal MOSI (Master Output, Slave Input), the Master inputs a Slave Output signal terminal MISO (Master Input, Slave Output), and a chip select terminal cs (chip select).
As shown in fig. 8, two single chip systems are connected to each other by Serial Peripheral Interface (SPI) 54, 44, respectively, one of the single chip systems being the master device 50 and the other being the slave device 40. The serial clock terminals SCK of the serial peripheral interfaces 54 and 44 are connected to each other, and the serial clock signal at the serial clock terminal SCK is supplied from the master device 50 to the slave device 40. The data transmission between the serial peripheral interfaces 54, 44 is synchronized by a serial clock signal, and the master device 50 outputs serial data from the slave input signal terminal MOSI to the slave device 40 via the master; the slave device 40 outputs serial data to the master device 50 via the master input slave output signal terminal MISO.
Each of the SPI 54, 44 includes a data transmitting device and a data receiving device. The data transmission device is used for outputting data to an external device, and the data receiving device is used for receiving externally input data. In the master device 50, the data transmission device of the serial peripheral interface 54 is connected to the master-output-slave-input signal terminal MOSI, and the data reception device is connected to the master-input-slave-output signal terminal MISO. In the slave device 40, the data transmission device of the serial peripheral interface 44 is connected to the master input/slave output signal terminal MISO, and the data reception device is connected to the master output/slave input signal terminal MOSI. The data transfer means of the serial peripheral interfaces 54, 44 are somewhat different. The data transmission device of the serial peripheral interfaces 54, 44 has a buffer and a register, and transmits data from the parallel buses 52, 42 to the master-out-slave-in signal terminal MOSI or the master-in-slave-out signal terminal MISO, and at least 2 internal clocks using the internal clock signal are required. The data receiving device of the serial peripheral interface 44, 54 also has a buffer and a register, and the data received by the machine output slave input signal terminal MOSI or the machine input slave output signal terminal MISO is transmitted to the parallel bus 42, 52 by using at least 1 internal clock in the internal clock signal.
Disclosure of Invention
The present invention is directed to an improved data transmitting device and an improved data receiving device of a serial peripheral interface.
The main technical means to achieve the above object is to make the data transmission device of the serial peripheral interface convert a first parallel data including a plurality of first digital data into a serial format and then output the converted data from a data output terminal of the serial peripheral interface, wherein the data transmission device comprises:
a first output buffer, operating in an internal clock domain corresponding to an internal clock signal, for receiving the first parallel data and outputting the first digital data, wherein the first output buffer has a plurality of first storage elements for storing the first digital data;
a first selection unit having an output end connected to the data output end and a plurality of first input ends for receiving the plurality of first digital data outputted from the first output buffer, wherein the first selection unit is used for selecting one of the plurality of input ends to be connected to the data output end so as to output one of the plurality of first digital data; and
and the control unit is connected with the first selection unit and controls the first selection unit to output the plurality of first digital data in sequence according to a serial clock signal.
As can be seen from the above description, the data transmission device of the present invention omits the shift register of the data transmission device with the existing serial peripheral interface, which is helpful to save area and reduce cost; the detailed description and other advantages will be described in the following embodiments.
The main technical means to achieve the above object is a data receiving device of a serial peripheral interface, the serial peripheral interface having a data input terminal for receiving a first serial data including a plurality of first digital data, comprising:
a first input buffer having a plurality of first output terminals, the first input buffer being configured to receive the first serial data and output the first digital data from the plurality of first output terminals, wherein the first input buffer has a plurality of first storage elements for storing the first digital data; and
the control unit is used for controlling the first input buffer to sequentially store the plurality of first digital data to the plurality of first storage elements according to the serial clock signal.
As can be seen from the above description, the data receiving device of the present invention omits the shift register of the data receiving device having the existing serial peripheral interface, which is helpful to save area and reduce cost. The detailed description and other advantages will be described in the following embodiments.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1: the invention is a functional block diagram of a serial peripheral interface;
FIG. 2: a functional block diagram of an embodiment of a data transfer device of the present invention;
FIG. 3: FIG. 2 shows an embodiment of a data transfer device;
FIG. 4: a functional block diagram of another embodiment of a data transfer device according to the present invention;
FIG. 5: a functional block diagram of an embodiment of a data receiving apparatus of the present invention;
FIG. 6: fig. 5 shows an embodiment of a data receiving apparatus;
FIG. 7: a functional block diagram of another embodiment of a data receiving device according to the present invention;
FIG. 8: two single chip systems use a functional block diagram of the existing serial peripheral interface interconnect.
Wherein the reference numerals
A serial peripheral interface 10 integrated circuit device
11 processing unit 12 parallel bus
20. 20' data transfer device 21 control unit
22 output buffer 222 first storage element
224 multiplexer 23 selection unit
232 a first input terminal 234 and an output terminal
24 output buffer 26 selection unit
27 selection unit 28 control unit
30. 30' data receiving device 31 control unit
32 input buffer 322 first storage element
324 multiplexer 326 first input terminal
33 control unit 34 input buffer
36 selection unit 38 selection unit
40 slave 42 parallel bus
44 serial peripheral interface 50 host device
52 parallel bus 54 serial peripheral interface
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
FIG. 1 illustrates a serial peripheral interface A according to the present invention. In fig. 1, the integrated circuit device 10 may be a master device (host) or a slave device (slave), that is, the serial peripheral interface a may be applied to the master device or the slave device. The integrated circuit device 10 includes a processing unit 11, a parallel bus 12, and a serial peripheral interface a. The serial peripheral interface a has four terminals, which are a serial clock terminal sck (serial clock), a data Output terminal Output, a data Input terminal Input, and a chip select terminal cs (chip select), respectively. If the integrated circuit device 10 is a Master device, the data Output terminal is a Master Output Slave Input signal terminal MOSI (Master Output), and the data Input terminal is a Master Input Slave Output signal terminal MISO (Master Input). If the integrated circuit device 10 is a Slave device, the data Output terminal is a Master Input/Slave Output signal terminal MISO (Master Input, Slave Output), and the data Input terminal is a Master Output/Slave Input signal terminal MOSI (Master Output, Slave Input). A serial clock signal is provided to the serial clock terminal SCK of the serial peripheral interface A, and the serial clock signal is usually provided by a processing unit (e.g., a CPU) of the host device. The data transmission between the two serial peripheral interfaces A is synchronized by the serial clock signal. The processing unit 11 provides an internal clock signal (internal clock signal), and the serial peripheral interface a receives the internal clock signal and the serial clock signal for data transmission.
The serial peripheral interface a includes a data transmission device 20 and a data reception device 30. The data transfer device 20 is connected between the data Output terminal Output and the parallel bus 12, and is configured to convert a parallel data including a plurality of digital data into a serial form for Output. The data receiving device 30 is connected between the data Input terminal Input and the parallel bus 12, and receives serial data including a plurality of digital data Input from the data Input terminal Input, and transmits the plurality of digital data to the parallel bus 12.
Fig. 2 provides an embodiment of the data transfer device 20. In fig. 2, the processing unit 11 is configured to connect the data transmission apparatus 20 via the parallel bus 12 to transmit a first parallel data including a plurality of first digital data to the data transmission apparatus 20, wherein the first parallel data may be, for example, a Byte (Byte) including 8 digital data (0 or 1) with 1 bit (bit). The data transmission device 20 includes a control unit 21, an output buffer 22 and a selection unit 23. In one embodiment, the control unit 21 receives the serial clock signal and the internal clock signal, and the control unit 21 is connected to the serial clock terminal SCK of the serial peripheral interface a to receive the serial clock signal. The output buffer 22 is connected between the parallel bus 12 and the selection unit 23. The output buffer 22 is configured to receive the first parallel data and transmit the plurality of first digital data to the selecting unit 23. The output buffer 22 has a plurality of first storage elements, such as flip-flops. The output buffer 22 stores the plurality of first digital data in the plurality of first storage elements according to the internal clock signal. The selection unit 23 has an Output connected to the data Output and a plurality of inputs connected to the Output buffer 22. The plurality of input terminals of the selecting unit 23 are configured to receive the plurality of first digital data output from the output buffer 22. The selection unit 23 is connected to the data output terminal output by selecting one of the input terminals, so that one of the first digital data is output. In other embodiments, the selection unit 23 may be a multiplexer or other logic circuit with the same function. The control unit 21 is connected to the selection unit 23, and is configured to control the selection unit 23 to sequentially Output the plurality of first digital data according to the serial clock signal, so that the plurality of first digital data are Output from the data Output terminal in a serial manner. In one embodiment, the control unit 21 includes a Finite State Machine (FSM) connection selection unit 23. The finite state machine generates a control signal to control the operation of the selection unit 23 according to the serial clock signal.
As can be understood from the above description, the output buffer 22 operates in an internal clock domain (internal clock domain) corresponding to the internal clock signal, and the selection unit 23 operates in a serial clock domain (SCK domain) corresponding to the serial clock signal, and the clock domains are different from each other. In response to the selection unit 23 completing outputting the plurality of first digital data, the control unit 21 sends a notification signal to the processing unit 11 in accordance with the internal clock signal of the processing unit 11. Generally, 1 clock of the serial clock signal corresponds to one digital data, and in one embodiment, the control unit 21 sends the notification signal according to the number of clocks of the counted serial clock signal and the internal clock signal. In response to the notification signal, the processing unit 11 transmits the next parallel data to the data transmission device 20.
Fig. 3 illustrates one embodiment of the data transfer device 20. Fig. 3 uses a multiplexer as the selection unit 23. The parallel bus 12 transfers first parallel data including 8 pieces of first digital data D0-D7. The output buffer 22 includes 8 first storage elements 222 and 8 multiplexers 224. Each multiplexer 224 has an input coupled to the parallel bus 12 for receiving 1 digital data. The first storage element 222 is a flip-flop having a clock input receiving the internal clock signal, an input D and an output Q. Each input D of flip-flop 222 is coupled to a 2-to-1 multiplexer 224. multiplexer 224 is a selection unit for selecting the input D of flip-flop 222 for coupling to the data input of multiplexer 224 for transmission to flip-flop 222. In other embodiments, other logic circuits having the same function as multiplexer 224 may be used in place of multiplexer 224. The multiplexer 224 is controlled by the processing unit 11 to transmit the first digital data D0-D7 to the input D of the flip-flop 222, and the first digital data D0-D7 are stored and transmitted to the multiplexer 23 in accordance with a rising edge (or a falling edge) of the internal clock signal. The multiplexer 23 has 8 first input terminals 232 respectively connected to the 8 output terminals Q of the output buffer 22 for receiving the 8 first digital data D0-D7 outputted from the output buffer 22, and a first input terminal 232 for receiving a first digital data. The multiplexer 23 is controlled by the control unit 21 to sequentially output the first digital data D0-D7 from an output port 234 of the multiplexer 23, and the first digital data D0-D7 output from the output port 234 are in serial form.
Compared with the prior art, the data transmission device 20 of the invention omits a shift register, thereby reducing the area and the cost. Moreover, in the operation of the data transfer device 20, only 1 internal clock is used by the output buffer 22, and the frequency requirement of the internal clock signal can be lower in the present invention compared to the prior art that requires 2 internal clocks.
Fig. 4 provides another embodiment of a data transfer device 20'. The data transfer device 20' in fig. 4 comprises output buffers 22, 24, selection units 26, 27, and a control unit 28. In one embodiment, the control unit 28 receives the serial clock signal and the internal clock signal, and the control unit 28 is connected to the serial clock terminal SCK of the serial peripheral interface a to receive the serial clock.
The selection unit 27 is connected between the parallel bus 12 and the output buffers 22, 24 for connecting the parallel bus 12 and one of the output buffers 22, 24. The selection unit 27 sequentially receives first parallel data including a plurality of first digital data and second parallel data including a plurality of second digital data. The selection unit 27 transfers the first parallel data to the output buffer 22 and then transfers the second parallel data to the output buffer 24. In other embodiments, the selection unit 27 may be a demultiplexer or other logic circuit with the same function. The output buffers 22, 24 are both operating in the internal clock domain, and are both coupled between the selection units 27, 26. The output buffer 22 receives the first parallel data and outputs the plurality of first digital data to the selection unit 26, and the output buffer 22 has a plurality of first storage elements for storing the plurality of first digital data, in one embodiment, the first storage elements are flip-flops. The output buffer 24 receives the second parallel data and outputs the second digital data to the selection unit 26, and the output buffer 24 has a plurality of second storage elements for storing the second digital data, in one embodiment, the second storage elements are flip-flops. In one embodiment, the output buffer 24 and the input buffer 22 are the same, and reference is made to fig. 3 for an embodiment of the internal structure of both. The selection unit 26 has an Output connected to the data Output, a plurality of first inputs connected to the Output buffer 22, and a plurality of second inputs connected to the Output buffer 24. The first input terminals are used for receiving a plurality of first digital data outputted from the output buffer 22, and the second input terminals are used for receiving a plurality of second digital data outputted from the output buffer 24. The selecting unit 26 is used for selecting one of the first input terminals and the second input terminals to be connected to the data output terminal, so as to select one of the first digital data and the second digital data for output. In other embodiments, the selection unit 26 may be a multiplexer or other logic circuit with the same function. The control unit 28 is connected to the selection unit 27 for controlling the selection unit 27 to transfer the first parallel data to the output buffer 22 and to transfer the second parallel data to the output buffer 24. The control unit 28 is connected to the selection unit 26, and controls the selection unit 26 to sequentially Output the plurality of first digital data and the plurality of second digital data according to the serial clock signal, so that the plurality of first digital data and the plurality of second digital data are Output from the data Output terminal Output in a serial manner. In one embodiment, the control unit 28 includes one or more Finite State Machines (FSMs) that generate control signals according to the serial clock signal to control the operation of the selection unit 26.
The control unit 28 is further connected to the processing unit 11 via the parallel bus 12. In response to the selection unit 26 completing outputting the plurality of first digital data, the control unit 28 sends a notification signal to the processing unit 11 in accordance with the internal clock signal of the processing unit 11, and controls the selection unit 27 to connect the output buffer 22 to the parallel bus 12. In response to the notification signal, the processing unit 11 transmits a third parallel data to the data transmission device 20'. The third parallel data is transmitted to the output buffer 22 via the selection unit 27. That is, when the selecting unit 26 sequentially outputs the plurality of second digital data, the next parallel data (i.e. the third parallel data) is transmitted to the output buffer 22 to be transmitted, which helps to improve the efficiency of data transmission.
Fig. 5 provides an embodiment of the data receiving apparatus 30 of the present invention. The data receiver 30 is connected between the data Input terminal Input of the serial peripheral interface a and the parallel bus 12. The data Input of the serial peripheral interface A is used for receiving a first serial data including a plurality of first digital data. The data receiving device 30 receives the first serial data via the data Input terminal, and outputs a plurality of first digital data of the first serial data to the parallel bus 12. The first serial data may be, for example, one Byte (Byte) including 8 digital data (0 or 1) of 1 bit (bit). The data receiving apparatus 30 includes an input buffer 32 and a control unit 31. In one embodiment, the control unit 31 receives the serial clock signal and the internal clock signal, and the control unit 31 is connected to the serial clock terminal SCK of the serial peripheral interface a to receive the serial clock signal. The Input buffer 32 has a first Input terminal connected to the data Input terminal and a plurality of first output terminals connected to the parallel bus 12. The input buffer 32 receives the first serial data through the first input terminal, and outputs the first digital data from the first output terminals to the parallel bus 12. The input buffer 32 has a plurality of first storage elements for storing the plurality of first digital data, and in one embodiment, the first storage elements are flip-flops. The control unit 31 is connected to the input buffer 32. The control unit 31 controls the input buffer 32 to sequentially store the plurality of first digital data into the plurality of first storage elements according to the serial clock signal of the serial peripheral interface a. In one embodiment, the control unit 31 includes a Finite State Machine (FSM) coupled to the input buffer 32. The finite state machine generates a control signal to control the operation of the input buffer 32 according to the serial clock signal. The control unit 31 is further connected to the processing unit 11 via the parallel bus 12. In response to the input buffer 32 outputting the plurality of first digital data, the control unit 31 sends a notification signal to the processing unit 11 in accordance with the internal clock signal of the processing unit 11. In one embodiment, the control unit 31 sends the notification signal according to the number of clocks of the counting serial clock signal and the internal clock signal. In response to the notification signal, the processing unit 11 receives the plurality of first digital data via the parallel bus 12.
Fig. 6 illustrates an embodiment of the data receiving apparatus 30, in fig. 6, a flip-flop is used as the first storage element 322, and each flip-flop 322 has a clock input receiving the serial clock signal, an input D and an output Q. The input buffer 32 includes 8 flip-flops 322 and 8 multiplexers 324. The Input buffer 32 includes a first Input 326 connected in series with the Input terminals of the 8 multiplexers 324, and the first serial data Input from the data Input terminal is transmitted to the 8 multiplexers 324. Each flip-flop 322 has an input D coupled to an output of a multiplexer 324 and an output Q coupled to the parallel bus 12. Multiplexer 324 is a selection unit that selects the input terminal of multiplexer 324 to be connected to input terminal D of flip-flop 322, so that the data at the input terminal of multiplexer 324 is transmitted to flip-flop 322. In other embodiments, other logic circuits having the same function as the multiplexer 324 may be used instead of the multiplexer 324. The control unit 31 controls each multiplexer 324 according to the serial clock signal, so that the 8 first digital data of the first serial data are stored in different flip-flops 322. The 8 output terminals Q output the 8 first digital data to the parallel bus 12 for being read by the processing unit 11.
Compared with the prior art, the data receiving device 30 of the present invention omits a shift register, thereby reducing the area and the cost.
Fig. 7 provides another embodiment of a data receiving device 30'. The data apparatus 30' of fig. 7 includes a control unit 33, Input buffers 32, 34 and selection units 36, 38, which can be applied to process a first serial data and a second serial data received from the data Input, wherein the first serial data includes a plurality of first digital data, and the second serial data includes a plurality of second digital data. In one embodiment, the control unit 33 receives the serial clock signal and the internal clock signal, and the control unit 33 is connected to the serial clock terminal SCK of the serial peripheral interface a to receive the serial clock signal.
The selection unit 36 is connected between the data Input terminal Input and the Input buffers 32 and 34, and has an Input terminal coupled to the data Input terminal Input, and two output terminals respectively connected to the Input buffers 32 and 34, wherein the selection unit 36 is configured to connect the Input buffer 32 or 34 with the data Input terminal Input. The selection unit 36 is used for receiving the first serial data and the second serial data in sequence, and transmitting the first serial data to the input buffer 32, and then transmitting the second serial data to the input buffer 34. In other embodiments, the selection unit 36 may be a demultiplexer or other logic circuit with the same function. The input buffers 32 and 34 are both operated in the serial clock domain, and both are coupled between the selection units 36 and 38. Input buffer 32 receives the first serial data and has a plurality of first output terminals outputting the plurality of first digital data to selection unit 38. The input buffer 32 has a plurality of first storage elements for storing the plurality of first digital data, and in one embodiment, the first storage elements are flip-flops. The input buffer 34 receives the second serial data and has a plurality of second output terminals outputting the plurality of second digital data to the selection unit 38. The input buffer 34 has a plurality of second storage elements for storing the plurality of second digital data, and in one embodiment, the second storage elements are flip-flops. In one embodiment, the input buffer 34 and the input buffer 32 are the same, and reference can be made to fig. 6 for an embodiment of the internal structure of both.
The selection unit 38 has a plurality of outputs connected to the parallel bus 12. The selection unit 38 is respectively connected to the first output terminals of the input buffer 32 and the second output terminals of the input buffer 34 to receive the first digital data and the second digital data. The selection unit 38 is operative to connect a plurality of output terminals thereof to the output buffer 32 or 34 to selectively output the plurality of first digital data or the plurality of second digital data to the parallel bus 12. In other embodiments, the selection unit 38 may be a multiplexer or other logic circuit with the same function.
The control unit 33 is connected to the selection units 36 and 38, and controls the operations of the selection units 36 and 38 according to the serial clock signal, in one embodiment, the control unit 33 controls the switching of the selection units 36 and 38 by counting the number of clocks of the serial clock signal. The control unit 33 connects the input buffers 32 and 34. The control unit 33 controls the input buffer 32 to sequentially store the first digital data to the first storage elements and controls the input buffer 34 to sequentially store the second digital data to the second storage elements according to the serial clock signal.
In one embodiment, the control unit 33 includes one or more Finite State Machines (FSMs) that generate control signals according to the serial clock signal to control the operations of the input buffers 32, 34 and the selection units 36, 38.
The control unit 33 is further connected to the processing unit 11 via the parallel bus 12. In response to the selection unit 38 outputting the first digital data or the second digital data, the control unit 33 sends a notification signal to the processing unit 11 in accordance with the internal clock signal of the processing unit 11. In one embodiment, the control unit 33 sends the notification signal according to the number of clocks of the counting serial clock signal and the internal clock signal. In response to the notification signal, the processing unit 11 receives the data output from the selection unit 38 via the parallel bus 12. In response to the selection unit 38 outputting the first digital data of the input buffer 32, the control unit 33 controls the selection unit 36 to connect to the input buffer 32, so that the next serial data is transmitted to the input buffer 32. In response to the multi-selection unit 38 outputting the second digital data from the input buffer 34, the control unit 33 controls the selection unit 36 to connect to the input buffer 34, so that the next serial data is transmitted to the input buffer 34. The switching of the two input buffers 32 and 34 in conjunction with the selection unit 36 can help to improve the efficiency of data transmission.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A data transmission device of a serial peripheral interface, for converting a first parallel data including a plurality of first digital data into a serial form, and outputting the converted data from a data output terminal of the serial peripheral interface, the data transmission device comprising:
a first output buffer, operating in an internal clock domain corresponding to an internal clock signal, for receiving the first parallel data and outputting the first digital data, wherein the first output buffer has a plurality of first storage elements for storing the first digital data;
a first selection unit having an output end connected to the data output end and a plurality of first input ends for receiving the plurality of first digital data outputted from the first output buffer, the first selection unit being used for selecting one of the plurality of first input ends to be connected to the data output end so as to output one of the plurality of first digital data; and
and the control unit is connected with the first selection unit and controls the first selection unit to output the plurality of first digital data in sequence according to a serial clock signal.
2. The data transmission device of claim 1, further receiving a second parallel data including a plurality of second digital data, the data transmission device further comprising:
a second output buffer, operating in the internal clock domain, for receiving the second parallel data and outputting the second digital data to the first selection unit, wherein the second output buffer has a plurality of second storage elements for storing the second digital data;
a second selection unit, connected to the first output buffer and the second output buffer, for sequentially outputting the first parallel data to the first output buffer and the second parallel data to the second output buffer;
the first selection unit further includes a plurality of second input terminals connected to the second output buffer, the plurality of second input terminals are used for receiving the plurality of second digital data output by the second output buffer, the first selection unit selects one of the plurality of first digital data and the plurality of second digital data to output by selecting one of the plurality of first input terminals and the plurality of second input terminals to be connected to the data output terminal, and the control unit controls the first selection unit to sequentially output the plurality of first digital data and the plurality of second digital data according to the serial clock signal.
3. The data transmitting device of claim 1, wherein the first storage element is a flip-flop having a clock input receiving the internal clock signal.
4. The data transmission apparatus according to claim 2, wherein the second storage element is a flip-flop having a clock input receiving the internal clock signal.
5. The data transmission apparatus of claim 1, wherein the control unit comprises a finite state machine for generating control signals to control the operation of the first selection unit.
6. The data transmission device as claimed in claim 1, wherein the control unit further sends a notification signal in response to the first selection unit outputting the plurality of first digital data in response to the internal clock signal.
7. The data transmission apparatus according to claim 1, wherein the first selection unit is a multiplexer.
8. The data transmission apparatus of claim 2, wherein the second selection unit is a demultiplexer.
9. A data receiving device of a serial peripheral interface, the serial peripheral interface having a data input terminal for receiving a first serial data including a plurality of first digital data, comprising:
a first input buffer having a plurality of first output terminals, the first input buffer being configured to receive the first serial data and output the first digital data from the plurality of first output terminals, wherein the first input buffer has a plurality of first storage elements for storing the first digital data; and
the control unit is connected with the first input buffer and used for controlling the first input buffer to sequentially store the plurality of first digital data to the plurality of first storage elements according to the serial clock signal.
10. The data receiving device of claim 9, wherein the data input of the serial peripheral interface further receives a second serial data comprising a plurality of second digital data, the data receiving device further comprising:
the first selection unit is connected with the first input buffer and used for receiving and outputting the first serial data and the second serial data, and the first selection unit outputs the first serial data to the first input buffer;
a second input buffer connected to the first selection unit and having a plurality of second output terminals, the second input buffer being configured to receive the second serial data outputted from the first selection unit and output the plurality of second digital data via the plurality of second output terminals, the second input buffer having a plurality of second storage elements for storing the plurality of second digital data;
a second selection unit, connected to the first input buffer and the second input buffer, for receiving the first digital data outputted from the first input buffer and the second digital data outputted from the second input buffer, and selecting to output the first digital data or the second digital data;
the control unit controls the second input buffer to sequentially store the second digital data to the second storage elements according to the serial clock signal, and controls the first selection unit and the second selection unit to operate.
11. The data receiving device of claim 9, wherein the first storage element is a flip-flop having a clock input receiving the serial clock signal.
12. The data receiving device of claim 10, wherein the second storage element is a flip-flop having a clock input receiving the serial clock signal.
13. The data receiving device of claim 10, wherein the control unit comprises at least one finite state machine for generating control signals to control the operations of the first selection unit and the second selection unit, respectively.
14. The data receiving device of claim 9, wherein the control unit further sends a notification signal in response to the first input buffer outputting the plurality of first digital data in response to an internal clock signal.
15. The data receiving device of claim 10, wherein the control unit further sends a notification signal in response to the second selection unit outputting the first digital data or the second digital data.
16. The data receiving device of claim 10, wherein the first selecting unit is a demultiplexer.
17. The data receiving device of claim 10, wherein the second selecting unit is a multiplexer.
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| TW106116934A TWI690806B (en) | 2017-05-22 | 2017-05-22 | Data transmitting device and data receiving device for a serial peripheral interface |
| TW106116934 | 2017-05-22 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020133662A1 (en) * | 2001-03-16 | 2002-09-19 | Hugo Cheung | Serial peripheral interface with high performance buffering scheme |
| CN2682480Y (en) * | 2003-12-31 | 2005-03-02 | 上海贝岭股份有限公司 | SPI synchronous serial communication interface circuit integrated in a chip |
| CN1588337A (en) * | 2004-09-15 | 2005-03-02 | 北京中星微电子有限公司 | Serial communiction bus external equipment interface |
| CN101025725A (en) * | 2007-04-12 | 2007-08-29 | 威盛电子股份有限公司 | Serial peripheral interface data transmission method and serial peripheral interface data transmission system |
| US20080183915A1 (en) * | 2007-01-29 | 2008-07-31 | Nec Electronics Corporation | Communication system, communication device and flow control method |
| CN101324873A (en) * | 2008-07-08 | 2008-12-17 | 那微微电子科技（上海）有限公司 | Compatible type non-standard bit wide serial perimeter interface and data transmission method among interfaces |
| CN102023945A (en) * | 2009-09-22 | 2011-04-20 | 鸿富锦精密工业（深圳）有限公司 | Serial peripheral interface bus-based equipment and data transmission method thereof |
| CN102023956A (en) * | 2009-09-23 | 2011-04-20 | 上海摩波彼克半导体有限公司 | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method |
| US20140281651A1 (en) * | 2013-03-14 | 2014-09-18 | Micron Technology, Inc. | Serial peripheral interface and methods of operating same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7082481B2 (en) * | 2003-11-25 | 2006-07-25 | Atmel Corporation | Serial peripheral interface (SPI) apparatus with write buffer for improving data throughput |
| US7546402B2 (en) * | 2005-03-24 | 2009-06-09 | Sunplus Technology Co., Ltd. | Optical storage system comprising interface for transferring data |
| TWI334547B (en) * | 2007-06-07 | 2010-12-11 | Via Tech Inc | System and method for serial peripheral interface data transmission |
| TWI369610B (en) * | 2008-04-25 | 2012-08-01 | Novatek Microelectronics Corp | Serial peripheral interface (spi) circuit and display using the same |
| KR20120055034A (en) * | 2010-11-22 | 2012-05-31 | 삼성전자주식회사 | Apparatus for connecting peripheral device in portable terminal using serial peripheral interface and method for transmitting data |
| CN102163180B (en) * | 2011-01-20 | 2013-02-13 | 电子科技大学 | I2C bus interface circuit module and control method thereof |
| US9471484B2 (en) * | 2012-09-19 | 2016-10-18 | Novachips Canada Inc. | Flash memory controller having dual mode pin-out |
| US9846426B2 (en) * | 2014-07-28 | 2017-12-19 | Computational Systems, Inc. | Parallel digital signal processing of machine vibration data |
-
2017
- 2017-05-22 TW TW106116934A patent/TWI690806B/en active
- 2017-06-07 CN CN201710423029.4A patent/CN108932210B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020133662A1 (en) * | 2001-03-16 | 2002-09-19 | Hugo Cheung | Serial peripheral interface with high performance buffering scheme |
| CN2682480Y (en) * | 2003-12-31 | 2005-03-02 | 上海贝岭股份有限公司 | SPI synchronous serial communication interface circuit integrated in a chip |
| CN1588337A (en) * | 2004-09-15 | 2005-03-02 | 北京中星微电子有限公司 | Serial communiction bus external equipment interface |
| US20080183915A1 (en) * | 2007-01-29 | 2008-07-31 | Nec Electronics Corporation | Communication system, communication device and flow control method |
| CN101025725A (en) * | 2007-04-12 | 2007-08-29 | 威盛电子股份有限公司 | Serial peripheral interface data transmission method and serial peripheral interface data transmission system |
| CN101324873A (en) * | 2008-07-08 | 2008-12-17 | 那微微电子科技（上海）有限公司 | Compatible type non-standard bit wide serial perimeter interface and data transmission method among interfaces |
| CN102023945A (en) * | 2009-09-22 | 2011-04-20 | 鸿富锦精密工业（深圳）有限公司 | Serial peripheral interface bus-based equipment and data transmission method thereof |
| CN102023956A (en) * | 2009-09-23 | 2011-04-20 | 上海摩波彼克半导体有限公司 | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method |
| US20140281651A1 (en) * | 2013-03-14 | 2014-09-18 | Micron Technology, Inc. | Serial peripheral interface and methods of operating same |
Non-Patent Citations (2)
| Title |
|---|
| "DSP多通道缓冲串行口SPI方式的应用";杨光等;《电子产品世界》;20021025;第50-62页 * |
| "Optimal Implementation design and Simulation of Uart Serial Communication Module Based on Vhdl";Radha Krishna AN等;《International Refereed Journal of Engineering and Science (IRJES)》;20140430;第34-41页 * |
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| CN108932210A (en) | 2018-12-04 |
| TW201901460A (en) | 2019-01-01 |
| TWI690806B (en) | 2020-04-11 |
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