CN116737623A - Communication protocol switching method, chip and electronic equipment - Google Patents

Abstract

The application discloses a communication protocol switching method, a chip and electronic equipment, which enable the chip to be compatible with various communication protocols and save the number of interfaces and interface circuits of the chip. The chip comprises: protocol switching circuit, universal interface circuit and n-way digital circuit, n is greater than or equal to 2; the universal interface circuit is an interface circuit which is universal to the transmission requirements of n communication protocols; the protocol switching circuit is used for enabling the n paths of digital circuits to switch and gate under the control of a protocol switching signal, and only one path of digital circuits is in a gating state at the same time; the ith digital circuit is in a gating state, which means that the universal interface circuit is communicated with the subsequent circuit through the ith digital circuit, and at the moment, the chip can externally communicate with the ith communication protocol in the n communication protocols, i=1, 2, … and n.

Description

Communication protocol switching method, chip and electronic equipment

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a communication protocol switching method, a chip, and an electronic device.

Background

To implement compatibility with multiple communication protocols on the same chip, it is generally necessary to increase the number of interfaces, and separately set a corresponding interface circuit for each communication protocol on the chip. For example, SSI (Synchronous Serial Interface ) and IIC (Inter-Integrated Circuit, integrated circuit bus) are common communication protocols, and if a chip needs to switch between these two communication protocols to transmit data, without special processing, four interfaces need to be added to the chip to transmit data (two of the two communication protocols, SSI and IIC, respectively), and an SSI interface circuit and an IIC interface circuit are provided.

However, the above solution can certainly increase the number of interfaces and the number of interface circuits of the chip, and increase the hardware cost of the chip.

Disclosure of Invention

In view of the above, the present application provides a communication protocol switching method, a chip and an electronic device, so that the chip is compatible with multiple communication protocols, and the number of interfaces and interface circuits of the chip is reduced.

A chip, comprising: protocol switching circuit, universal interface circuit and n-way digital circuit, n is greater than or equal to 2;

the universal interface circuit is an interface circuit which is universal to the transmission requirements of n communication protocols;

the protocol switching circuit is used for enabling the n paths of digital circuits to switch and gate under the control of a protocol switching signal, and only one path of digital circuits is in a gating state at the same time;

the ith digital circuit is in a gating state, which means that the universal interface circuit is communicated with the subsequent circuit through the ith digital circuit, and at the moment, the chip can externally communicate with the ith communication protocol in the n communication protocols, i=1, 2, … and n.

Optionally, when n=2, the two digital circuits in the chip are respectively a synchronous serial interface SSI digital circuit and an integrated circuit bus IIC digital circuit.

Optionally, the protocol switching signal is a signal that is output to the protocol switching circuit after the first original signal is processed by the universal interface circuit and the digital circuit in the gating state.

Optionally, the protocol switching circuit includes: a first switch TG1, a second switch TG2, a third switch TG3, a fourth switch TG4, a fifth switch TG5, a sixth switch TG6, and an inverter F1;

each of the six switches TG1 to TG6 has four terminals, and any one of the switches corresponds to the four terminals: when the first terminal of the switch is at a low level and the second terminal of the switch is at a high level, the third terminal of the switch is communicated with the fourth terminal, namely the switch is turned on, otherwise, the switch is turned off;

the third terminal of the first switch TG1 and the third terminal of the third switch TG3 are connected together and then connected to the universal interface circuit;

the second terminal of the first switch TG1, the second terminal of the second switch TG2, the first terminal of the third switch TG3, the first terminal of the fourth switch TG4, the second terminal of the fifth switch TG5, the second terminal of the sixth switch TG6, and the output terminal of the inverter F1 are connected together;

the input end of the inverter F1, the first terminal of the second switch TG2, the fourth terminal of the second switch TG2, the first terminal of the first switch TG1, the second terminal of the fourth switch TG4, the fourth terminal of the fourth switch TG4, the second terminal of the third switch TG3, the first terminal of the fifth switch TG5, and the second terminal of the sixth switch TG6 are connected together;

the fourth terminal of the first switch TG1 is connected to one end of the first digital circuit, the third terminal of the second switch TG2 and the third terminal of the fifth switch TG5 are connected to the other end of the first digital circuit together, the fourth terminal of the third switch TG3 is connected to one end of the second digital circuit, and the third terminal of the fourth switch TG4 and the third terminal of the sixth switch TG6 are connected to the other end of the second digital circuit together; the fourth terminal of the fifth switch TG5 and the fourth terminal of the sixth switch TG6 are connected together and then connected to the post-stage circuit;

the protocol switching signals comprise a first switching signal used for gating the second path of digital circuit and a second switching signal used for gating the first path of digital circuit; initially default gating any one of the digital circuits; the first path of digital circuit outputs low level initially, outputs high level when receiving a first switching signal, and outputs reset to low level after delaying for preset time; the second digital circuit outputs a high level initially, outputs a low level when receiving a second switching signal, and outputs a reset to a high level after delaying for a preset time.

Optionally, the first original signal is a signal that satisfies transmission requirements of the n communication protocols.

Or the protocol switching signal is a signal which is output to the protocol switching circuit after the second original signal is processed by one interface circuit except the general interface circuit on the chip and the judging circuit in the chip; the judging circuit is used for judging the content of the second original signal and outputting a corresponding signal.

Optionally, the protocol switching circuit includes: a first switch TG1, a second switch TG2, a third switch TG3, a fourth switch TG4, and an inverter F1;

each of the four switches TG1 to TG4 has four terminals, and any one of the four switches corresponds to the four terminals: when the first terminal of the switch is at a low level and the second terminal of the switch is at a high level, the third terminal of the switch is communicated with the fourth terminal, namely the switch is turned on, otherwise, the switch is turned off;

the third terminal of the first switch TG1 and the third terminal of the third switch TG3 are connected together and then connected to the universal interface circuit;

the output end of the judging circuit, the second terminal of the first switch TG1, the second terminal of the second switch TG2, the first terminal of the third switch TG3, the first terminal of the fourth switch TG4 and the input end of the inverter F1 are connected together;

the output end of the inverter F1, the first terminal of the second switch TG2, the first terminal of the first switch TG1, the second terminal of the fourth switch TG4, and the second terminal of the third switch TG3 are connected together;

the fourth terminal of the first switch TG1 is connected with one end of the first path of digital circuit, the third terminal of the second switch TG2 is connected with the other end of the first path of digital circuit, the fourth terminal of the third switch TG3 is connected with one end of the second path of digital circuit, and the third terminal of the fourth switch TG4 is connected with the other end of the second path of digital circuit;

the fourth terminal of the second switch TG2 and the fourth terminal of the fourth switch TG4 are connected together and then connected into the post-stage circuit;

the judging circuit outputs a high-level signal when needing to gate the first path of digital circuit; when the second digital circuit needs to be gated, a low level signal is output.

Optionally, the second original signal is a pulse signal that transmits different information with different pulse numbers, or the second original signal is a level signal that transmits different information with a level.

An electronic device, comprising: such as any of the chips disclosed above.

A communication protocol switching method applied to any one of the chips disclosed above;

the method comprises the following steps: receiving an original signal; judging whether the original signal is used for protocol switching, if so, generating and outputting the protocol switching signal.

According to the technical scheme, the interface circuit which can be universally used for transmission requirements of various communication protocols is designed on the chip, and based on the universal interface circuit, the chip is switched to use various communication protocols for external communication, so that the compatibility of various communication protocols on the same chip is realized, the number of interfaces and interface circuits of the chip is saved, and the hardware cost of the chip is reduced.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an internal structure of a chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an internal structure of a chip according to another embodiment of the present application;

FIG. 3 is a schematic diagram of an internal structure of a chip according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a protocol switching circuit applied to the chip shown in FIG. 1;

FIG. 5 is a schematic diagram of a protocol switching circuit applied to the chip shown in FIG. 3;

fig. 6 is a flowchart of a communication protocol switching method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, an embodiment of the present application discloses a chip, including: protocol switching circuit (two parts of protocol switching circuit A and protocol switching circuit B shown in figure 1 form a complete protocol switching circuit), universal interface circuit and n-way digital circuit, n is more than or equal to 2 (only n=2 is taken as an example in figure 1);

the universal interface circuit is an interface circuit which is universal to the transmission requirements of n communication protocols;

the protocol switching circuit is used for enabling the n paths of digital circuits to switch and gate under the control of a protocol switching signal, and only one path of digital circuits is in a gating state at the same time;

the ith digital circuit is in a gating state, which means that the universal interface circuit is communicated with the subsequent circuit through the ith digital circuit, and at the moment, the chip can externally communicate with the ith communication protocol in the n communication protocols, i=1, 2, … and n.

The interface is a port for transmitting data between the host and the chip; an interface circuit is a circuit that processes an input signal of an interface to meet transmission requirements of a certain communication protocol for electrical characteristics. As can be seen from the above description of the embodiment of the present application, in the embodiment of the present application, instead of setting interface circuits for n communication protocols on a chip, an interface circuit capable of being used for transmission requirements of the n communication protocols is designed on the chip, and n digital circuits corresponding to the n communication protocols are switched and gated, so that the chip can switch and use multiple communication protocols to communicate with the outside, specifically:

when the host computer and the chip need to use the 1 st communication protocol in the n communication protocols to transmit data, the host computer is communicated to the post-stage circuit through the interface at the front end of the universal interface circuit, the universal interface circuit and the 1 st digital circuit in sequence; when the host computer and the chip need to use the 2 nd communication protocol in the n communication protocols to transmit data, the host computer is communicated to the post-stage circuit through the interface at the front end of the universal interface circuit, the universal interface circuit and the 2 nd digital circuit in sequence; … …; when the data is required to be transmitted between the host and the chip by using the nth communication protocol in the n communication protocols, the host is communicated to the subsequent circuit sequentially through the interface at the front end of the universal interface circuit, the universal interface circuit and the nth digital circuit.

At this time, the chip adopts the universal interface circuit without setting the interface circuits for n communication protocols, so that the number of the interface circuits and the total number of interfaces of the chip are saved.

In summary, the embodiment of the application designs an interface circuit capable of being universally used for transmission requirements of various communication protocols on a chip, and based on the universal interface circuit, the chip is switched to use various communication protocols for external communication, so that the compatibility of various communication protocols on the same chip is realized, the number of interfaces and interface circuits of the chip is saved, and the hardware cost of the chip is reduced.

For example, to make the chip compatible with two communication protocols, i.e., SSI (Synchronous Serial Interface ) and IIC (Inter-Integrated Circuit, integrated circuit bus), the present application sets n=2, and sets two digital circuits in the chip to be IIC digital circuit and SSI digital circuit, respectively, as shown in fig. 2. The specific analysis is as follows:

IIC is a bi-directional two-wire synchronous Serial bus developed by Philips, and requires only two wires to communicate, SCL (Serial Clock Line ) and SDA (Serial Data Line), respectively.

SSI is a protocol for counting clock pulses, and its communication principle is: inputting a section of clock pulse, storing the clock pulse into a shift register and converting the clock pulse into binary numbers; after the pulse number is input, a high input signal is set for a period of time, and a reset signal is triggered to transmit binary numbers in the shift register, then the shift register is cleared, and different pulse numbers can be sequentially sent to the chip for configuration according to the rule.

IIC communication protocols are commonly used for host configuration chips or reading chip states, and SSI communication protocols are commonly used for host configuration chip states. The chip may only need to use the SSI communication protocol during normal operation, but because the SSI communication protocol cannot read the state of the chip, the IIC communication protocol needs to be used when the chip needs to be tested or debugged. In the prior art, in order to realize that a chip is compatible with two communication protocols, namely SSI and IIC, two interfaces are arranged on the chip for the SSI communication protocol, an SCL interface and an SDA interface are arranged for the IIC communication protocol, and an SSI interface circuit, an IIC interface circuit, an SSI digital circuit and an IIC digital circuit are arranged at the same time; when the host transmits data to the IIC interface circuit through the SCL interface and the SDA interface, the IIC digital circuit realizes that the host configures a chip or reads the state of the chip; when the host transmits data to the SSI interface circuit through two interfaces provided for the SSI, the SSI digital circuit realizes the state of the host configuration chip.

In order to enable the chip to be compatible with two communication protocols of SSI and IIC, the embodiment of the application adopts an interface circuit which simultaneously meets the transmission requirements of the two communication protocols of SSI and IIC as a universal interface circuit, and based on the universal interface circuit, the chip can switch between using the SSI and IIC communication protocols to communicate externally without setting the interface circuits for the two communication protocols of SSI and IIC respectively, thereby saving the number of the interface circuits; in addition, the chip adopts a general interface circuit, and the interface circuits are not required to be respectively arranged for the SSI and the IIC communication protocols, so that the total number of interfaces is reduced, and the original need of four interfaces to transmit data is changed into the need of two interfaces to transmit data.

Alternatively, in any of the embodiments disclosed above, the protocol switching signal may be input through a different path. For example, the protocol switching signal may be a signal (hereinafter referred to as "a signal input through a first path") that is output to the protocol switching circuit after the first original signal is processed by the universal interface circuit and the digital circuit in the gating state; the processing content of the digital circuit in the gating state is mainly to judge the content of the first original signal, including judging whether the first original signal is a signal for protocol switching and which communication protocol is to be switched. For another example, as shown in fig. 3, the protocol switching signal may be a signal (hereinafter referred to as "a signal input through a second path") that is output to the protocol switching circuit after the second original signal is processed by an interface circuit on the chip other than the general interface circuit and a judging circuit in the chip; the judging circuit is used for judging the content of the second original signal, and comprises judging whether the second original signal is a signal for protocol switching and which communication protocol is to be switched to, and outputting a corresponding signal.

In one embodiment, when the protocol switching signal is a signal input through a first path and n=2, as shown in fig. 4, the protocol switching circuit includes: a first switch TG1, a second switch TG2, a third switch TG3, a fourth switch TG4, a fifth switch TG5, a sixth switch TG6, and an inverter F1;

each switch in the protocol switching circuit is provided with four terminals, and when the first terminal of the switch is at a low level 0 and the second terminal of the switch is at a high level 1, the third terminal of the switch is communicated with the fourth terminal, namely the switch is on, and otherwise, the switch is off;

the third terminal of the first switch TG1 and the third terminal of the third switch TG3 are connected together and then connected into the universal interface circuit;

the second terminal of the first switch TG1, the second terminal of the second switch TG2, the first terminal of the third switch TG3, the first terminal of the fourth switch TG4, the second terminal of the fifth switch TG5, the second terminal of the sixth switch TG6, and the output terminal of the inverter F1 are connected together;

the input terminal of the inverter F1, the first terminal of the second switch TG2, the fourth terminal of the second switch TG2, the first terminal of the first switch TG1, the second terminal of the fourth switch TG4, the fourth terminal of the fourth switch TG4, the second terminal of the third switch TG3, the first terminal of the fifth switch TG5, and the second terminal of the sixth switch TG6 are connected together;

the fourth terminal of the first switch TG1 is connected with one end of the first path of digital circuit, the third terminal of the second switch TG2 and the third terminal of the fifth switch TG5 are commonly connected with the other end of the first path of digital circuit, the fourth terminal of the third switch TG3 is connected with one end of the second path of digital circuit, and the third terminal of the fourth switch TG4 and the third terminal of the sixth switch TG6 are commonly connected with the other end of the second path of digital circuit; the fourth terminal of the fifth switch TG5 and the fourth terminal of the sixth switch TG6 are connected together and then connected to the post-stage circuit.

The protocol switching signals include a first switching signal for gating the second path digital circuit and a second switching signal for gating the first path digital circuit. Initially default gating any one of the digital circuits; the first path of digital circuit outputs low level 0 initially, outputs high level 1 when receiving a first switching signal, and outputs reset to low level 0 after delaying for a preset time; the second digital circuit outputs a high level 1 initially, outputs a low level 0 when receiving a second switching signal, and outputs a reset to the high level 1 after delaying for a preset time.

For example, the first digital circuit is initially gated by default, TG5, TG1 and TG2 are turned on, TG6, TG3 and TG4 are turned off, the first digital circuit initially outputs low level 0, and the second digital circuit initially outputs high level 1; when the second path of digital circuit needs to be switched and gated, the host controls the first path of digital circuit to output high level 1 through the universal interface circuit and simultaneously gives a delay reset signal to the first path of digital circuit, at the moment, TG5, TG1 and TG2 are turned off, TG6, TG3 and TG4 are turned on, and after a period of delay, the signal output by the first path of digital circuit is reset to 0. When the second path digital circuit is required to be switched back to gate, the host controls the output of the second path digital circuit to be set to 0 through the universal interface circuit and simultaneously gives a delay reset signal to the second path digital circuit, then TG5, TG1 and TG2 are conducted, TG6, TG3 and TG4 are not conducted, and after a period of delay, the signal output by the second path digital circuit is reset to 1.

When the protocol switching signal is a signal input through a first path, the first original signal is a signal satisfying transmission requirements of the n communication protocols.

In still another embodiment, when the protocol switching signal is a signal input through a second path and n=2, as shown in fig. 5, the protocol switching circuit includes: a first switch TG1, a second switch TG2, a third switch TG3, a fourth switch TG4, and an inverter F1;

each switch in the protocol switching circuit is provided with four terminals, and when the first terminal of the switch is at a low level and the second terminal of the switch is at a high level, the third terminal of the switch is communicated with the fourth terminal, namely the switch is on, and otherwise, the switch is off;

the third terminal of the first switch TG1 and the third terminal of the third switch TG3 are connected together and then connected into the universal interface circuit;

the output end of the judging circuit, the second terminal of the first switch TG1, the second terminal of the second switch TG2, the first terminal of the third switch TG3, the first terminal of the fourth switch TG4 and the input end of the inverter F1 are connected together;

the output terminal of the inverter F1, the first terminal of the second switch TG2, the first terminal of the first switch TG1, the second terminal of the fourth switch TG4, and the second terminal of the third switch TG3 are connected together;

the fourth terminal of the first switch TG1 is connected with one end of the first path of digital circuit, the third terminal of the second switch TG2 is connected with the other end of the first path of digital circuit, the fourth terminal of the third switch TG3 is connected with one end of the second path of digital circuit, and the third terminal of the fourth switch TG4 is connected with the other end of the second path of digital circuit;

the fourth terminal of the second switch TG2 and the fourth terminal of the fourth switch TG4 are connected together and then connected to the post-stage circuit.

The judging circuit outputs a high-level signal when needing to gate the first path of digital circuit; when the second digital circuit needs to be gated, a low level signal is output.

In fig. 5, the host inputs a second original signal to the interface circuit, the judging circuit judges whether the second original signal outputs a high level or a low level, when the judging circuit outputs a high level 1, the first switch TG1 and the second switch TG2 are turned on, the third switch TG3 and the fourth switch TG4 are turned off, and the first digital circuit is turned on; when the judging circuit outputs low level 0, the first switch TG1 and the second switch TG2 are turned off, the third switch TG3 and the fourth switch TG4 are turned on, and the second digital circuit is turned on.

When the protocol switching signal is a signal input through a second path, the second original signal may be a pulse signal that transfers different information in different pulse numbers, or the second original signal may be a level signal that transfers different information in a level height.

In addition, the embodiment of the application also discloses an electronic device, which comprises: such as any of the chips disclosed above.

In addition, the embodiment of the application also discloses a communication protocol switching method which is applied to any chip disclosed above; as shown in fig. 6, the method includes:

step S01: receiving an original signal;

when the protocol switching signal is a signal input through the first path, the original signal is the first original signal; when the protocol switching signal is a signal input through the second path, the original signal is the second original signal.

Step S02: judging whether the original signal is used for protocol switching, if so, entering step S03; if not, executing other operations.

Step S03: and generating and outputting the protocol switching signal.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple as it corresponds to the chip disclosed in the embodiment, and the relevant points are only referred to the chip part.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar different objects and not necessarily for describing a particular sequential or chronological order. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments of the application. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A chip, comprising: protocol switching circuit, universal interface circuit and n-way digital circuit, n is greater than or equal to 2;

the universal interface circuit is an interface circuit which is universal to the transmission requirements of n communication protocols;

the protocol switching circuit is used for enabling the n paths of digital circuits to switch and gate under the control of a protocol switching signal, and only one path of digital circuits is in a gating state at the same time;

the ith digital circuit is in a gating state, which means that the universal interface circuit is communicated with the subsequent circuit through the ith digital circuit, and at the moment, the chip can externally communicate with the ith communication protocol in the n communication protocols, i=1, 2, … and n.

2. The chip of claim 1, wherein when n=2, the two digital circuits in the chip are a synchronous serial interface SSI digital circuit and an integrated circuit bus IIC digital circuit, respectively.

3. The chip according to claim 1 or 2, wherein the protocol switching signal is a signal that is output to the protocol switching circuit after the first original signal is processed by the universal interface circuit and the digital circuit in the gating state.

4. The chip of claim 3, wherein the protocol switching circuit comprises: a first switch (TG 1), a second switch (TG 2), a third switch (TG 3), a fourth switch (TG 4), a fifth switch (TG 5), a sixth switch (TG 6), and an inverter (F1);

each of the six switches of the first switch (TG 1) to the sixth switch (TG 6) has four terminals, and any one of the switches corresponds to: when the first terminal of the switch is at a low level and the second terminal of the switch is at a high level, the third terminal of the switch is communicated with the fourth terminal, namely the switch is turned on, otherwise, the switch is turned off;

a third terminal of the first switch (TG 1) and a third terminal of the third switch (TG 3) are connected together and then connected into the universal interface circuit;

-the second terminal of the first switch (TG 1), the second terminal of the second switch (TG 2), the first terminal of the third switch (TG 3), the first terminal of the fourth switch (TG 4), the second terminal of the fifth switch (TG 5), the second terminal of the sixth switch (TG 6) and the output of the inverter (F1) are connected together;

-the input of the inverter (F1), the first terminal of the second switch (TG 2), the fourth terminal of the second switch (TG 2), the first terminal of the first switch (TG 1), the second terminal of the fourth switch (TG 4), the fourth terminal of the fourth switch (TG 4), the second terminal of the third switch (TG 3), the first terminal of the fifth switch (TG 5) and the second terminal of the sixth switch (TG 6) are connected together;

the fourth terminal of the first switch (TG 1) is connected with one end of a first path of digital circuit, the third terminal of the second switch (TG 2) and the third terminal of the fifth switch (TG 5) are commonly connected with the other end of the first path of digital circuit, the fourth terminal of the third switch (TG 3) is connected with one end of the second path of digital circuit, and the third terminal of the fourth switch (TG 4) and the third terminal of the sixth switch (TG 6) are commonly connected with the other end of the second path of digital circuit; a fourth terminal of the fifth switch (TG 5) and a fourth terminal of the sixth switch (TG 6) are connected together and then connected into the rear-stage circuit;

the protocol switching signals comprise a first switching signal used for gating the second path of digital circuit and a second switching signal used for gating the first path of digital circuit; initially default gating any one of the digital circuits; the first path of digital circuit outputs low level initially, outputs high level when receiving a first switching signal, and outputs reset to low level after delaying for preset time; the second digital circuit outputs a high level initially, outputs a low level when receiving a second switching signal, and outputs a reset to a high level after delaying for a preset time.

5. A chip according to claim 3, wherein the first original signal is a signal satisfying transmission requirements of the n communication protocols.

6. The chip according to claim 1 or 2, wherein the protocol switching signal is a signal which is output to the protocol switching circuit after the second original signal is processed by an interface circuit on the chip other than the general interface circuit and a judging circuit in the chip; the judging circuit is used for judging the content of the second original signal and outputting a corresponding signal.

7. The chip of claim 6, wherein the protocol switching circuit comprises: a first switch (TG 1), a second switch (TG 2), a third switch (TG 3), a fourth switch (TG 4), and an inverter (F1);

each of the four switches, the first switch (TG 1) to the fourth switch (TG 4), has four terminals, and any one of the four switches corresponds to the four terminals: when the first terminal of the switch is at a low level and the second terminal of the switch is at a high level, the third terminal of the switch is communicated with the fourth terminal, namely the switch is turned on, otherwise, the switch is turned off;

a third terminal of the first switch (TG 1) and a third terminal of the third switch (TG 3) are connected together and then connected into the universal interface circuit;

the output end of the judging circuit, the second terminal of the first switch (TG 1), the second terminal of the second switch (TG 2), the first terminal of the third switch (TG 3), the first terminal of the fourth switch (TG 4) and the input end of the inverter (F1) are connected together;

-the output of the inverter (F1), the first terminal of the second switch (TG 2), the first terminal of the first switch (TG 1), the second terminal of the fourth switch (TG 4) and the second terminal of the third switch (TG 3) are connected together;

the fourth terminal of the first switch (TG 1) is connected with one end of a first path of digital circuit, the third terminal of the second switch (TG 2) is connected with the other end of the first path of digital circuit, the fourth terminal of the third switch (TG 3) is connected with one end of a second path of digital circuit, and the third terminal of the fourth switch (TG 4) is connected with the other end of the second path of digital circuit;

a fourth terminal of the second switch (TG 2) and a fourth terminal of the fourth switch (TG 4) are connected together and then connected into the rear-stage circuit;

the judging circuit outputs a high-level signal when needing to gate the first path of digital circuit; when the second digital circuit needs to be gated, a low level signal is output.

8. The chip of claim 6, wherein the second original signal is a pulse signal that transmits different information in different pulse numbers, or the second original signal is a level signal that transmits different information in level steps.

9. An electronic device, comprising: the chip of any one of claims 1 to 8.

10. A communication protocol switching method, characterized by being applied to the chip according to any one of claims 1 to 8;

the method comprises the following steps: receiving an original signal; judging whether the original signal is used for protocol switching, if so, generating and outputting the protocol switching signal.