JP3893873B2 - Duplex processor entanglement system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a duplex processor entanglement system, and more particularly, to a duplex processor that exchanges data with each other and compares the received data from the other side with its own data to make a coincidence determination between duplex processor cards that are clock synchronous operation systems. It concerns the confounding system.
[0002]
[Prior art]
Such a processor that is duplicated by clock synchronous operation generally achieves clock edge matching by referring to the operation clocks in the processor card, and the CPU operation from the bus clock in the processor card. Synchronize everything up to the clock. This makes it possible to perform a duplex operation by synchronizing the traveling command at the clock level.
[0003]
In such a duplex processor, the bus of the inter-processor entanglement unit is also synchronized with the bus clock in the processor card at the same frequency, and the operation at the same clock edge is realized. The access from the active processor and the access from the standby processor are checked by the coincidence check circuit, and if they match, the access is accepted as a valid access.
[0004]
An example of such a dual processor system according to the prior art is shown in FIG. In FIG. 4, the 0-system processor card pc11 is considered as the active system and the 1-system processor card pc12 as the standby system. Each of the processor cards pc11 and pc12 includes processors p1 and p2, bus drivers d11 and d12, bus receivers d13 and d14, and coincidence check circuits c1 and c2.
[0005]
The process cards are connected by interlace buses b11 and b12. The processor p1 and the processor p2 operate with synchronized clocks, and access from the processor p2 is input to the match check circuit c1 in the processor card pc11 via the bus driver d12 and the bus receiver d13. A match check with the access from p1 is performed. After the check, if the two match, it is accepted as a normal access.
[0006]
[Problems to be solved by the invention]
However, in the conventional technique shown in FIG. 4, the operating frequency of the bus in the processor card is also limited by the clock frequency of the entanglement bus unit between the duplex processor cards. In general, the signal frequency at the time of signal transmission of the back wiring board connecting the cards is lower than the signal frequency at the time of signal transmission in the card because the distance of the transmission path becomes longer. For this reason, the processing capability of the duplex processor card is limited by the signal frequency at the time of signal transmission of the back wiring board.
[0007]
Specific problems include the problem that the data transfer rate from the CPU using the processor entanglement bus to the input / output interface and the data transfer rate from the input / output interface to the memory cannot be increased, and the standby system (SBY system). There is a problem that it takes a long time to copy the memory when it is installed in service.
[0008]
In addition, to increase the data transfer capability of inter-processor entanglement, the number of signals increases to increase the number of buses, and the performance of the processor is prevented by using a buffer circuit or the like while maintaining the data transfer capability of inter-processor entanglement. This causes a problem of an increase in the number of parts.
[0009]
If a parallel bus with an increased number of buses is used for high-speed data transfer of the back wiring board, the influence of the difference in wiring length of each signal line is large, and it is difficult to increase the data speed.
[0010]
It is an object of the present invention to improve the performance of a duplex processor by using a serial link having a high data transfer capability for an interprocessor interlacing unit in a clock synchronous duplex processor to improve the transfer capability of the interprocessor intermingling unit. Another object of the present invention is to provide a dual processor entanglement system capable of reducing the number of parts by reducing the number of signals and downsizing the buffer circuit.
[0011]
[Means for Solving the Problems]
According to the present invention, there is provided a duplex processor entanglement system in which data is mutually exchanged between duplex processor cards having a clock synchronous operation method, and the received data from the other is compared with its own data to make a coincidence determination. A serial link that exchanges data between the duplex processor cards, a synchronization signal transmission / reception circuit that is provided in each of the processor cards and that synchronizes the transfer data of the serial link, and A first buffer circuit which is provided in each of the first buffer circuits, which is sequentially written and controlled to be read out by a read timing signal, and which is provided in each of the processor cards and which sequentially writes the received data via the serial link and the read timing signal; A second buffer circuit controlled to read out by The synchronization signal transmission / reception circuit generates a low-speed clock that is synchronized with an operation clock in the processor card and sends it to the other processor card, and receives the low-speed clock to receive the low-speed clock. redundant processor entangled system and having a synchronization timing generator circuit for generating the read timing signal for the first and second buffer circuits are obtained.
[0012]
The serial link includes a parallel / serial conversion circuit for parallel / serial conversion of the own data and sending the converted data to a counterpart processor card, and a serial / parallel conversion circuit for serial / parallel conversion of the received data from the counterpart processor card; The output data of the serial / parallel conversion circuit is written to the second buffer circuit.
[0013]
The synchronization timing generation circuit generates the read timing signal in consideration of a delay time corresponding to a total value of the operation delay times of the parallel / serial conversion circuit, the serial / parallel conversion circuit, and the serial link. It is characterized by doing so.
[0014]
The first and second buffer circuits are FIFO type memory circuits, and read data from the memory circuit is output to a coincidence check circuit, and the first buffer circuit writes the self data. It has a timer which starts at the timing and stops at the read timing signal, and reports the fact to the coincidence check circuit when the timer times out.
[0015]
The operation of the present invention will be described. The dual processor entanglement system according to the present invention is characterized in that the transfer capability is improved by using a serial link in the interprocessor entanglement section. In general, the serial link receives parallel data as input and multiplexes and outputs the serial data signal, and converts the input serial data into parallel data and outputs it. In the present invention, this serial link is used. . In this case, such a serial link generally includes a PLL (phase locked loop) circuit, and outputs a serial data signal including a clock component from the transmitting device, and the receiving device receives the data signal component from the received serial data signal. And the clock component are extracted, and there is a problem that the parallel signals of the respective devices become asynchronous with each other.
[0016]
Therefore, in the present invention, in addition to the serial signal transmission / reception circuit, the synchronization pulse transmission / reception circuit and the parallel signal synchronization buffer circuit controlled by the synchronization pulse are used, so that the parallel data signal transmitted by the serial link is transmitted. We are trying to achieve synchronization.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In order to clarify the objects, features, and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals.
[0018]
Referring to FIG. 1, in addition to the processors p1 and p2 and the coincidence check circuits c1 and c2, the duplex processor entanglement system includes parallel / serial conversion circuits ps21 and ps22 for realizing the entanglement of the duplex processor, Parallel conversion circuits sp21, sp22, buffer circuits bf21, bf22, bf23, bf24, pulse generation circuits pg21, pg22, and synchronization timing generation circuits t21, t22 are provided, and each processor card pc1, pc2 is a serial link s21. , S22 and pulse signal lines pl21, pl22.
[0019]
The parallel / serial conversion circuits ps21 and ps22 serially convert accesses from the processors p1 and p2, and output the converted data to the mate (partner) processor cards pc21 and pc22 via the serial links s21 and s22. The pulse generation circuits pg21 and pg22 output timing pulses to the mate processor cards pc22 and pc21 via the pulse signal lines pl21 and pl22 in synchronization with the serial signal output. Since the timing pulse signal lines pl21 and pl22 connect the processor cards pc21 and pc22, the timing pulse signal lines pl21 and pl22 operate at a slower clock synchronized with the operation clock in the processor cards pc21 and pc22. The serial signals s22 and s21 from the mates are restored to parallel signals by the serial / parallel conversion circuits sp21 and sp22.
[0020]
On the other hand, access from the processors p1 and p2 waits for access from the mate processor card in the buffer circuits bf21 and bf22. Access from the mate processor card is restored to a parallel signal, and then converted into clocks by the buffer circuits bf23 and bf24.
[0021]
The synchronization timing generation circuits t21 and t22 generate timing pulses for activating the buffer circuit by signals from the pulse signal lines pl22 and pl21, and input them to the buffer circuits bf21 and bf23 and the buffer circuits bf22 and bf24. The buffer circuits bf21, bf22, bf23, bf24 output accesses from the processors p1, p2 to the coincidence check circuits c1, c2 by the timing pulse signals tp21, tp22 from the synchronization timing generation circuits t21, t22.
[0022]
The coincidence check circuits c1 and c2 check the coincidence of accesses from both processors p1 and p2. If they match after the check, the access is accepted as normal. The buffer circuits bf21, bf22, bf23, bf24 have a FIFO (First-In-First-Out) configuration in which the stored data is read out and output by the timing signals tp21, tp22 generated by the synchronization timing generation circuits t21, t22.
[0023]
It should be noted that the processor of FIG. 1 and the coincidence check circuit are well known to those skilled in the art and are not directly related to the present invention.
[0024]
The operation of the configuration of FIG. 1 will be described below using the timing chart of FIG. The processor c1 and the processor c2 operate with synchronized clocks, and in describing the operation of the present embodiment, it is assumed that the 0-system processor card pc21 is an active system and the 1-system processor card pc22 is a standby system. To do.
[0025]
Access from the processor p2 is shown in the processor p2 signal output, and access from the processor p1 operating in synchronism is shown in the processor p1 signal output. Since the operations of the processors p1 and p2 have the same clock edge timing, the output signals from the processors p1 and p2 have the same timing. When the processor p2 signal output is converted into a serial signal by the parallel / serial conversion circuit ps22, a delay time d1 due to the conversion of the asynchronous clock is generated. When the converted serial signal s22 is input to the serial / parallel conversion circuit sp21 of the 0-system processor card pc21, a delay time d2 due to wiring is generated. Even when the serial / parallel conversion circuit sp21 converts the signal into a parallel signal, a delay time d3 occurs.
[0026]
Further, the pulse signal pl22 output generated by the pulse generation circuit pg22 in response to the processor p2 output signal reaches the 0-system processor card pc21 with the wiring delay d4. The pulse signal pl22 is a signal operation clock with a delay of one clock. The synchronization timing generation circuit t21 is reached. The synchronization timing generation circuit t21 outputs the timing pulse signal tp21 to the buffer circuits bf21 and bf23 with a delay d5 synchronized with the clock in the processor card pc21 considering the delay generated in the serial / parallel conversion circuit sp21 and the buffer circuit bf23.
[0027]
The buffer circuits bf21 and bf23 output accesses from the respective processors p1 and p2 to the coincidence check circuit at the timing of the timing pulse signal tp21. The coincidence check circuit c1 performs a coincidence check between the access from the processor p1 and the access from the processor p2. After checking, if they match, it is accepted as normal access.
[0028]
Each of the buffer circuits has a timer (not shown) that is activated by receiving (writing) in its own processor card and stopped by timing signals tp21 and tp22 from the synchronous timing generation circuits t21 and t22. In the case of a failure such as the absence of a pulse signal due to a failure of the mate processor card, for example, the timer does not generate the synchronization timing signals tp21 and tp22, and the timer is over, and the match check circuit c1, It is assumed that a notification signal is output to notify c2 of that fact. This makes it possible to avoid the influence of other system failures.
[0029]
As another embodiment of the present invention, the basic configuration is as described above, but the invention further devise to reduce the number of confounding signals between processor cards and the circuit scale. The structure is shown in FIG. 3, and the same part as FIG. 1 is shown with the same code | symbol. In FIG. 3, timing generation circuits tg31 and tg32 are provided instead of the pulse generation circuits pg21 and pg22 and the synchronous timing generation circuits t21 and t22 of FIG.
[0030]
The timing generation circuits tg31 and tg32 are composed of a delay d1 generated by the parallel / serial conversion circuits ps21 and ps22, a delay d2 generated by the serial signals s21 and s22, a serial / parallel conversion circuit sp21 and sp22, and buffer circuits bf23 and bf24. The timing signals tp31 and tg32 that are generated in synchronism with the operation clock in the processor cards pc21 and pc22 are generated by adding the delay time d3 generated by the above.
[0031]
The pulse generation circuits pg21 and pg22 and the synchronous timing generation circuits t21 and t22 shown in FIG. 1 can be replaced by the timing generation circuits tg31 and tg32.
[0032]
Further, it is possible to omit the pulse signals pl21 and pl22 connecting the two processor cards pc21 and pc22, and the effect of further reducing the number of interlaced signals between the processor cards and reducing the circuit scale can be obtained. In this configuration, since the timing generation circuits tg31 and tg32 can generate the timing pulses tp31 and tp32 regardless of the state of the standby processor card, the active processor card can be used even when there is no pulse signal input due to a failure of the standby processor card. The effect of not stopping is obtained.
[0033]
In the timing chart of the figure, the pulse signal pl22 is output in one-to-one correspondence with the serial signal s22, and this pulse signal pl22 is slower than the operation clock in the processor card. The clock pulse is actually a low-speed pulse having a period that is an even multiple of the operation clock. In FIG. 2, the buffer circuit bf21 signal output is supplied to the check circuit c1 with a slight delay from the timing pulse tp21. This is because each buffer circuit is activated after the timing pulse tp21 is generated. Since data is read out from the FIFO, the data is drawn with a delay corresponding to the data.
[0034]
In the above embodiment, the data passed between the duplex processors is shown as access, but the present invention is not limited to this, and various instructions and data may be used. It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.
[0035]
【The invention's effect】
As described above, according to the present invention, the signal of the back wiring board that connects the cards by using the serial link, the synchronization pulse circuit, and the synchronization buffer circuit in the interlace bus section between the duplex processor cards. The effect of signal frequency during transmission can be reduced, the data transfer speed from the CPU using the processor entanglement bus to the input / output interface and the data transfer speed from the input / output interface to the memory can be improved. The memory copy time can be shortened. In addition, the number of signals for inter-processor entanglement can be reduced, and the buffer circuit etc. possessed by the existing circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the block of FIG. 1;
FIG. 3 is a block diagram of another embodiment of the present invention.
FIG. 4 is a block diagram for explaining the prior art.
[Explanation of symbols]
pc21, pc22 processor card p1, p2 processor ps21, ps22 serial / parallel conversion circuit pg21, pg22 pulse generation circuit bf21, bf22,
bf23, bf24 buffer circuit c1, c2 coincidence check circuit sp21, sp22 serial / parallel conversion circuit t21, t22 synchronization timing generation circuit tg31, tg32 timing generation circuit

Claims (5)

A duplex processor entanglement system in which data is exchanged between the duplex processor cards that have been set to the clock synchronous operation system, and the received data from the other is compared with its own data to make a coincidence determination,
A serial link for transferring data between the duplex processor cards; and
A synchronization signal transmission / reception circuit provided in each of the processor cards for synchronizing the transfer data of the serial link;
A first buffer circuit that is provided in each of the processor cards, and that sequentially writes the own data and is controlled to be read by a read timing signal;
A second buffer circuit provided in each of the processor cards, sequentially writing the received data via the serial link and reading-controlled by the read timing signal;
The synchronization signal transmitting / receiving circuit includes:
A pulse generation circuit that generates a lower-speed clock in synchronization with an operation clock in the processor card and sends the clock to the other processor card;
A duplex processor entanglement system comprising: a synchronous timing generation circuit that receives the low-speed clock and generates the read timing signal for the first and second buffer circuits. The serial link is
A parallel / serial conversion circuit for parallel / serial conversion of the own data and sending it to a counterpart processor card;
A serial / parallel conversion circuit for serial / parallel conversion of the received data from the counterpart processor card;
2. The dual processor entanglement system according to claim 1, wherein the output data of the serial / parallel conversion circuit is written to the second buffer circuit. The synchronization timing generation circuit generates the read timing signal in consideration of a delay time corresponding to a total value of the operation delay times of the parallel / serial conversion circuit, the serial / parallel conversion circuit, and the serial link. The duplex processor entanglement system according to claim 2, wherein:   4. The dual processor entanglement system according to claim 1, wherein the first and second buffer circuits are FIFO type storage circuits, and read data from the storage circuit is output to a coincidence check circuit.   The first buffer circuit has a timer that starts at the write timing of the own data and stops at the read timing signal, and reports that fact to the match check circuit when the timer times out. The duplex processor entanglement system according to claim 4.

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