KR100651888B1 - Apparatus and method for asynchronous interfacing - Google Patents

Abstract

An asynchronous interface device and a method thereof are provided to support smooth communication between an asynchronous switch and a synchronous IP(Intellectual Property) forming an SoC(System on Chip). An output interface(231) outputs a control signal representing data is transferred simultaneously with interfacing data transfer to a switch module(210) from a local synchronous IP module(220). An input interface(232) outputs the control signal representing the data is transferred simultaneously with interfacing the data transfer to the local synchronous IP module from the switch module. A local clock generator(233) stops an operation of the local synchronous IP module by stopping generation of a clock provided to the local synchronous IP module if at least one of the control signals output from the input and the output interface represents that the data is transferred.

Description

Apparatus and method for asynchronous interfacing

1 is a conceptual diagram of a typical NoC

2 is a configuration block diagram of a Noc including an asynchronous interface device according to the present invention;

3A and 3B are flowcharts illustrating examples of an operation of the output interface unit and the input interface unit of FIG. 2.

4 is a detailed circuit diagram illustrating an embodiment of the asynchronous interface device of FIG. 2.

5A through 5C show an example of detailed circuit and operation of element C of FIG.

6A and 6B illustrate examples of detailed circuits and operations of the local clock generator according to the present invention.

Explanation of symbols for main parts of the drawings

210: connection module 220: IP module

230: asynchronous interface device 231: output interface unit

232: input interface unit 233: clock generator

611: Noah gate 612: selection

613: clock control unit 614: odd inverter chain

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a System on Chip (SoC), and more particularly, to an interface device and a method between a switch in an SoC and an IP (Intellectual Property).

The System on Chip (SoC) may be regarded as a semiconductor integrated circuit in which main functions of the system are integrated on one chip. The SoC includes all the hardware and software features that make up the system, including memory, processors, external interfaces, analog and mixed-mode blocks, embedded software, and operating systems.

In the SoC, it is common to have an interconnection structure in which all components share a single bus so as to communicate with each other. In this case, a communication speed between the components is slow. In addition, the signal transmission from one component to another component is not only transmitted to a specific component but to all components, so power consumption is disadvantageous. In addition, although 8 to 10 components are mounted and used in one chip, there is a need to expand the structure of the chip to mount 50 to 100 components in the future. In this case, as the number of components connected to the bus sharing structure increases, the load increases and the transmission speed between the components decreases. Therefore, the bus structure is used to determine the number of components included in one chip. It is impossible to increase indefinitely.

As such, the SoC adopts a bus structure for interconnection between components, but there are problems such as scalability, delay in data transmission, and limited bandwidth, and bottlenecks. . In addition, since a plurality of bus masters compete to gain control of the bus, as the number of bus masters increases, data transmission delay increases and performance decreases, and the performance of the bus is a component, that is, an IP (Core) core Because it is determined by, it is impossible to make the best use of the bus performance. In addition, since the switching using the current bus structure is implemented synchronously, the use of a clock is essential and a problem thereof cannot be ruled out.

In order to solve the problem of the SoC bus structure, NoC, a platform in which a connection between components in the SoC is networked using a switch, has been proposed. In other words, the NoC is a substructure of the SoC.

The NoC has the scalability to easily add new components to the network while maintaining a large bandwidth for reasons suitable for SoC design. At this time, by using the same network protocol for each component, hardware / software for implementing the same can be reused. .

FIG. 1 is a general conceptual diagram of a NoC and shows an example of a 2-D mesh structure. The NoC is defined as a structure in which each IP of the SoC is interconnected by a switch, and each node includes one IP and one switch.

At this time, if the switch is an asynchronous method and the IP is a synchronous method, an interface circuit between the switch and the IP is required to support smooth communication between the synchronous IPs through the asynchronous switch.

Accordingly, an object of the present invention is to provide an asynchronous interface device and method for supporting smooth communication between an asynchronous switch constituting the NoC and a synchronous IP.

In order to achieve the above object, the asynchronous interface device according to the present invention indicates that the data transmission from the IP module to the connection module and at the same time during the data transmission to perform the communication between the synchronous IP module through the asynchronous connection module An output interface unit for outputting a control signal; An input interface unit for interfacing data transmission from the connection module to the IP module and outputting a control signal indicating that data is being transmitted; And a clock generator for stopping the operation of the IP module by stopping the generation of the clock provided to the IP module when at least one control signal of the output interface unit and the input interface unit is transmitting data. .

The clock generator comprises a logic unit for combining the control signal of the output interface and the control signal of the input interface unit; A selection unit receiving the output of the logic unit as one input and a selection signal; A clock control unit for generating a normal clock when the output of the selection unit is 0 and not generating a clock; And an odd number of inverters in series, and an odd inverter chain which inverts the output of the clock control unit and provides the input to the other input and the clock control unit of the selection unit.

The asynchronous interface method of interfacing the asynchronous connection module and the corresponding IP module to perform the communication between the synchronous IP modules through the asynchronous connection module in the SoC according to the present invention simultaneously interface the data transmission from the IP module to the connection module. An output interface step of outputting a control signal indicating that data is being transmitted; An input interface step of interfacing data transmission from the connection module to an IP module and outputting a control signal indicating that data is being transmitted; And stopping operation of the IP module by stopping a clock generation provided to the IP module when at least one control signal of the output and input interface steps indicates that data is being transmitted.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

2 shows a relationship between a connection module and an IP module of each node in the NoC according to the present invention.

The connection module is an interconnect module that connects the IP modules through switching, and uses an asynchronous bufferfly fat-tree network switch 210 as an embodiment.

The IP module 220 is operated by a clock that is local (synchronous) to the IP module of another node.

That is, although FIG. 2 shows only one IP module, the IPs in the NoC do not use a single globally clock but operate by local synchronous clocks.

At this time, the IP module 220 communicates with other IPs connected to the connection module, that is, the asynchronous switch 210 by using an asynchronous interface device 230 called a wrapper.

The asynchronous interface device 230 may be configured independently as shown in FIG. 2, or may be configured in the IP module 220.

The asynchronous interface device 230 interfaces an output interface unit 231 for interfacing data output from the IP module 220 to the switch 210 and data input from the switch 210 to the IP module 220. A local clock generator 233 which provides or stops a clock to the IP module 220 according to the input interface unit 232 and the synchronization signals out_sync and in_sync of the input / output interface units 231 and 232. It is composed.

That is, since the respective synchronous IP modules operate at different speeds independently of each other, a problem of clock skew may occur. To prevent this, the asynchronous interface device 230 is used. The asynchronous interface device 230 provides synchronization between synchronous IP modules operating at different clocks.

3A is a flowchart illustrating an operation process of the output interface unit 231.

The output interface unit 231 has IP_out_req and W_out_ack signals as input signals, and W_out_req, IP_out_ack and out_sync signals as output signals.

The IP_out_req signal is a signal for transmitting data from the IP module 220 to the asynchronous interface device 230, and the IP_out_ack signal is a signal indicating that the asynchronous interface device 230 has received data and is transmitted to the IP module 220. do.

When the IP_out_req signal is 1, the out_sync signal applied to the local clock generator 233 becomes 1, so that the local clock generator 233 does not provide a clock to the IP module 220. The IP module 220 stops operating. At the same time, the asynchronous interface device 230 sends the data to the asynchronous switch 210 by setting the W_out_req signal to 1 and applying it to the asynchronous switch 210.

Thereafter, the asynchronous switch 210 sets the W_out_ack signal to 1 and applies it to the asynchronous interface device 230. That is, the asynchronous switch 210 informs the asynchronous interface device 230 that the asynchronous interface device 230 has received data.

Then, the asynchronous interface device 230 sets the IP_out_ack to 1 and transmits it to the IP module 220. This means that the data output from the IP module 220 is provided to the asynchronous switch 210.

When the input IP_out_ack signal is 1, the IP module 220 resets the IP_out_req signal to 0 and outputs the same to the asynchronous interface device 230. That is, according to this signal, all signals out_sync, W_out_req, W_out_ack, and IP_out_ack are initialized to 0 to prepare for the next data transition. That is, the local clock generator 233 provides a clock to the IP module 220, and the IP module 220 operates normally.

3B is a flowchart illustrating an operation process of the input interface unit 232, and IP_in_req and W_in_ack signals are input signals, and W_in_req, IP_in_ack and in_sync signals are output signals.

Referring to FIG. 3B, the input interface unit 232 also operates in the same way as the output interface unit 231, and only detailed signal names are omitted.

4 is a detailed circuit diagram illustrating an embodiment of an asynchronous interface device 230 designed to perform the same operations as FIGS. 3A and 3B.

Referring to FIG. 4, since the output interface unit 231 and the input interface unit 232 of the asynchronous interface device 230 may operate only one of the two, the mutual exclusion (ME) unit 241 may be removed. Arbitration is being used. Mutual exclusion controls when multiple parallel processes access a common variable or resource so that only one process is allowed to access it at any point in the access to justify its operation. For example, if one process is writing data to a file and another process deletes the file, many problems will occur. Accordingly, the mutual exclusion unit 241 controls only one of the output interface unit 231 and the input interface unit 232 to operate.

The output interface unit 231 and the input interface unit 232 are each composed of a plurality of C elements designed to perform the above-described operation.

That is, the output interface unit 231 is composed of three C elements 231-1 to 231-3. At this time, the C element 231-3 receives the W_iut_req signal and the W_out_ack signal as inputs, and the output thereof becomes an IP_out_ack signal, which is provided to the ME unit 241 and is inverted and provided to the C elements 231-1 and 231-2. The C element 231-1 receives an inverted output value of the C element 231-3 and an IP_out_req signal input through the ME unit 241, and the output thereof becomes a W_out_req signal to the switch 210. It is outputted and provided to the C elements 231-2 and 231-3. The C element 231-2 receives an inverted output of the C element 231-3 and an output of the C element 231-1 as an input, and the output thereof becomes an out_sync signal and is provided to the local clock generator 233. do.

Since the input interface unit 232 differs only in the signal name, the components are the same as the output interface unit 231, and thus detailed description thereof will be omitted.

FIG. 5 is a diagram illustrating a detailed circuit and an operation example of one of the plurality of C elements of FIG. 4.

FIG. 5A is a C element labeled 231-3 or 232-3, and FIG. 5B is a transistor level implementation of the C element of FIG. 5A. 5C shows an example of the operation of the C element at this time.

5, if input A and B are all 0 or input A is 1 and input B is 0, output 0 is output C, and if input A and B are all 1 or input A is 0 and input B is 1, Output 1 to output C. In other words, if the input A becomes 1 while the output C is 0, and the input B becomes 0, the output C remains 0. If input B becomes 1 while input A remains 1, output C changes to 1. If input A goes to 0 and input B keeps 1, output C also keeps 1.

The C elements may be designed using digital logic circuits.

The local clock generator 233 is controlled by the synchronization signals out_sync and in_sync of the output interface unit 231 and the input interface unit 232 to supply a clock to the IP module 220.

That is, the local clock generator 233 provides a clock to the local IP module 220 configured as a synchronization circuit in order to provide an interface to the IP modules. At this time, the local clock generator 233 stops the clock provided to the IP module 220 according to the synchronization signals out_sync and in_sync of the output / input interface units 231 and 232 for a predetermined time to stop the operation of the IP module 220. Stop it. That is, when the out_sync signal or the in_sync signal is 1, the clock signal transmitted to the IP module 220 is stopped, so that the IP module 220 stops operating. At this time, the IP module 220 is prepared to communicate with other IP modules. This is to provide synchronization between synchronous IP modules operating at different clocks. By doing so, it is possible to solve the problem of clock skew caused by each of the synchronous IP modules operating at clock speeds independently of each other.

FIG. 6A is a detailed circuit diagram illustrating an embodiment of the local clock generator 233, and includes a NOR gate 611, a selector 612, a clock controller 613, and an odd inverter chain 614. The clock controller 613 includes a NAND gate for NAND combining the output of the selector 612 and the output of the odd inverter chain 614, and an inverter for inverting and outputting the output of the NAND gate. The odd inverter chain 614 has an odd number of inverters connected in series.

The NOR gate 611 outputs 1 only when the synchronization signal out_sync of the output interface unit 231 and the synchronization signal in_sync of the input interface unit 232 are 0, and otherwise, 0 is output. At this time, the out_sync signal and the in_sync signal do not become 1 at the same time.

The output of the NOR gate 611 is provided to the first input terminal and the selection signal terminal sel of the selector 612. The selector 612 receives an output of the odd inverter chain 614 to a second input terminal. The selector 612 selects 0 output from the NOR gate 611 when the output of the NOR gate 611 is 0 and outputs the output to the clock controller 613, and selects an output of the odd inverter chain 614 when 1. To the clock control unit 613.

Accordingly, when any one of the out_sync signal and the in_sync signal is 1, 0 is applied to the clock controller 613 through the NOR gate 611 and the selector 612. The clock controller 613 is an asymmetric circuit that outputs 0 as a clock signal when 0 is applied from the selector 612.

That is, as shown in FIG. 6B, when the output of the selector 612 is 0, the NAND gate of the clock controller 613 outputs 1 unconditionally regardless of the output of the odd inverter chain 614, and this output passes through the inverted part. 0 is output to the IP module 220. In this case, the IP module 220 is stopped, and communication is performed between the IP module 220 and another IP module.

Then, when the communication between the IP modules ends and the out_sync signal and the in_sync signal are both 0, the output of the NOA gate 611 becomes 1, and the clock controller 613 uses the IP signal of the odd inverter chain 614 as a clock signal as it is. Output to module 220. At this time, since the odd inverter chain 614 is composed of an odd number of inverters, if the output of the clock controller 613 is 1, 0 is output, and if 0, 1 is output. Accordingly, the clock signal is a normal clock signal that periodically repeats 0 and 1, and the period of the clock signal is determined by the number of inverters constituting the odd inverter chain 614. The IP module 220 is normally operated by the clock signal.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

According to the asynchronous interface device and method according to the present invention described above, it can be used in any SoC using an asynchronous switch circuit for communication between IP modules, and also from the circuit design to the interface that needs to connect various IP to the interface Can be used immediately, reducing the design cost.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (8)

A system-on-chip asynchronous interface device for interfacing the asynchronous connection module and the corresponding IP module to perform communication between the synchronous IP modules through an asynchronous connection module, An output interface unit for interfacing data transmission from the IP module to a connection module and outputting a control signal indicating that data is being transmitted; An input interface unit for interfacing data transmission from the connection module to the IP module and outputting a control signal indicating that data is being transmitted; And And a clock generator for stopping the operation of the IP module by stopping the generation of the clock provided to the IP module when at least one control signal of the output interface unit and the input interface unit is transmitting data. Interface device. The method of claim 1, wherein the output interface unit Receives a signal IP_out_req indicating data transmission from the IP module and outputs a signal W_out_req indicating data transmission to the connection module, and receives a signal W_out_ack indicating that data has been received from the connection module. And outputs a control signal out_sync to the clock generator so that a clock does not occur during this process. The method of claim 1, wherein the input interface unit Receives a signal W_in_req indicating data transmission from the connection module, outputs a signal IP_in_req indicating data transmission to the IP module, receives a signal IP_in_ack indicating that data has been received from the IP module, and signals W_in_ack indicating that data has been received to the connection module. And outputs a control signal in_sync to the clock generator to prevent a clock from being generated during this process. The method of claim 1, wherein the clock generator A logic unit for combining the control signal of the output interface with the control signal of the input interface unit; A selection unit receiving the output of the logic unit as one input and a selection signal; A clock control unit for generating a normal clock when the output of the selection unit is 0 and not generating a clock; And An odd number of inverters are configured in series, and the asynchronous interface device comprising an odd inverter chain for inverting the output of the clock control unit to provide to the other input and the clock control unit of the selection unit. The method of claim 4, wherein the clock control unit A logic unit for NAND combining the output of the selection unit and the output of the odd inverter chain; And And an inversion unit for inverting and outputting the output of the logic unit. In the asynchronous interface method for interfacing the asynchronous connection module and the corresponding IP module to perform communication between the synchronous IP module through an asynchronous connection module in a system on chip, An output interface step of interfacing data transmission from the IP module to a connection module and outputting a control signal indicating that data transmission is in progress; An input interface step of interfacing data transmission from the connection module to an IP module and outputting a control signal indicating that data is being transmitted; And And stopping the operation of the IP module by stopping a clock generation provided to the IP module when at least one control signal of the output and input interface steps indicates that data is being transmitted. 7. The method of claim 6, wherein said output interface step is Receives signal IP_out_req indicating data transmission from the IP module, outputs a signal W_out_req indicating data transmission to the connection module, and receives a signal W_out_ack indicating that data has been received from the connection module. Output IP_out_ack, and outputs the control signal out_sync to prevent the clock from occurring during this process. The method of claim 6, wherein the input interface step Receives a signal W_in_req indicating data transmission from the connection module, outputs a signal IP_in_req indicating data transmission to the IP module, receives a signal IP_in_ack indicating that data has been received from the IP module, and signals W_in_ack indicating that data has been received to the connection module. And outputs a control signal in_sync to prevent a clock from occurring during this process.

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