JP2002189610A - Dual processor mixing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the performance of a dual processor by enhancing transferring ability of an inter-processor mixing part while to reduce the number of component items by reducing the number of signal lines and by miniaturizing a buffer circuit. SOLUTION: A serial link is used as the inter-processor mixing part to enhance its transferring ability. This serial link is used on the ground that a serial link is used in general to multiplex inputted parallel data and output them as serial data signals while to convert inputted serial data into parallel data to be outputted. Since the serial link has a problem of desynchronizing parallel signals of devices from each other, the synchronization of parallel data signals conveyed by the serial link is realized by using synchronizing-pulse transmitting/receiving circuits pg21, pg22, t21, and t22, and synchronization buffer circuits bf21, bf22, bf23, and bf24, in addition to serial signal transmitting/ receiving circuits ps21, ps22, sp21, and sp22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual processor confounding system, and more particularly, to a dual processor card of a clock synchronous operation system, which receives data from each other and compares received data from the other with its own data to determine a coincidence. The present invention relates to a dual-processor confounding system.

[0002]

2. Description of the Related Art Generally, such a processor which is duplicated by clock synchronous operation realizes the coincidence of clock edges by referring to the operation clocks in the processor card. Synchronization from the bus clock to the CPU operation clock is performed. As a result, the running command is synchronized at the clock level to enable the duplex operation.

In such a duplicated processor, the bus of the inter-processor confounding section is also synchronized at the same frequency as the bus clock in the processor card, and operates at the same clock edge. The access from the active processor and the access from the standby processor are checked by a matching check circuit, and if they match, the access is accepted as a valid access.

FIG. 4 shows an example of such a conventional dual processor system. In FIG. 4, it is assumed that the 0-system processor card pc11 is an active system and the 1-system processor card pc12 is a standby system. Each processor card pc11, pc12 is provided with a processor p1, p
2, bus drivers d11 and d12, and bus receivers d13 and d13.
It comprises d14 and coincidence check circuits c1 and c2.

The confounding buses b11 and b1 are located between the processor cards.
Connected by two. The processor p1 and the processor p2 operate with a synchronized clock, and the access from the processor p2 is input to the match check circuit c1 in the processor card pc11 via the bus driver d12 and the bus receiver d13. A match check with access from p1 is performed. After the check, if they match, it is accepted as a normal access.

[0006]

However, in the prior art shown in FIG. 4, the operating frequency of the bus in the processor card is also limited by the clock frequency of the confounding bus between the duplicated processor cards. . Generally, the signal frequency at the time of signal transmission of the back wiring board connecting between cards is lower than the signal frequency at the time of signal transmission within the card due to the longer distance of the transmission path. For this reason, the processing capacity of the duplicated processor card is limited by the signal frequency at the time of signal transmission of the back wiring board.

[0007] The specific problems are that the data transfer speed from the CPU using the processor confounding bus to the input / output interface and the data transfer speed from the input / output interface to the memory cannot be increased, and that the standby system (S
There is a problem in that it takes a long time to copy the memory when incorporation into the in-service (BY system).

In addition, the number of buses is increased to increase the number of signals in order to improve the data transfer capability of inter-processor congestion, and the performance of the processor is improved by using a buffer circuit or the like without changing the inter-processor data transfer capability. The prevention of the drop causes an increase in the number of parts.

When a parallel bus having an increased number of buses is used for high-speed data transfer of the back wiring board, the influence of the difference in the wiring length of each signal line is large,
It is difficult to speed up data.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the performance of a dual processor by using a serial link having a high data transfer capability for the interprocessor between processors in a clock synchronous type dual processor. At the same time, it is an object of the present invention to provide a dual processor confounding system capable of reducing the number of components by reducing the number of signals and the size of the buffer circuit.

[0011]

According to the present invention, data is exchanged between duplicated processor cards of the clock synchronous operation system, and received data from the other is compared with own data to determine a coincidence. A redundant processor confounding system as described above, wherein a serial link for transmitting and receiving data between the redundant processor cards and synchronization for providing synchronization of transfer data of the serial link provided in each of the processor cards. A signal transmission / reception circuit, a first buffer circuit provided in each of the processor cards for sequentially writing the own data and controlled by the synchronization signal, and a reception circuit provided in each of the processor cards for receiving via the serial link. A second buffer in which data is sequentially written and read controlled by the synchronization signal Redundant processor confounding system comprising a road is obtained.

The serial link includes a parallel / serial conversion circuit for converting the own data from parallel to serial and sending the data to the partner processor card, and a serial / parallel for converting the received data from the partner processor card to serial / parallel. A conversion circuit, and the output data of the serial / parallel conversion circuit is written into the second buffer circuit.

The synchronizing signal transmitting / receiving circuit generates a lower-speed clock in synchronism with the operation clock in the processor card and sends the generated clock to the other processor card. A synchronous timing generation circuit for generating a read timing signal for the first and second buffer circuits. The synchronous timing generation circuit generates the readout timing signal in consideration of a delay time corresponding to a total value of operation delay times of the parallel / serial conversion circuit, the serial / parallel conversion circuit, and the serial link. It is characterized by having done.

Further, the first and second buffer circuits are provided with a FIFO.
An O-type storage circuit for outputting read data from the storage circuit to a coincidence check circuit, wherein the first buffer circuit is activated at the write timing of the own data and stopped at the read timing signal A timer is provided, and when the timer expires, the fact is reported to the coincidence check circuit.

The operation of the present invention will be described. A feature of the dual processor confounding system according to the present invention is that the transfer capability is improved by using a serial link for the inter-processor confounding part. Generally, a serial link multiplexes and outputs a serial data signal with parallel data as input, and converts input serial data into parallel data and outputs the data. In the present invention, this serial link is used. . In this case, such a serial link generally has a built-in PLL (Phase Locked Loop) circuit, outputs a serial data signal including a clock component from a transmitting device, and a receiving device outputs a data signal component from a received serial data signal. And the extraction of clock components, there is a problem that the parallel signals of each device are asynchronous with each other.

Therefore, according to the present invention, in addition to the serial signal transmitting / receiving circuit, a synchronizing pulse transmitting / receiving circuit and a parallel signal synchronizing buffer circuit controlled by the synchronizing pulse are used, so that the parallel signal transmitted by the serial link is transmitted. The synchronization of the data signal is realized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals.

Referring to FIG. 1, the dual processor confounding system includes parallel / serial converters ps21 and ps22 for realizing confounding of the dual processors in addition to the processors p1 and p2 and the coincidence check circuits c1 and c2.
, Serial / parallel conversion circuits sp21, sp22, buffer circuits bf21, bf22, bf23, bf24, pulse generation circuits pg21, pg22, and synchronization timing generation circuit t21,
t22, and the respective processor cards pc1, p2
c2 is the serial links s21 and s22 and the pulse signal line pl2.
1, pl22.

Parallel / serial conversion circuits ps21, ps
22 converts the access from the processors p1 and p2 into serial data and mate via the serial links s21 and s22.
To the processor cards pc21 and pc22. The pulse generation circuits pg21 and pg22 output timing pulses to the mate processor cards pc22 and pc21 via the pulse signal lines pl21 and pl22 in synchronization with the serial signal output. The timing pulse signal lines pl21 and pl22 operate at a lower speed clock synchronized with the operation clock in the processor cards pc21 and pc22 to connect the processor cards pc21 and pc22. Serial signal from mate
22 and s21 are serial / parallel conversion circuits sp21 and sp22
Is restored to a parallel signal.

On the other hand, for the access from the processors p1 and p2, the buffer circuits bf21 and bf22 wait for the access from the mate processor card. Access from a mate processor card is restored to a parallel signal, and then clock conversion is performed by the buffer circuits bf23 and bf24.

The synchronous timing generation circuits t21 and t22 generate timing pulses for starting the buffer circuit in response to signals from the pulse signal lines pl22 and pl21, and the buffer circuits bf21 and bf
f23 and buffer circuits bf22 and bf24. Buffer circuit b
f21, bf22, bf23, bf24 are timing pulse signals tp21, tp from the synchronous timing generation circuits t21, t22.
22, the match check circuits c1 and c2 cause the processor p
1 Access from p2 is output.

The coincidence check circuits c1 and c2 check the coincidence of accesses from both processors p1 and p2. If they match after the check, they are accepted as normal access. Buffer circuits bf21, bf22, bf23, bf24
Has a FIFO (First-In-First-Out) configuration in which stored data is read out and applied by timing signals tp21 and tp22 generated by the synchronization timing generation circuits t21 and t22.

The processor and the coincidence check circuit shown in FIG. 1 are well known to those skilled in the art, and are not directly related to the present invention.

The operation of the configuration of FIG. 1 will be described below with reference to the timing chart of FIG. The processor c1 and the processor c2 operate on a synchronized clock, and
In describing the operation of the present embodiment, the 0-system processor card pc21 is set as the active system, and the 1-system processor card p21 is used.
Description will be made assuming that c22 is a standby system.

Access from the processor p2 is shown at the signal output of the processor p2, and access from the processor p1 operating in synchronization is shown at the signal output of the processor p1. In the operations of the processors p1 and p2, the clock edges have the same timing, so that the output signals from the processors p1 and p2 have the same timing. When the signal output from the processor p2 is converted into a serial signal by the parallel / serial conversion circuit ps22, a delay time d1 due to the conversion of the asynchronous clock is generated. When the converted serial signal s22 is input to the serial / parallel conversion circuit sp21 of the 0-system processor card pc21, a delay time d2 due to wiring occurs. The delay time d3 also occurs when the signal is converted into a parallel signal by the serial / parallel conversion circuit sp21.

The output of the pulse signal pl22 generated by the pulse generation circuit pg22 in response to the output signal of the processor p2 reaches the 0-system processor card pc21 with a wiring delay d4. Arrives at the synchronization timing generation circuit t21 with the delay of.
The synchronization timing generation circuit t21 has a delay d synchronized with the clock in the processor card pc21 in consideration of the delay generated in the serial / parallel conversion circuit sp21 and the buffer circuit bf23.
5, the timing pulse signal tp21 is supplied to the buffer circuit b.
Output to f21 and bf23.

The buffer circuits bf21 and bf23 output accesses from the respective processors p1 and p2 to the coincidence check circuit at the timing of the timing pulse signal tp21.
The coincidence check circuit c1 checks the coincidence between the access from the processor p1 and the access from the processor p2. After checking, if they match, it is accepted as a normal access.

Each of the buffer circuits is started upon receiving (writing) access in its own processor card, and receives timing signals t from the synchronous timing generation circuits t21 and t22.
It is assumed that the timer has a timer (not shown) that is stopped by p21 and tp22, and this timer is used for synchronizing timing signals tp21 and tp22 when a failure of the mate processor card occurs, for example, when a pulse signal does not come. Is not generated, a time-out occurs, and a notification signal is output to notify the coincidence check circuits c1 and c2 of that fact. As a result, it is possible to avoid the influence of a failure in another system.

In another embodiment of the present invention, the basic configuration is as described above, but the number of confounding signals between processor cards and the circuit scale are further devised. . FIG. 3 shows the configuration, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, timing generation circuits tg31 and tg32 are provided instead of the pulse generation circuits pg21 and pg22 and the synchronization timing generation circuits t21 and t22 of FIG.

The timing generation circuits tg31 and tg32 are provided with a delay d1 generated by the parallel / serial conversion circuits ps21 and ps22 and a delay d generated by the serial signals s21 and s22.
2 and the delay signal d3 generated by the serial / parallel conversion circuits sp21 and sp22 and the buffer circuits bf23 and bf24, and a delay time, which is generated in synchronization with the operation clock in the processor cards pc21 and pc22.
1, generate tg32.

The timing generation circuits tg31 and tg32 can replace the pulse generation circuits pg21 and pg22 and the synchronous timing generation circuits t21 and t22 shown in FIG.

Further, both processor cards pc21, pc22
It is possible to omit the pulse signals pl21 and pl22 connecting between them, and it is possible to obtain an effect of further reducing the number of confounding signals between processor cards and reducing the circuit scale. In this configuration, since the timing generation circuits tg31 and tg32 can generate the timing pulses tp31 and tp32 regardless of the state of the standby processor card, even if there is no pulse signal input due to the failure of the standby processor card, the active processor card Has the effect of not stopping the operation.

In the timing chart of FIG.
The pulse signal pl22 is output in one-to-one correspondence with the serial signal s22.
Is a clock pulse that is slower than the operation clock in the processor card, and is actually a low-speed pulse having a cycle that is an even multiple of this operation clock. In FIG. 2, the buffer circuit bf21 signal output is supplied to the check circuit c1 with a slight delay from the timing pulse tp21.
Is generated, each buffer circuit is activated, and data is read from the FIFO.

In the above embodiment, the data transferred between the redundant processors is shown as an access. However, the present invention is not limited to this, and may be various instructions and data. It should be noted that the present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0035]

As described above, according to the present invention,
By using a serial link, a synchronization pulse circuit, and a synchronization buffer circuit in the confounding bus section between the duplicated processor cards, the influence of the signal frequency at the time of signal transmission of the back wiring board connecting the cards is reduced, and The data transfer speed from the CPU using the confounding bus to the input / output interface and the data transfer speed from the input / output interface to the memory can be improved, and there is an effect that the memory copy time at the time of incorporation into SBY-based in-service can be reduced. . Also, the number of signals for confounding between processors can be reduced, and the buffer circuit and the like of the existing circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the block in FIG. 1;

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 pc21, pc22 processor card p1, p2 processor ps21, ps22 serial / parallel conversion circuit pg21, pg22 pulse generation circuit bf21, bf22, bf23, bf24 buffer circuit c1, c2 coincidence check circuit sp21, sp22 serial / parallel conversion circuit t21, t22 synchronization Timing generation circuit tg31, tg32 Timing generation circuit

Claims (6)

[Claims] The present invention is characterized in that data is exchanged between redundant processor cards having a clock synchronous operation method.
A duplicated processor confounding system configured to compare received data from the other with its own data to determine a match, comprising: a serial link for exchanging data between the duplicated processor cards; and a serial link provided for each of the processor cards. A synchronization signal transmission / reception circuit for synchronizing the transfer data of the serial link; and a first buffer circuit provided in each of the processor cards, wherein the self-data is sequentially written and read-out controlled by the synchronization signal. And a second buffer circuit provided in each of the processor cards and sequentially writing received data via the serial link and being controlled to be read out by the synchronizing signal. 2. The serial link includes: a parallel / serial conversion circuit for converting the own data from parallel to serial and sending it to a partner processor card; and a serial / parallel for converting the received data from the partner processor card to serial / parallel. 2. A duplex processor confounding system according to claim 1, further comprising a conversion circuit, wherein output data of said serial / parallel conversion circuit is written to said second buffer circuit. 3. The synchronizing signal transmitting / receiving circuit includes: a pulse generating circuit that generates a lower-speed clock synchronized with an operation clock in the processor card and sends the generated clock to another processor card; 3. The dual processor confounding system according to claim 1, further comprising: a synchronous timing generation circuit for generating a read timing signal for said first and second buffer circuits. 4. The read timing signal taking into account a delay time according to a total value of operation delay times of the parallel / serial conversion circuit, the serial / parallel conversion circuit, and the serial link. 4. The dual processor confounding system according to claim 3, wherein 5. The buffer circuit according to claim 1, wherein said first and second buffer circuits are FIFO type memory circuits, and output data read from said memory circuits to a coincidence check circuit.
A dual processor confounding system according to any of the preceding claims. 6. The first buffer circuit has a timer which starts at a write timing of the own data and stops at a read timing signal. When the timer times out, the first buffer circuit notifies the coincidence check circuit of the timer. 6. The dual processor confounding system according to claim 5, wherein: