JPH07281785A - Processor system - Google Patents

Abstract

PURPOSE:To provide the processor system which can increase the operation speed of each board without causing trouble such as crosstalk, skew between signals, etc. CONSTITUTION:A frequency divider 3 of a master board (a) divides the frequency of a master clock into a frequency lower than the maximum propagation frequency of a system bus B, and distributes the frequency-divided clock signal to respective slave boards b1-bn as a reference signal through a reference signal line BA, and the slave boards b1-bn generate internal operation clocks in subordinate synchronism with the reference signal by PLL circuits 23 and supply them to internal control circuits 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system used in a large-scale data processor such as a packet switch, and more particularly to a plurality of boards including at least one processor board via a common system bus. Regarding the connected system.

[0002]

2. Description of the Related Art In a relatively large-scale data processing apparatus, a processor system in which a plurality of boards including processor boards are connected as a central processing unit through a common system bus is often used. 2 to 5 show the configuration of a conventionally known system.

First, the system shown in FIG. 2 generates and operates an independent clock for each board. That is, each of the boards a20 to a2n is connected to the system bus B2, and the clock oscillator 20
Have one. Each of the boards a20 to a2n operates by a clock independently generated from these clock oscillators 201.

On the other hand, in the system shown in FIG. 3, a clock is distributed from one clock master board to each of the other slave boards via a system bus.
That is, the clock signal generated by the clock oscillator 301 provided on the master board a3 is transmitted to the system bus B.
It distributes to each slave board b31-b3n via 3,
Each slave board b31-b3n operates by the distributed clock.

In the system shown in FIG. 4, clocks are distributed from one master board a4 to the other slave boards b41 to b4n via a system bus B4 in a daisy chain.

Further, the system shown in FIG. 5 has one master board a5 and other slave boards b51 to b5n.
The clock is distributed in a daisy chain via the system bus B5 to the slave boards b51 to b.
In 5n, the clock coming from the upstream board is inverted and transferred to the downstream board.

[0007]

However, these conventional systems have the following problems to be solved. First, Figure 2
In the system shown in (1), various signal skews on the system bus B2, conflict settling skews, etc. occur, so that it is necessary to reduce the transmission rate as a bus cycle.
In addition, since the data acknowledge between the boards also responds asynchronously, there is a problem that the delay is one cycle later than the expected delay.

On the other hand, in the system shown in FIG. 3, since the clock is distributed from the master board to each slave board through the bus connection, the speed of the clock can be increased as compared with the system shown in FIG. However, since each board is connected to the system bus using the TTL interface, the clock speed is limited to about 20 MHz at most, and it is impossible to further increase the speed. Further, if the clocks are independently distributed to each board, crosstalk noise on the system bus increases, which may cause an unexpected failure or clock skew.

Further, in a system in which each slave board is connected to a master board in a daisy chain like the system shown in FIGS. 4 and 5, the signal delay due to the daisy chain gate of each slave board is large, so that the system There is a problem that the speed of the bus is limited.
Further, there is a problem in that the occurrence of clock skew cannot be prevented, and furthermore, slot mounting is restricted.

The present invention has been made in view of the above-mentioned circumstances, and a processor capable of increasing the operating speed of each board without causing problems such as crosstalk and signal skew. The purpose is to provide a system.

[0011]

According to the present invention, in a processor system in which a plurality of boards including at least one processor board are connected via a common system bus, a master board serving as a clock master among the plurality of boards is used. A master clock generating means for generating a master clock, and a component for dividing the master clock generated by the master clock generating means to a frequency lower than the maximum propagation frequency determined by the transmission characteristics of the system bus to generate a reference signal. A frequency dividing means and a reference signal transmitting means for transmitting the reference signal generated by the frequency dividing means to the system bus, and to a board other than the master board among the plurality of boards via the system bus. Based on the reference signal sent from the master board, subordinate to this reference signal. Those having a slave clock generating means having a PLL circuit for generating a slave clock consisting of required frequencies.

According to the present invention, the above-mentioned dependent clock generating means is provided with a signal monitoring means for monitoring the presence or absence of a reference signal arriving via the system bus. When a disconnection is detected, the PLL circuit is set to the free-running mode during the reference signal disconnection period to continue the operation of generating the dependent clock.

[0013]

As a result, according to the present invention, from the master board serving as the clock master to the slave board, the clock whose frequency is divided by the frequency divider to the maximum propagation frequency of the system bus or less is sent as the reference signal. Therefore, occurrence of crosstalk or the like on the system bus is prevented. Further, in the slave board, a clock generating means having a PLL circuit generates a clock of a required frequency which is subordinately synchronized with the reference signal based on the reference signal sent from the master board, and the subordinate clock has the subordinate clock. It is used as the operation clock of. For this reason,
The slave board operates in a state of being completely synchronized with the master board, which minimizes the occurrence of dead time such as signal skew and bus contention. Moreover, since the high-speed clock required by the slave board can be generated, the slave board can operate at high speed. That is, it is possible to provide a system that achieves both improved stability and higher operating speed.

Further, according to the present invention, the slave board is monitored for the arrival of the reference signal, and if the arrival of the reference signal is interrupted during the generation of the slave clock, the slave board enters the free-running mode to generate the slave clock. Is continued. For this reason, even if the reference clock is temporarily cut off for some reason, the slave board can continue its operation without being directly affected by it, thereby further improving the stability of the system. .

[0015]

1 is a circuit block diagram showing the configuration of a processor system according to an embodiment of the present invention. In the figure, a is a master board serving as a clock master, and b1 to
bn indicates a slave board, and B indicates a system bus. The system bus B includes a reference signal line BA, an address bus BB, a data bus BC and a control bus B.
It consists of D.

The master board a has a CPU 1 for executing the main control of the system, and further has a clock oscillator 2, a frequency divider 3, and a buffer 4. The clock oscillator 2 generates a high speed master clock signal necessary for the operation of the CPU 1, and uses this master clock as the CPU 1
Supply to. The frequency divider 3 sets the master clock signal to 1
/ N (n = 1, 2, ...) And the reference signal is generated by this. Here, n is set so that the reference signal frequency is lower than the maximum propagation frequency (maximum cutoff frequency) determined by the propagation characteristics such as the distributed capacitance of the system bus B and the capacitive load. The reference signal output from the frequency divider 3 is sent to the reference signal line BA via the buffer 4.

The address A output from the CPU 1
The DD, the data DAT, and the control signal CONT are supplied to the address bus B of the system bus B via the buffer 4.
B, data bus BC and control bus BD.

On the other hand, the slave boards b1 to bn are CPUs.
It has an internal control circuit 21 provided with 22, and the internal control circuit 21 and each bus B of the system bus B.
Address ADD and data DAT between B, BC and BD
A buffer 25 for buffering the control signal CONT, the PLL circuit 23, and the clock loss detection circuit 2
4 and.

The PLL circuit 23 generates an internal operation clock of a frequency required by the CPU 22 in synchronization with the reference signal input from the reference signal line BA via the buffer 25, and uses this clock. It is supplied to the internal control circuit 21. The clock loss detection circuit 24 has a function of detecting the disappearance of the reference signal coming through the system bus B. The PLL circuit 23 is in the free-running mode while the clock loss detection circuit 24 detects the disappearance of the reference signal.

Next, the operation of the system configured as described above will be described. A master clock is generated in the clock oscillator 2 of the master board a, and this master clock is supplied to the CPU 1 as an operating clock. The master clock is 1 / n (n = n) in the frequency divider 3.
1, 2, ...), resulting in a frequency lower than the maximum propagation frequency of the system bus B, and then output to the reference signal line BA of the system buffer B via the buffer 4 and the reference signal line BA. Via each slave board b
1 to bn.

That is, a clock whose frequency is lower than the maximum propagation frequency of the system bus B is transmitted on the reference signal line BA. Therefore, no trouble such as crosstalk occurs on the system bus B.

On the other hand, in each slave board b1 to bn,
Based on the reference signal arrived via the reference signal line BA,
In the PLL circuit 23, the CP is synchronized with this reference signal and
A high-speed internal operation clock required for the operation of U22 is generated. Then, this internal operation clock is supplied to the CPU 22.

Therefore, each slave board b1 to bn
Both are fully slaved to the reference signal and CPU 22
Will operate in synchronization with the high-speed clock required for the operation of. Therefore, the slave boards b1 to bn can operate at high speed without causing signal skew.

It is assumed that the reference signal is temporarily lost due to some cause during the above operation. Then, the loss of the reference signal is detected by the clock loss detection circuit 24, and the PLL circuit 23 is in the free-running mode during the loss period of the reference signal. Therefore, the PLL circuit 23 continuously generates the internal operation clock. Therefore, the CPU 22
The internal control circuit 21 including the above can continue the processing operation according to this clock.

As described above, according to the present embodiment, the frequency divider 3 of the master board a divides the master clock into a frequency lower than the maximum propagation frequency of the system bus B, and the divided clock signal is used as a reference. Reference signal line BA as a signal
Through the slave boards b1 to bn, and in the slave boards b1 to bn, the PLL circuit 23 generates an internal operation clock subordinately synchronized with the reference signal and supplies it to the internal control circuit 21. All the slave boards b1 to bn can operate in perfect synchronization with the master board a, and the system bus B can be completely synchronized. Therefore, it is possible to minimize the dead time due to signal skew or bus contention.
Further, since the clock frequency of the reference signal on the system bus B is set to be equal to or lower than the maximum propagation frequency, the problem that crosstalk noise or the like occurs on the system bus B is eliminated. Therefore, it is possible to provide a system in which each board is stable and can operate at high speed.

Further, according to the present embodiment, even if the reference signal is temporarily lost, this is detected by the clock loss detection circuit 24 and the PLL circuit 23 enters the free running mode, whereby the internal operation clock continues. Is generated. Therefore, the internal operation of the slave boards b1 to bn is guaranteed, which can further improve the operational stability of the system. The present invention is not limited to the above-described embodiments, and can be implemented by appropriately modifying it without departing from the scope of the invention.

[0027]

According to the present invention, in a master board which is a clock master among a plurality of boards, the master clock is divided into frequencies lower than the maximum propagation frequency determined by the transmission characteristics of the system bus to generate a reference signal, The generated reference signal is sent to the system bus, and in the boards other than the master board among the plurality of boards, the reference signal is sent based on the reference signal sent from the master board via the system bus. A dependent clock having a required frequency that is dependent on and synchronized with is generated.

Therefore, it is possible to provide a processor system which realizes both improved stability and higher operating speed.
As a result, it is possible to promote the stability and speed of the operation of the device or the like including the processor system.

Further, according to the present invention, in the above-described generation of the dependent clock, the presence or absence of the reference signal arriving via the system bus is monitored, and when the disconnection of the reference signal is detected during the generation of the dependent clock, , P during this reference signal disconnection period
Since the LL circuit is set to the free-running mode to continue the operation of generating the dependent clock, the stability of the processor system can be further enhanced, and thereby the stability of the operation of the device and the like including the processor system can be promoted. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a central processing unit of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional central processing unit.

FIG. 3 is a block diagram showing a configuration of a conventional central processing unit.

FIG. 4 is a block diagram showing a configuration of a conventional central processing unit.

FIG. 5 is a block diagram showing a configuration of a conventional central processing unit.

[Explanation of symbols]

a ... Master board, b1-bn ... Slave board, B ...
System bus, BA ... Reference signal line, BB ... Address bus, BC ... Data bus, BD ... Control bus, 1 ...
CPU, 2 ... Clock oscillator, 3 ... Divider, 4 ... Buffer, 21 ... Internal control circuit, 22 ... CPU, 23 ... PLL
Circuit, 24 ... Clock loss detection circuit, 25 ... Buffer.

Claims (2)

[Claims] 1. In a processor system in which a plurality of boards including at least one processor board are connected via a common system bus, a master board serving as a clock master of the plurality of boards is a master clock that generates a master clock. Generating means, frequency dividing means for dividing the master clock generated by the master clock generating means to a frequency lower than the maximum propagation frequency determined by the transmission characteristics of the system bus, and generating a reference signal; and the frequency dividing means. A reference signal sending means for sending the reference signal generated by the above to the system bus, and a board other than the master board among the plurality of boards is a reference sent from the master board via the system bus. Based on the signal, from the desired frequency slaved to this reference signal And a dependent clock generating means having a PLL circuit for generating the dependent clock. 2. The dependent clock generating means is a signal monitoring means for monitoring the presence or absence of a reference signal arriving via a system bus, and a disconnection of the reference signal is detected by the signal monitoring means during generation of the dependent clock. The processor system according to claim 1, further comprising: a PLL circuit that is in a free-running mode during the reference signal disconnection period and continues the operation of generating the dependent clock.