EP1211070A2 - Device and method for synchronizing processes running in several units - Google Patents

Abstract

The method of synchronizing processes in a paper making machine has a central control for producing a system cycle (7), with a free line for the field bus (10) to distribute the system phases to the processing stations. A further processor (11) for multiplying the system phases is provided. The circuit can use sensors to detect values for the rotational speed, angular position the acceleration of the machine.

Description

The invention relates to a device and a method for the synchronization of Processes that are executed by separate processors and on the system clock of one central unit are coordinated. This device or the Procedure for completed processes on various components of a paper processing machine

It is usually known from devices or methods that a bus special protocol is sent, whereby the different processors with the Control system can be synchronized. Systems of this type put a time and strain on the processors require special hardware.

In particular, EP 0 747 216 B1 proposes different units that are associated with Angular position signals must be supplied by means of two bus systems. Each unit continuously receives the current angle value using the one bus system and by means of the other bus system information about one to be carried out Switching operation. The angle setpoint at which the switching process is to be triggered is stored in a memory of the respective unit.

Starting from this prior art, the device according to the invention and the corresponding procedure is based on the task, a simple means Bring about synchronization of many processes.

This object is achieved by the characterizing features of claims 1 and 10. Further developments result from the dependent claims 2-9 and 11-18.

The device according to the invention assumes that a central unit Coordination of various other units in the periphery takes over. The central unit has the task, all on the periphery synchronize running processes. To do this, a centrally generated system clock is opened a free line of a field bus, e.g. B. CAN-BUS, to everyone in the process units involved. To keep the system clock susceptibility to malfunctions low, or to prevent crosstalk of this clock signal on other signal lines the frequency of the system clock is chosen to be relatively low. The clock signal thus moves in a frequency range, which results in a distribution of the clock signal over longer distances is possible. It is also possible to use an appropriate system clock Filtering measures.

Usually it is necessary for a process in the peripheral unit faster clock is required than the system clock. Therefore, the invention proposes Device in front of the incoming system clock in the peripheral unit multiply the requirements. This so-called module clock then generated has the desired resolution, or is advantageously to the desired resolution adjustable. Thus, the clock prevailing on the peripheral unit always prevails for the respective process is required.

The device according to the invention sees one integrated in the peripheral units Clock generator that is synchronized by the system clock. Between each The clock generator runs free of synchronization intervals due to the system clock. To the Keeping the module clock frequency stable on the peripheral unit suggests one Variant according to the invention to be stabilized using quartz. According to one calculated drift, which results from the quality of the stabilizing quartz, can Time interval of the synchronization interval can be determined.

The generation of a local module clock has the advantage that if the in the central unit generated system clock there is no risk that processes run uncontrolled and lead to accidents, since a vote of the independent running processes is no longer possible. The procedure is such that a Failure of the system clock to be recognized by the processor in the peripheral unit, which then controls the process based on the local module cycle to a standstill shuts down. The required time between the absence of the system clock and the controlled shutdown of the process is so short that that already mentioned Drifting the module clock from the system clock does not lead to any noteworthy problems. That means all processes that take place at and through the various peripheral units the system clock are synchronized to each other are generated by the on-site Module cycle brought to a standstill in a controlled manner.

A method according to the invention furthermore proposes that, at regular intervals, for example, a so-called after every hundredth system cycle Synchronization interval takes place. With this process, one is made to the peripheral unit Time announcement 37, which adjusts the peripheral unit to the absolute time. In which All peripheral units receive synchronization intervals for a time adjustment Absolute time, a so-called time stamp. By distributing this information each peripheral unit aligns its processes to the running machine, that is, ongoing processes can be kept in sync by corrective measures or beginning processes can occur at the right time or at the right time Angular position of the machine can be started.

Drehzahl v(t)

Beschleunigung a(t)

aktuelle Winkelstellung ϕ(t)

gegebenenfalls weitere Werte von Gebern, wie z.B. Papierankunftssignale eines Anlegers.

Furthermore, all peripheral units receive the following values and the time of acquisition of the values that are relevant for controlling a paper processing machine, for example by means of a CAN bus system:

Speed v (t)

Acceleration a (t)

current angular position ϕ (t)

If necessary, other values from donors, such as an investor's paper arrival signals.

With the simultaneous notification of the acquisition time of the value is the peripheral Unit capable of extrapolating the transmitted value to any one To calculate the time between two transmitted values. That is, already through the Time delay in the transmission of the values results in the problem that when receiving the Values that are no longer up to date. Through the device according to the invention, or The advantage of the procedure is that it is almost irrelevant how long the It takes time to transmit the values because the current value can always be determined.

An additional advantage is that the start time of a starting process between two transmitted values by the extrapolation mentioned above can be calculated. For example, the peripheral unit receives with the transmission the values the current angular position of the machine e.g. ϕ = 270 °, the speed, v = 8000 revolutions / hour, the acceleration a = 0. The participant should at a An angular position of ϕ = 278 ° trigger an event or start a process. Based on received values, the participant can calculate the time until the machine Has reached an angular position of ϕ = 278 °. Based on your own time base or Module clock that was synchronized to it when the last system clock was received can do this event to be triggered can be triggered without a time-synchronous instruction the central unit. Any such angle-dependent event peripheral unit can be triggered without direct wiring to a central incremental encoder is necessary. On the one hand, this saves cabling effort and on the other hand ensures less susceptibility to faults.

For whatever reason, it is not possible at the time of the system clock The actual values of the motor can also be read in at any time be imported. Then the actual values are extrapolated to the Calculated backward or forward time at which a system clock was present, or is present.

For the synchronous control of additional drives that run separately from the main drive, the method according to the invention proposes the following variant:

The additional drive is equipped with its own setpoint generator. This Setpoint generator calculates the setpoints for the additional drive. According to the dynamic requirements of the additional drive, sampling cycles are defined during which The actual values of the additional drive are read in and using various control algorithms new setpoints are specified. The actual values of the main drive become discrete Times (for reasons of bus load), but the frequency is lower than the scan cycles of the auxiliary drive. By the one that is also sent The point in time of the actual values of the main drive can determine the further course of the actual values of the main drive on the additional drive calculated at any time (interpolation / extrapolation).

An additional application of the device according to the invention or the method is that different motors running synchronously with each other do not follow the Actual values of a main drive, but can be regulated on a central command. This means that the central unit issues commands for everyone involved in the process Drives specified. Are drives running at a speed ratio e.g. half speed, a setpoint generator in the peripheral unit ensures three-speed or double-speed for the generation of adjusted target values. All engine governors are now reworking same algorithm and always read the actual values of the motors at exactly the same Time. This time corresponds to the system clock. This ensures that all motors are regulated on a virtual electronic shaft.

Fig. 1

ein Blockdiagramm der Vernetzung verschiedener Prozessoren,

Fig. 2

ein Blockdiagramm über eine Multiplikationseinheit,

Fig. 3a

ein Zeitdiagramm des Systemtakts,

Fig. 3b

ein Zeitdiagramm eines Zählvorgangs,

Fig. 3c

ein Zeitdiagramm der Feinauflösung des Modultakts,

Fig. 3d

ein Zeitdiagramm der Feinauflösung des Modultakts,

Fig. 3e

ein Zeitdiagramm der Feinauflösung des Modultakts,

Fig. 4

ein Zeitdiagramm über den Verlauf des Systemtakts,

Fig. 5

Fig. 1 mit zusätzlicher Motoransteuerung.

The invention will be explained in more detail below using an exemplary embodiment.
Show it:

Fig. 1

a block diagram of the networking of different processors,

Fig. 2

1 shows a block diagram over a multiplication unit,

Fig. 3a

a timing diagram of the system clock,

Fig. 3b

a timing diagram of a counting process,

Fig. 3c

a time diagram of the fine resolution of the module clock,

Fig. 3d

a time diagram of the fine resolution of the module clock,

Fig. 3e

a time diagram of the fine resolution of the module clock,

Fig. 4

a time diagram over the course of the system clock,

Fig. 5

Fig. 1 with additional motor control.

1 shows a network of two processors 1a, b. The processors 1a, b represent together with an interface 2a, b and connected input / output cards 3a, b and engine control cards 4a, b each represent a unit 5a, b. Die respective local components, such as processor 1a and interface 2a, or 1b and 2b are connected to each other by means of the VME bus system 6. Located on the interface 2a there is still a system clock 7. This system clock 7 is e.g. of a CAN bus system 10 to the input / output card 3a located in the periphery and passed the engine control card 4a. The number of input / output cards 3a or the number of engine control cards 4a is irrelevant. About an additional Line 9, which is assigned to the CAN bus system 10 as a free line, is the System clock passed to the interface 2b of the unit 5b. On the interface 2b there is a system clock processing 8, for example a filter or a Includes amplifier. From the interface 2b, the system clock 7 is also sent to the Unit 5b associated input / output card 3b and the motor control card 4b by means of Line 9 forwarded. The input / output card 3b or the subscriber Motor control card 4b can be used by subscribers 16a, b whose use is not defined be expanded. Likewise, the number of interfaces 2a, b per unit 5a, b be larger than shown in this embodiment. The system clock 7 will continue via the local VME bus system 6a, b all local belonging to the unit 5a, b Components 1a, b and 2a, b provided. There are more via a line 9d Units 5n can be connected to the system clock 7.

Tasks are performed on the input / output card 3a, b and the motor control card 4a, b executed that need a time resolution that is finer than the system clock 7 to Provides. Therefore, in these cards 3a, b 4a, b additional Multiplication units 11 required. The multiplication unit 11 has the task of Multiply the resolution according to the required circumstances. This can for example based on an embodiment according to FIG.

Fig. 2 shows a block diagram of a multiplication unit 11 as it relates to the various input / output cards 3a, b and motor control cards 4a, b is present. In A frequency generator 12 is a clock with a frequency of 1 MHz, for example generated. A crystal 13 is assigned to this for frequency stabilization. To the Frequency generator 12, a counter 14 is connected. With the system clock 7 Counter 14 started or reset. For example, the system clock 7 has one Clock frequency of 1 kHz, the counter counts within a period of the system clock 7 from 0-999 and repeats this process continuously. Described in more detail, this means that the Pulses of the frequency generator 12 in the event that they are synchronous with the system clock 7 be switched through, so to speak. There is no exact synchronicity between the pulses of the frequency generator 12 and the system clock 7 can cause the last of the 1000 pulses are either shortened somewhat if the counter 14 is reset early , or this is pending a little longer, because the counter 14 starts counting at 999 established. The synchronized module clock 15 is the output I / O card, 3ab or motor control card 4ab provided.

In Fig. 3a to 3e several diagrams are shown, the system clock 7 (Fig. 3a) Ramp function of the counter 14 (FIG. 3b) and a fine resolution of the module clock 15 (Fig. 3c, d, e) show. The diagram of Fig. 3a shows the system clock 7, wherein in 3b, the ramp function of the counter 14 always with the falling one Edge 30 of the system clock 7 is started. As mentioned earlier, the Counter 14 within a period, each between the falling edges 30 of the System clock 7 is from 0-999. The ramp functions 33, 34, 35 show different things Behavior which can be explained by the diagrams according to Fig. 3c, d, e. So is in 3c to see that the last count pulse 999 is narrower than the previous ones. This can be explained by the fact that the frequency of the module clock 15 is slightly slower than a thousand times the system clock 7. The 999th count is then replaced by the System clock 7 corrected, which results in synchronization.

The diagram of Fig. 3d shows the case that the module clock 15 compared to the System clock 7 is slightly faster than a thousand times the system clock 7. that the counter 14 no longer increases its counter reading at 999 remains the last Count pulse (999) until the counter is reset by the falling one Edge 30 of the system clock 7 takes place. A correction is also made again, or Synchronization. The diagram according to FIG. 3e represents yet another variant When the counter reaches 999, the counter is not affected by the system clock 7 reset because it failed, for example, but there is a Resetting the counter due to exceeding a specified one Time window 36. This time window 36 is at a defined counter reading (e.g. 990) starts and ends, for example, 10 µs after reaching counter 999. Thus the module clock 15 is forcibly reset, which simultaneously results in that the processes clocked by the module clock 15 from the time of the first Failure of the system clock to be brought to a controlled stop.

The effect of the time window 36 also amounts to filtering. For example A link between the time window 36 and the system clock 7 is achieved by means of an AND gate , so that switching of the system clock 7 only within the time window 36 is possible. Interference signals that will be on the line of system clock 7 ignored outside the time window 36.

4 shows a time diagram over the course of a section of the system clock 7. Die The clock frequency of the system clock 7 is, for example, 1 kHz and has an unequal one Duty cycle. After a falling edge 30, after 50, for example µs the rising edge 31. This has the advantage that the Participants 2b, 3ab, 4ab, for example 550 µs after the falling edge 30 one Measurement cycle 32 can start, which is usually in the high state of the system clock 7. With Participant 2b, 3ab, 4ab pays attention to the started measurement cycle 32 to recognize when the next system clock 7 comes. Every 100ms, that means after Every hundredth system clock 7 is a so-called time announcement 37. This Time announcement 37 is recognized by the fact that 550 μs after the falling edge 30 does not System clock high state prevails. The subscriber 2b, 3ab, 4ab thus recognizes that it is the announcement of the time announcement 37. With this time announcement 37 each participant 2b, 3ab, 4ab receives an exact indication of the time that has elapsed since Switching on the machine has passed (absolute time). The advantage is that participants switched on afterwards, i.e. while the machine is already running, always be informed of the absolute time of the machine. Everyone Participants 2b, 3ab, 4ab can then carry out an event that relates to the absolute time relates without having to receive the command for this from the central unit 5a.

Fig. 5 shows a block diagram for controlling two motors. Fig. 5 is opposite 1 expanded in such a way that one motor 20a, b and one each for the motor control card 4a, b Incremental encoders 21a, b have been added. Furthermore, the interface 2a is a Input device 22 for inputs that can be made by the operator of the machine attached. The motor 20a is, for example, the main motor that is used for the rotary movement the cylinder of a printing press is responsible. This motor 20a becomes as follows controlled:

The operator gives the machine a value for the by means of the input device 22 Speed on. This value is via the CAN bus system 10 a of the engine control card 4 a supplied, which determines the control values (current setpoints) for the motor 20a and hires. An incremental encoder 21a is located either directly on the motor 20a sits on the motor shaft of the motor 20a or at a suitable location by the Motor 20a driven gear or gear train. The pulses of the Incremental encoder 21a are read in by the motor control card 4a. The The read-in process always takes place at the time of a system clock 7. From these pulses the engine speed card 4a, the speed, the acceleration and the Angular position of the motor 20a calculated. On the one hand, these calculated values serve the Regulation for the motor 20a, on the other hand, these values are always together with the All other participants 3a, b 4b were informed of the time of detection. By the it is irrelevant whether the data is transferred quickly whether the data is transferred at a certain point in time or whether all Participants receive the data at the same time.

The engine control card 4b also receives these values Processor 2b has been given the task of motor 20b in synchronism with motor 20a operate. Such a task is performed in the engine control card 4b by a so-called Command interpreter implemented. The engine control card 4b now gets regular Distances the values of speed, acceleration and angular position of the motor 20a transmitted. From these values, the setpoints for your own engine 20b calculated.

The time interval between two transmissions of the values speed, acceleration and angular position of the motor 20a with the corresponding indication of the The time of detection is possibly for keeping two motors 20a, b in synchronism too large so that an interpolation takes place in the meantime. This interpolation is based on the engine control card 4b and based on these interpolated values Setpoints for the motor 20b are calculated.

Furthermore, a multiplication unit 11 is located on the motor control card 4b Generation of a module clock 15 according to FIG. 2. The resolution of the module clock 15 is like this dimensioned that the operations running on the motor control card 4b (interpolation the course of the motor 20a, reading in the pulses of the incremental encoder 21b, calculating the actual values of the motor 20b from the pulses of the incremental encoder 21b, calculating new ones Setpoints for the motor 21b, etc.) are all taken into account in a time-optimized manner.

LIST OF REFERENCE NUMBERS

1a, b

processor

2a, b

interface

3a, b

I / O card (participant)

4a, b

Engine control card (participant)

5a, b

unit

5n

further unit

6

VME bus system

7

system clock

8th

System clock conditioning

9

management

10

CAN bus system

11

multiplication unit

12

frequency generator

13

quartz

14

counter

15

module clock

16a, b

Attendees

20a, b

engine

21a, b

incremental

22

input device

30

falling edge

31

rising edge

32

measuring cycle

33

ramp function

34

ramp function

35

ramp function

36

Time window

37

time Of Day

Claims (18)

Device for synchronizing processes running on several units, a central unit being connected to further units via a field bus,
characterized in that the central unit has a device for generating a system clock, that a free line of the field bus is provided for distributing the system clock to the further units and that devices for multiplying the system clock are provided on the further units. Device according to claim 1,
characterized in that the system speed, the speeds n, the acceleration a, the angular position ϕ and possibly other values of the machine can be detected. Device according to claim 2,
characterized in that the detected values such as speed n, acceleration a, angular position ϕ and possibly further values of the machine can be fed to the further units by means of the bus system. Device according to claim 1,
characterized in that the multiplication unit has a filter device. Device according to claim 1,
characterized in that the multiplication unit has a device for detecting an absolute time announcement. Device according to claim 1,
characterized in that the multiplication unit has a quartz-stabilized frequency generator. Device according to claim 2,
characterized in that the multiplication unit generates a module clock for processes taking place in the further units. Device according to claim 3,
characterized in that the module cycle is adjustable according to the process taking place in the further unit. Device according to claim 1
characterized in that the bus system for distributing the system clock is a local bus system. Method for synchronizing processes running on a central unit and on further units, with a system clock generated in a central unit and module clocks generated in the further units,
characterized in that the system clock generated in the central unit is used to synchronize the module clock generated in the further units. A method according to claim 10,
characterized in that the other units are synchronized to an absolute time at regular intervals. A method according to claim 10,
characterized in that the module cycle available in the units involved is used for processes taking place there. A method according to claim 10,
characterized in that, in the event of a system cycle failure, the processes directed by the other units involved are shut down guided by the module cycle. A method according to claim 10,
characterized in that the frequency of the module clock is set according to the operation taking place there A method according to claim 10,
characterized in that the values such as speed n, acceleration a, angular position ϕ and possibly further values of the machine are recorded simultaneously with the system cycle. A method according to claim 10,
characterized in that the values of speed n, acceleration a, angular position ϕ and possibly further values of the machine are forwarded to the other units together with the time of detection. A method according to claim 10,
characterized in that the values of speed n, acceleration a, angular position ϕ and, if appropriate, further values of the machine are determined after transmission by the central unit for the period of time until transmission of the next current values using a calculation model in the units involved. A method according to claim 10,
characterized in that after a defined number of subdivided system clocks, an absolute time is transmitted from the central computer unit to the computer units involved.

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