EP1211070A2 - Dispositif et procédé pour synchroniser des opérations se déroulant dans plusieurs unités - Google Patents

Dispositif et procédé pour synchroniser des opérations se déroulant dans plusieurs unités Download PDF

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Publication number
EP1211070A2
EP1211070A2 EP01126527A EP01126527A EP1211070A2 EP 1211070 A2 EP1211070 A2 EP 1211070A2 EP 01126527 A EP01126527 A EP 01126527A EP 01126527 A EP01126527 A EP 01126527A EP 1211070 A2 EP1211070 A2 EP 1211070A2
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EP
European Patent Office
Prior art keywords
units
values
system clock
clock
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01126527A
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German (de)
English (en)
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EP1211070A3 (fr
EP1211070B1 (fr
EP1211070B2 (fr
Inventor
Kai Albrecht
Ulrich Grimm
Thomas Husterer
Reinhard Janzer
Helmut Meyer
Georg Roessler
Andreas Wagner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Heidelberger Druckmaschinen AG
Original Assignee
Heidelberger Druckmaschinen AG
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Application filed by Heidelberger Druckmaschinen AG filed Critical Heidelberger Druckmaschinen AG
Publication of EP1211070A2 publication Critical patent/EP1211070A2/fr
Publication of EP1211070A3 publication Critical patent/EP1211070A3/fr
Publication of EP1211070B1 publication Critical patent/EP1211070B1/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41F—PRINTING MACHINES OR PRESSES
    • B41F33/00—Indicating, counting, warning, control or safety devices

Definitions

  • the invention relates to a device and a method for the synchronization of Processes that are executed by separate processors and on the system clock of one central unit are coordinated.
  • EP 0 747 216 B1 proposes different units that are associated with Angular position signals must be supplied by means of two bus systems. Each unit continuously receives the current angle value using the one bus system and by means of the other bus system information about one to be carried out Switching operation. The angle setpoint at which the switching process is to be triggered is stored in a memory of the respective unit.
  • the device according to the invention and the corresponding procedure is based on the task, a simple means Bring about synchronization of many processes.
  • the device assumes that a central unit Coordination of various other units in the periphery takes over.
  • the central unit has the task, all on the periphery synchronize running processes.
  • a centrally generated system clock is opened a free line of a field bus, e.g. B. CAN-BUS, to everyone in the process units involved.
  • a field bus e.g. B. CAN-BUS
  • the frequency of the system clock is chosen to be relatively low.
  • the clock signal thus moves in a frequency range, which results in a distribution of the clock signal over longer distances is possible. It is also possible to use an appropriate system clock Filtering measures.
  • the invention proposes Device in front of the incoming system clock in the peripheral unit multiply the requirements.
  • This so-called module clock then generated has the desired resolution, or is advantageously to the desired resolution adjustable.
  • the clock prevailing on the peripheral unit always prevails for the respective process is required.
  • the device according to the invention sees one integrated in the peripheral units Clock generator that is synchronized by the system clock. Between each The clock generator runs free of synchronization intervals due to the system clock. To the Keeping the module clock frequency stable on the peripheral unit suggests one Variant according to the invention to be stabilized using quartz. According to one calculated drift, which results from the quality of the stabilizing quartz, can Time interval of the synchronization interval can be determined.
  • the generation of a local module clock has the advantage that if the in the central unit generated system clock there is no risk that processes run uncontrolled and lead to accidents, since a vote of the independent running processes is no longer possible.
  • the procedure is such that a Failure of the system clock to be recognized by the processor in the peripheral unit, which then controls the process based on the local module cycle to a standstill shuts down.
  • the required time between the absence of the system clock and the controlled shutdown of the process is so short that that already mentioned Drifting the module clock from the system clock does not lead to any noteworthy problems. That means all processes that take place at and through the various peripheral units the system clock are synchronized to each other are generated by the on-site Module cycle brought to a standstill in a controlled manner.
  • a method according to the invention furthermore proposes that, at regular intervals, for example, a so-called after every hundredth system cycle Synchronization interval takes place.
  • the peripheral unit Time announcement 37 which adjusts the peripheral unit to the absolute time.
  • All peripheral units receive synchronization intervals for a time adjustment Absolute time, a so-called time stamp.
  • the peripheral Unit capable of extrapolating the transmitted value to any one To calculate the time between two transmitted values. That is, already through the Time delay in the transmission of the values results in the problem that when receiving the Values that are no longer up to date.
  • the advantage of the procedure is that it is almost irrelevant how long the It takes time to transmit the values because the current value can always be determined.
  • the method according to the invention proposes the following variant:
  • the additional drive is equipped with its own setpoint generator.
  • This Setpoint generator calculates the setpoints for the additional drive. According to the dynamic requirements of the additional drive, sampling cycles are defined during which The actual values of the additional drive are read in and using various control algorithms new setpoints are specified. The actual values of the main drive become discrete Times (for reasons of bus load), but the frequency is lower than the scan cycles of the auxiliary drive. By the one that is also sent The point in time of the actual values of the main drive can determine the further course of the actual values of the main drive on the additional drive calculated at any time (interpolation / extrapolation).
  • An additional application of the device according to the invention or the method is that different motors running synchronously with each other do not follow the Actual values of a main drive, but can be regulated on a central command.
  • a setpoint generator in the peripheral unit ensures three-speed or double-speed for the generation of adjusted target values.
  • All engine governors are now reworking same algorithm and always read the actual values of the motors at exactly the same Time. This time corresponds to the system clock. This ensures that all motors are regulated on a virtual electronic shaft.
  • the processors 1a, b represent together with an interface 2a, b and connected input / output cards 3a, b and engine control cards 4a, b each represent a unit 5a, b. Die respective local components, such as processor 1a and interface 2a, or 1b and 2b are connected to each other by means of the VME bus system 6. Located on the interface 2a there is still a system clock 7. This system clock 7 is e.g. of a CAN bus system 10 to the input / output card 3a located in the periphery and passed the engine control card 4a. The number of input / output cards 3a or the number of engine control cards 4a is irrelevant.
  • an additional Line 9 which is assigned to the CAN bus system 10 as a free line, is the System clock passed to the interface 2b of the unit 5b.
  • a system clock processing 8 for example a filter or a Includes amplifier.
  • the system clock 7 is also sent to the Unit 5b associated input / output card 3b and the motor control card 4b by means of Line 9 forwarded.
  • the input / output card 3b or the subscriber Motor control card 4b can be used by subscribers 16a, b whose use is not defined be expanded.
  • the number of interfaces 2a, b per unit 5a, b be larger than shown in this embodiment.
  • the system clock 7 will continue via the local VME bus system 6a, b all local belonging to the unit 5a, b Components 1a, b and 2a, b provided. There are more via a line 9d Units 5n can be connected to the system clock 7.
  • the multiplication unit 11 has the task of Multiply the resolution according to the required circumstances. This can for example based on an embodiment according to FIG.
  • Fig. 2 shows a block diagram of a multiplication unit 11 as it relates to the various input / output cards 3a, b and motor control cards 4a, b is present.
  • a frequency generator 12 is a clock with a frequency of 1 MHz, for example generated.
  • a crystal 13 is assigned to this for frequency stabilization.
  • a counter 14 is connected to the Frequency generator 12.
  • the system clock 7 Counter 14 started or reset.
  • the system clock 7 has one Clock frequency of 1 kHz, the counter counts within a period of the system clock 7 from 0-999 and repeats this process continuously. Described in more detail, this means that the Pulses of the frequency generator 12 in the event that they are synchronous with the system clock 7 be switched through, so to speak.
  • the synchronized module clock 15 is the output I / O card, 3ab or motor control card 4ab provided.
  • FIG. 3a to 3e several diagrams are shown, the system clock 7 (Fig. 3a) Ramp function of the counter 14 (FIG. 3b) and a fine resolution of the module clock 15 (Fig. 3c, d, e) show.
  • the diagram of Fig. 3a shows the system clock 7, wherein in 3b, the ramp function of the counter 14 always with the falling one Edge 30 of the system clock 7 is started.
  • the Counter 14 within a period, each between the falling edges 30 of the System clock 7 is from 0-999.
  • the ramp functions 33, 34, 35 show different things Behavior which can be explained by the diagrams according to Fig. 3c, d, e. So is in 3c to see that the last count pulse 999 is narrower than the previous ones. This can be explained by the fact that the frequency of the module clock 15 is slightly slower than a thousand times the system clock 7.
  • the 999th count is then replaced by the System clock 7 corrected, which results in synchronization.
  • the diagram of Fig. 3d shows the case that the module clock 15 compared to the System clock 7 is slightly faster than a thousand times the system clock 7. that the counter 14 no longer increases its counter reading at 999 remains the last Count pulse (999) until the counter is reset by the falling one Edge 30 of the system clock 7 takes place. A correction is also made again, or Synchronization.
  • the diagram according to FIG. 3e represents yet another variant When the counter reaches 999, the counter is not affected by the system clock 7 reset because it failed, for example, but there is a Resetting the counter due to exceeding a specified one Time window 36. This time window 36 is at a defined counter reading (e.g. 990) starts and ends, for example, 10 ⁇ s after reaching counter 999.
  • the module clock 15 is forcibly reset, which simultaneously results in that the processes clocked by the module clock 15 from the time of the first Failure of the system clock to be brought to a controlled stop.
  • time window 36 also amounts to filtering.
  • a link between the time window 36 and the system clock 7 is achieved by means of an AND gate , so that switching of the system clock 7 only within the time window 36 is possible. Interference signals that will be on the line of system clock 7 ignored outside the time window 36.
  • the clock frequency of the system clock 7 is, for example, 1 kHz and has an unequal one Duty cycle. After a falling edge 30, after 50, for example ⁇ s the rising edge 31. This has the advantage that the Participants 2b, 3ab, 4ab, for example 550 ⁇ s after the falling edge 30 one Measurement cycle 32 can start, which is usually in the high state of the system clock 7. With Participant 2b, 3ab, 4ab pays attention to the started measurement cycle 32 to recognize when the next system clock 7 comes. Every 100ms, that means after Every hundredth system clock 7 is a so-called time announcement 37.
  • This Time announcement 37 is recognized by the fact that 550 ⁇ s after the falling edge 30 does not System clock high state prevails.
  • the subscriber 2b, 3ab, 4ab thus recognizes that it is the announcement of the time announcement 37.
  • each participant 2b, 3ab, 4ab receives an exact indication of the time that has elapsed since Switching on the machine has passed (absolute time).
  • the advantage is that participants switched on afterwards, i.e. while the machine is already running, always be informed of the absolute time of the machine.
  • everyone Participants 2b, 3ab, 4ab can then carry out an event that relates to the absolute time relates without having to receive the command for this from the central unit 5a.
  • Fig. 5 shows a block diagram for controlling two motors.
  • Fig. 5 is opposite 1 expanded in such a way that one motor 20a, b and one each for the motor control card 4a, b Incremental encoders 21a, b have been added.
  • the interface 2a is a Input device 22 for inputs that can be made by the operator of the machine attached.
  • the motor 20a is, for example, the main motor that is used for the rotary movement the cylinder of a printing press is responsible. This motor 20a becomes as follows controlled:
  • the operator gives the machine a value for the by means of the input device 22 Speed on. This value is via the CAN bus system 10 a of the engine control card 4 a supplied, which determines the control values (current setpoints) for the motor 20a and hires.
  • An incremental encoder 21a is located either directly on the motor 20a sits on the motor shaft of the motor 20a or at a suitable location by the Motor 20a driven gear or gear train.
  • the pulses of the Incremental encoder 21a are read in by the motor control card 4a. The The read-in process always takes place at the time of a system clock 7. From these pulses the engine speed card 4a, the speed, the acceleration and the Angular position of the motor 20a calculated.
  • these calculated values serve the Regulation for the motor 20a, on the other hand, these values are always together with the All other participants 3a, b 4b were informed of the time of detection. By the it is irrelevant whether the data is transferred quickly whether the data is transferred at a certain point in time or whether all Participants receive the data at the same time.
  • the engine control card 4b also receives these values Processor 2b has been given the task of motor 20b in synchronism with motor 20a operate. Such a task is performed in the engine control card 4b by a so-called Command interpreter implemented. The engine control card 4b now gets regular Distances the values of speed, acceleration and angular position of the motor 20a transmitted. From these values, the setpoints for your own engine 20b calculated.
  • the time interval between two transmissions of the values speed, acceleration and angular position of the motor 20a with the corresponding indication of the The time of detection is possibly for keeping two motors 20a, b in synchronism too large so that an interpolation takes place in the meantime.
  • This interpolation is based on the engine control card 4b and based on these interpolated values Setpoints for the motor 20b are calculated.
  • a multiplication unit 11 is located on the motor control card 4b Generation of a module clock 15 according to FIG. 2.
  • the resolution of the module clock 15 is like this dimensioned that the operations running on the motor control card 4b (interpolation the course of the motor 20a, reading in the pulses of the incremental encoder 21b, calculating the actual values of the motor 20b from the pulses of the incremental encoder 21b, calculating new ones Setpoints for the motor 21b, etc.) are all taken into account in a time-optimized manner.

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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Control Of Multiple Motors (AREA)
  • Control By Computers (AREA)
  • Control Of Stepping Motors (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Control Of Velocity Or Acceleration (AREA)
  • Conveying And Assembling Of Building Elements In Situ (AREA)
  • Numerical Control (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Time Recorders, Dirve Recorders, Access Control (AREA)
  • Multi Processors (AREA)
EP01126527A 2000-11-29 2001-11-14 Dispositif et procédé pour synchroniser des opérations se déroulant dans plusieurs unités Expired - Lifetime EP1211070B2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10059270 2000-11-29
DE10059270A DE10059270B4 (de) 2000-11-29 2000-11-29 Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse

Publications (4)

Publication Number Publication Date
EP1211070A2 true EP1211070A2 (fr) 2002-06-05
EP1211070A3 EP1211070A3 (fr) 2003-08-27
EP1211070B1 EP1211070B1 (fr) 2010-06-30
EP1211070B2 EP1211070B2 (fr) 2013-01-16

Family

ID=7665113

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01126527A Expired - Lifetime EP1211070B2 (fr) 2000-11-29 2001-11-14 Dispositif et procédé pour synchroniser des opérations se déroulant dans plusieurs unités

Country Status (8)

Country Link
US (1) US6948085B2 (fr)
EP (1) EP1211070B2 (fr)
JP (1) JP4078065B2 (fr)
CN (1) CN1272173C (fr)
AT (1) ATE472407T1 (fr)
CZ (1) CZ303068B6 (fr)
DE (2) DE10059270B4 (fr)
HK (1) HK1047726B (fr)

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JP3363872B2 (ja) * 2000-06-23 2003-01-08 株式会社東京機械製作所 切断見当及び印刷見当自動調整機能を有する同期制御装置
DE10248690B4 (de) 2001-11-15 2019-10-31 Heidelberger Druckmaschinen Ag Verfahren zur Synchronisation mehrerer elektrischer Antriebseinheiten
DE10312379B4 (de) 2002-04-04 2018-06-28 Heidelberger Druckmaschinen Ag Verfahren und Vorrichtung zur Synchronisation von Antriebskombinationen
DE10246732A1 (de) 2002-10-07 2004-04-15 OCé PRINTING SYSTEMS GMBH Verfahren und Vorrichtung zum Synchronisieren von Aktionen, die über ein lokales, mehrere Mikrokontroller aufweisendes Datennetz gesteuert werden, sowie Verfahren und Vorrichtung zum Senden von Nachrichten über ein solches Datennetzwerk
US7091827B2 (en) * 2003-02-03 2006-08-15 Ingrid, Inc. Communications control in a security system
DE102005039450B4 (de) * 2005-08-18 2008-04-30 Dspace Digital Signal Processing And Control Engineering Gmbh Verfahren und Netzwerk zur synchronen Bearbeitung und Bereitstellung von Daten
US7596711B2 (en) 2005-08-19 2009-09-29 Dspace Digital Signal Processing And Control Engineering Gmbh Method and network for synchronistic processing and providing data using an extrapolation data set including at least one update time point
JP2007219642A (ja) * 2006-02-14 2007-08-30 Fanuc Ltd 制御システム
US8325767B2 (en) 2006-09-29 2012-12-04 Agilent Technologies, Inc. Enhancement of IEEE 1588 synchronization using out-of-band communication path
US20090292388A1 (en) * 2006-12-19 2009-11-26 Tatsushi Iimori Semiconductor manufacturing system
DE102007031709B4 (de) * 2007-07-06 2009-04-30 Schneider Electric Motion Deutschland Gmbh & Co. Kg Elektrischer Antrieb
US8516293B2 (en) * 2009-11-05 2013-08-20 Novell, Inc. System and method for implementing a cloud computer
DE102008039793A1 (de) * 2008-08-26 2010-03-04 Siemens Aktiengesellschaft Verfahren zur Taktsynchronisierung in einem Kommunikationsnetz und Kommunikationsnetz
US9766648B2 (en) 2013-07-16 2017-09-19 Ford Global Technologies, Llc Controller system coordinated using a timing signal and method of controller coordination using a timing signal
JP6236996B2 (ja) 2013-08-28 2017-11-29 富士通株式会社 情報処理装置および情報処理装置の制御方法

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JPH07281785A (ja) 1994-04-05 1995-10-27 Toshiba Corp プロセッサシステム
EP0747216A2 (fr) 1995-06-08 1996-12-11 MAN Roland Druckmaschinen AG Dispositif de commande pour une machine à imprimer

Also Published As

Publication number Publication date
HK1047726B (zh) 2007-02-23
US20020111696A1 (en) 2002-08-15
DE50115536D1 (de) 2010-08-12
CZ20013655A3 (cs) 2002-07-17
JP2002258980A (ja) 2002-09-13
JP4078065B2 (ja) 2008-04-23
CN1272173C (zh) 2006-08-30
DE10059270B4 (de) 2012-08-02
CN1356208A (zh) 2002-07-03
US6948085B2 (en) 2005-09-20
DE10059270A1 (de) 2002-06-06
EP1211070A3 (fr) 2003-08-27
EP1211070B1 (fr) 2010-06-30
EP1211070B2 (fr) 2013-01-16
HK1047726A1 (en) 2003-03-07
CZ303068B6 (cs) 2012-03-21
ATE472407T1 (de) 2010-07-15

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