KR20110005264A - Testing device, transmission circuit, testing device control method and transmission circuit control method - Google Patents
Testing device, transmission circuit, testing device control method and transmission circuit control method Download PDFInfo
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- KR20110005264A KR20110005264A KR1020107025468A KR20107025468A KR20110005264A KR 20110005264 A KR20110005264 A KR 20110005264A KR 1020107025468 A KR1020107025468 A KR 1020107025468A KR 20107025468 A KR20107025468 A KR 20107025468A KR 20110005264 A KR20110005264 A KR 20110005264A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
- G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
Abstract
A test apparatus for testing a device under test, comprising: a test cycle signal indicative of a timing which becomes a reference for the start timing of a test cycle and a test cycle indicative of a delay amount from a test cycle signal to a start timing of a test cycle in synchronization with a reference clock; A test cycle generator for generating data, and a timing generator for generating a timing for transmitting and receiving a signal to and from the device under test based on the start timing of the test cycle specified by the test cycle data. In the case of a cycle in which the test cycle data and the test cycle signal are generated, a data acquisition unit which acquires the test cycle data in synchronization with the reference clock and outputs the test cycle data to the timing generator, and a cycle in which the test cycle signal is not generated. Clock gate section for stopping supply of reference clock to data acquisition section It provides a test device comprising a.
Description
The present invention relates to a test apparatus, a transmission circuit, a control method of the test apparatus, and a control method of the transmission circuit. In particular, the present invention relates to a test apparatus for testing a device under test and a control method of the test apparatus, and a transmission circuit and a transmission circuit for transmitting data and a data enable signal indicating whether the data is valid from a transmission circuit to a reception circuit. It relates to a control method of. This application is an application which claims priority from the following Japanese application with respect to the following Japanese application. Regarding a designated country where inclusion by reference to a document is recognized, the contents described in the following application are incorporated into the present application by reference, and are part of the present application.
1. Japanese Patent Application No. 2008-144581 Filed June 2, 2008
The test apparatus for testing a semiconductor or the like includes a timing generator that generates a timing signal specifying a change point of a test signal to a device under test (see
By the way, the test apparatus propagates the test cycle data generated by the cycle generator by a plurality of flip-flops which are continuously connected, and gives the timing generator of the subsequent stage. However, in recent years, the number of bits of test cycle data is increasing with the improvement of the performance of a device under test and many pinning. In addition, the number of flip flops that propagate the test cycle data from the cycle generator to the timing generator is increasing.
In addition, a test apparatus may generate several timing signals within the range of one test period. In such a case, the timing generator selects and operates a plurality of delay circuits connected in parallel one by one each time the test cycle data is given, thereby generating a plurality of timing signals within a range of one test cycle. .
However, in recent years, with the high performance of the device under test, the number of timing signals to be generated within the range of one test cycle has increased, and the number of the plurality of delay circuits which should be connected in parallel is increasing. This caused the increase in power consumption of the test apparatus.
MEANS TO SOLVE THE PROBLEM In order to solve the said subject, in the 1st aspect of this invention, in the test apparatus which tests a device under test, the test period signal which shows the timing used as a reference of the start timing of a test period in synchronization with a reference clock, and the said test Between the test cycle generator for generating test cycle data indicating a delay amount from the cycle signal to the start timing of the test cycle, and the device under test on the basis of the start timing of the test cycle specified by the test cycle data. A timing generator for generating a timing for sending and receiving a signal, wherein the test cycle generator includes a cycle generator for generating the test cycle data and the test cycle signal, and the test cycle data in synchronization with the reference clock; And a data acquiring unit for outputting to the timing generator The present invention provides a test apparatus including a clock gate section for stopping the supply of the reference clock to the data acquisition section in the case of a cycle in which no signal is generated, and a control method of the test apparatus.
In a second aspect of the present invention, in a transmission circuit for transmitting data and a data enable signal indicating whether the data is valid from a transmission circuit to a reception circuit, the data is transferred from the transmission circuit in synchronization with a reference clock. A clock for stopping the supply of the reference clock to the data acquisition unit when the data acquisition unit acquires and outputs the data enable signal from the transmission circuit to indicate that the data is invalid; A transmission circuit including a gate portion and a control method of the transmission circuit are provided.
In the third aspect of the present invention, in a test apparatus for testing a device under test, timing data and timing data for specifying a timing of generation of a timing signal indicating a timing of transmitting and receiving a signal to and from the device under test are effective. A timing data generator for generating a timing enable signal indicative of whether or not it is operating; and synchronously operating with a reference clock to receive the valid timing data from the timing data generator; A counting unit for counting the reference clock by the number of upper data indicating a time in units of a period or more, and then outputting the lower data other than the upper data of the timing data and the timing enable signal indicating the validity of the timing data. Wow, the count unit is If one does not count the upper side the number of data the contained in the timing data, and provides a control of the apparatus, and such a test device including a clock gate unit for stopping the supply of the reference clock method for the counting section.
In addition, the summary of the above invention does not enumerate all of the necessary features of the present invention, and the subcombination of such a feature group can also be invented.
FIG. 1: shows the structure of the
2 shows an example of a bit configuration of test period data output by the
3 shows a reference clock, test period data output by the
4 shows the configuration of a
5 shows a configuration of a
6 shows an example of the configuration of the
FIG. 7 shows an example of the configuration of the
8 shows an example of a timing chart of each signal in the
9 shows the configuration of the
10 shows an example of a timing chart of timing enable signals input to the plurality of
11 shows an example of a timing enable signal output from the plurality of
12 shows the configuration of the
13 shows an example of a timing chart of each signal in the
EMBODIMENT OF THE INVENTION Hereinafter, although this invention is demonstrated through embodiment of invention, the following embodiment does not limit the invention based on a claim, and all the combination of the characteristics demonstrated in embodiment are essential for the solution of this invention. Can not.
FIG. 1: shows the structure of the
The
The
The
The
The
The
2 shows an example of a bit configuration of test period data output by the
The test cycle data includes a plurality of bits. For example, in the example of FIG. 2, the test period data includes (J + K) bits (J and K are natural numbers).
As the test period data, as an example, the bit of the reference position (for example, the bit of the position of n in FIG. 2) represents a delay time of one cycle (T time) of the reference clock. Each time the test cycle data advances from one bit of the reference position to one bit, each bit is twice, four times, eight times,... , A delay time that is 2 K times (K is a natural number). In addition, each time the test cycle data advances one bit from the bit of the reference position to the lower one, each bit is 1/2, 1/4, 1/8, ... of the 1 cycle of the reference clock. , 2 -J times (J is a natural number).
Hereinafter, in this embodiment, the part which shows the delay time less than 1 period T of the reference clock in test period data is called the lower bit of test period data. In addition, in this embodiment, the part which shows the delay time of 2 cycles (2 * T) or more of the reference clock in test period data is called an upper bit of test period data. In other words, in the present embodiment, the test cycle data indicates an upper time indicating a unit of time larger than the period of the reference clock in the delay time from the timing at which the
3 shows a reference clock, test period data output by the
Therefore, when a test period is less than 2 cycles (2 x T) of the reference clock, that is, from the start timing of the test cycle specified by the test cycle data to the start timing of the test cycle specified by the next test cycle data When the interval of is less than two cycles, the
4 shows the configuration of a
The
5 shows a configuration of a
The lower bit acquisition flip-
The
The
And the
The clock enable
The first
Here, the first
In addition to the above, the first
When it is detected that the upper bits of the test period data coincide with a predetermined value (0 in the present embodiment), the
The test cycle
6 and 7 show an example of a specific circuit configuration of the
The lower
The upper
As an example, as shown in FIG. 7, the
The AND circuit 74 in the detection unit outputs the result of ANDing the output signal of the
The clock enable
As an example, as shown in FIG. 7, the first
In addition, each of the n gate circuits 78-1 to 78-n receives a clock enable signal input to the corresponding flip-
As an example, as shown in FIG. 6, the
The
In addition, such
The test period
8 shows an example of a timing chart of each signal in the
8A shows a reference clock. RATE_IN in FIG. 8B shows a test cycle signal generated by the
Gckl_1 in FIG. 8D shows a reference clock given by the first
Gckl_2 in FIG. 8G shows a reference clock given by the first
Gckl_3 in FIG. 8J shows the reference clock that the first
RATE_OUT in FIG. 8M shows a test period signal that the
As shown in Fig. 8C, the
Here, the test cycle data RATE2 having the value "0x23", the test cycle data RATE3 having the value "0x37", and the test cycle data RATE5 having the value "0xF1" are not the upper bit. In this case, the first
On the other hand, the test cycle data RATE1 having the value "0x0C" and the test cycle data RATE4 having the value "0x05" have an upper bit of zero. Thus, in the period of the reference clock following this test period data, other test period data RATE2 and RATE5 are generated. In this case, the first
In addition, as shown in FIGS. 8L and 8M, the
In addition, as shown in FIG. 8B, the test cycle signal from the test cycle data RATE2 having the value "0x23" to the test cycle data RATE3 having the value "0x37" indicates invalidity. have. In addition, the test cycle signal from the test cycle data RATE3 having the value "0x37" to the test cycle data RATE4 having the value "0x05" is also invalid. In this case, the first
As described above, the
As a result, the
In particular, when the upper bit of the test period data is 0, since the valid test period data propagates continuously at the interval of the reference clock, power consumption increases. Therefore, when the upper bit of the test period data is 0, the power consumption can be reduced with good efficiency by stopping the reference clock used for propagation of the upper bit of the valid test period data.
In this
In this case, the
In addition, such a
In this case, the
9 shows the configuration of the
The
As an example, the
The
Each of the plurality of
Each of the plurality of
The
The
The
According to the
10 shows an example of a timing chart of timing enable signals input to the plurality of
FIG. 10C shows a timing enable signal received by the first counter delay unit 114-1 from the
Each time the
11 shows an example of a timing enable signal output from the plurality of
FIG. 11A illustrates a timing enable signal output from the first counter delay unit 114-1. FIG. 11B shows the lower side data output from the first counter delay unit 114-1. FIG. 11C shows a timing enable signal output from the second counter delay unit 114-2. FIG. 11D shows lower data output from the second counter delay unit 114-2. FIG. 11E shows the timing enable signal output from the third counter delay unit 114-3. Fig. 11F shows the lower side data output from the third counter delay unit 114-3.
FIG. 11E shows a timing enable signal output from the first combining
The
In this way, the
12 shows the configuration of the
The
The
The
The first AND
The
The
As an example, the
The second
As an example, the second
The
More specifically, the second
The
13 shows an example of a timing chart of each signal in the
FIG. 13E shows a state signal output from the second flip-
As illustrated in FIG. 13B, the
In addition, when the timing enable signal indicating validity is received from the
As shown in FIG. 13H, the first AND
As illustrated in FIG. 13G, when the count value of the
Thus, the
In addition, such a
In this case, the
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various modifications or improvements can be added to the above embodiments. It is clear from description of a claim that the form which added such a change or improvement can also be included in the technical scope of this invention.
The order of execution of each process such as operations, procedures, steps, and steps in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not specifically stated as "before", "before", or the like. In addition, it should be noted that the output of the previous process can be used in any order unless the output is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if described using "priority", "next," etc. for convenience, it does not mean that it is essential to implement in this order.
10
22
26
30
34
40
44 Flip-flop for
48
52 Clock Enable
56 Data switch 58 Test cycle signal transmission circuit
60 lower
64 flip-
68 AND circuit in
74 AND circuit in the
78
110
114
118
132
142
150 zero
154
158 First Flip-
162
166
200 device under test
Claims (15)
A test cycle generator for generating a test cycle signal indicative of a timing which becomes a reference for the start timing of a test cycle and test cycle data indicative of a delay amount from the test cycle signal to a start timing of a test cycle in synchronization with a reference clock; And
A timing generator for generating a timing for transmitting and receiving a signal to and from the device under test based on the start timing of the test period specified by the test period data.
Including,
The test cycle generator,
A period generator which generates the test period data and the test period signal;
A data acquisition unit that acquires the test period data and outputs the test cycle data to the timing generator in synchronization with the reference clock; And
A clock gate section for stopping the supply of the reference clock to the data acquisition section in the case where the test period signal is not generated
Including,
tester.
The test cycle generator may further include a detector configured to detect whether at least one predetermined bit in the test cycle data generated by the cycle generator matches a predetermined value,
Wherein the clock gate section is the cycle in which the test period signal is not generated or when it is detected that the at least one bit in the test period data coincides with the predetermined value, the data acquisition section is the at least one To stop the supply of the reference clock used to acquire the bits of
The test period generator is configured to replace the at least one bit from the data acquiring unit when the at least one bit in the test period data matches the predetermined value. Further comprising a data switching unit for supplying to the timing generator,
tester.
The detecting unit detects whether or not an upper bit of a predetermined number of bits as the at least one bit in the test period data generated by the period generating unit coincides with the predetermined value.
tester.
The period generation unit includes the test including the upper bit indicating a time in a unit larger than the period of the reference clock and the lower bit indicating a time in a unit less than the period of the reference clock in the time until the start timing of a test period. Periodic data, and generating the test period signal,
The detection unit detects whether the upper bit is 0,
The clock gate section supplies the reference clock used by the data acquisition unit for acquiring the upper bits when the test period signal is a cycle in which the test period signal is not generated or when the upper bit of the test period data is detected as 0. Stop,
The data switching unit supplies 0 to the timing generator in place of the upper bit from the data acquiring unit when the upper bit of the test period data is detected as zero.
tester.
The data acquisition unit,
In synchronization with the reference clock, the lower bit of the test period data is acquired by a flip-flop at the first stage, sequentially propagated to a flip-flop at a later stage, and output to the timing generator from the flip-flop at the last stage. Transmission circuits; And
Synchronizing with the reference clock, the upper bits of the test period data are acquired by a flip-flop at the first stage, sequentially propagated to a flip-flop at the next stage, and output to the timing generator from the flip-flop at the last stage. Transmission circuit
Including,
The test cycle generator,
A clock enable signal that acquires a clock enable signal indicating whether to supply the reference clock used for acquiring the higher bits in synchronization with the reference clock by a first flip-flop, and sequentially propagates to a subsequent flip-flop Signal transmission circuits; And
In synchronism with the reference clock, a test cycle signal transmission circuit for acquiring the test cycle signal by a flip-flop at the first stage, sequentially propagating to a flip-flop at the next stage, and outputting the flip-flop at the last stage to the timing generator.
Including,
The clock gate portion flips to the next stage in the higher bit transfer circuit when the clock enable signal at either stage propagated by the clock enable signal transfer circuit stops supplying the reference clock. To stop the supply of the reference clock to the flop,
tester.
The data switching section being output from the last stage of the higher bit transfer circuit when receiving the clock enable signal indicating that the supply of the reference clock is stopped from the last stage of the clock enable signal transfer circuit. Outputting 0 to the timing generator in place of the upper bits of the periodic data,
tester.
A data acquisition unit that acquires the data from the transmission circuit and outputs the data to the reception circuit in synchronization with a reference clock; And
A clock gate section for stopping the supply of the reference clock to the data acquisition section when receiving the data enable signal from the transmission circuit indicating that the data is invalid;
Including,
Transmission circuit.
A detector for detecting whether at least one predetermined bit in the data coincides with a predetermined value,
When the clock gate unit receives the data enable signal from the transmitting circuit that the data is invalid, or when it is detected that the at least one bit in the data matches the predetermined value, The data acquiring unit stops supplying the reference clock used for acquiring the at least one bit,
Data for supplying the predetermined value to the receiving circuit in place of the at least one bit from the data acquiring unit, when it is detected that the at least one bit in the data coincides with the predetermined value. Further comprising a switching unit,
Transmission circuit.
A timing data generator for generating timing data specifying timing of generation of a timing signal indicative of timing of signal exchange with the device under test and a timing enable signal indicating whether the timing data is valid;
Operating in synchronization with a reference clock to receive the timing data valid from the timing data generator, and then counting the reference clock by the number of higher-order data representing time in units of the period of the reference clock included in the timing data. A counting unit which outputs the lower side data other than the upper side data of the timing data and the timing enable signal indicating the validity of the timing data; And
A clock gate section for stopping the supply of the reference clock to the count section when the count section does not count the number of upper data contained in the valid timing data
Including,
tester.
The clock gate unit,
In response to receiving the timing enable signal indicating the validity of the timing data, the supply of the reference clock to the counting unit is started so that the count value of the counting unit becomes a value after counting the number of higher-order data. To stop the supply of the reference clock to the counting unit,
tester.
And a state maintaining unit which holds a state signal indicating whether the count unit is counting the number of upper data included in the valid timing data.
The counting unit holds the state signal indicating that the state maintaining unit is counting, while the counting enable indicating the validity of the timing data when a count value becomes a value after counting the upper data count. Outputting a signal,
tester.
A plurality of groups of the counting unit, the clock gate unit, and the state maintaining unit;
And a distribution unit that distributes the valid timing data sequentially output from the timing data generation unit and the timing enable signal indicating the validity of the timing data to each of the plurality of groups.
tester.
The test device,
A test cycle generator for generating a test cycle signal indicative of a timing which becomes a reference for the start timing of a test cycle and test cycle data indicative of a delay amount from the test cycle signal to a start timing of a test cycle in synchronization with a reference clock; And
A timing generator for generating a timing for transmitting and receiving a signal to and from the device under test based on the start timing of the test period specified by the test period data.
Including,
The test cycle generator,
A period generator which generates the test period data and the test period signal;
A data acquisition unit for acquiring the test period data and outputting the test cycle data to the timing generator in synchronization with the reference clock;
Including,
Stopping the supply of the reference clock to the data acquisition unit when the test period signal is a cycle in which no test cycle signal is generated;
Control method of the test device.
The transmission circuit includes a data acquisition unit that acquires the data from the transmission circuit and outputs the data to the reception circuit in synchronization with a reference clock.
Stopping the supply of the reference clock to the data acquiring unit when the data enable signal is received from the transmission circuit to indicate that the data is invalid;
Control method of the transmission circuit.
The test device,
A timing data generator for generating timing data specifying timing of generation of a timing signal indicative of timing of signal exchange with the device under test and a timing enable signal indicating whether the timing data is valid; And
Operating in synchronization with a reference clock to receive the timing data valid from the timing data generator, and then counting the reference clock by the number of higher-order data representing time in units of the period of the reference clock included in the timing data. After that, a counting unit that outputs the lower side data other than the upper side data of the timing data and the timing enable signal indicating the validity of the timing data.
Including,
If the counting unit does not count the number of the upper data contained in the valid timing data, supplying the reference clock to the counting unit is stopped;
Control method of the test device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008144581 | 2008-06-02 | ||
| JPJP-P-2008-144581 | 2008-06-02 | ||
| PCT/JP2009/002301 WO2009147797A1 (en) | 2008-06-02 | 2009-05-25 | Testing device, transmission circuit, testing device control method and transmission circuit control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20110005264A true KR20110005264A (en) | 2011-01-17 |
| KR101239121B1 KR101239121B1 (en) | 2013-03-11 |
Family
ID=41397883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020107025468A KR101239121B1 (en) | 2008-06-02 | 2009-05-25 | Testing device, transmission circuit, testing device control method and transmission circuit control method |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5202628B2 (en) |
| KR (1) | KR101239121B1 (en) |
| TW (1) | TWI388863B (en) |
| WO (1) | WO2009147797A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9054719B2 (en) | 2013-03-21 | 2015-06-09 | Advantest Corporation | Current compensation circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113466675B (en) * | 2021-05-26 | 2022-06-21 | 中国电子科技集团公司第五十四研究所 | Test vector generation method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3773617B2 (en) * | 1997-02-28 | 2006-05-10 | 沖電気工業株式会社 | Clock signal supply device |
| JP4293840B2 (en) * | 2003-06-06 | 2009-07-08 | 株式会社アドバンテスト | Test equipment |
| JP2005038187A (en) * | 2003-07-15 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2006038831A (en) * | 2004-06-23 | 2006-02-09 | Fujitsu Ltd | Semiconductor integrated circuit having scan test circuit |
| JP4477450B2 (en) | 2004-08-12 | 2010-06-09 | 株式会社アドバンテスト | Timing generator, test apparatus, and skew adjustment method |
| JP2007183860A (en) * | 2006-01-10 | 2007-07-19 | Nec Electronics Corp | Clock control circuit |
-
2009
- 2009-05-25 KR KR1020107025468A patent/KR101239121B1/en not_active IP Right Cessation
- 2009-05-25 WO PCT/JP2009/002301 patent/WO2009147797A1/en active Application Filing
- 2009-05-25 JP JP2010515748A patent/JP5202628B2/en not_active Expired - Fee Related
- 2009-06-01 TW TW98118033A patent/TWI388863B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9054719B2 (en) | 2013-03-21 | 2015-06-09 | Advantest Corporation | Current compensation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5202628B2 (en) | 2013-06-05 |
| KR101239121B1 (en) | 2013-03-11 |
| TWI388863B (en) | 2013-03-11 |
| TW201000928A (en) | 2010-01-01 |
| WO2009147797A1 (en) | 2009-12-10 |
| JPWO2009147797A1 (en) | 2011-10-20 |
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