JP2007183860A - Clock control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stop supply of clock to a module while each module does not require processing and to reduce consumed electric current generated on a clock line, in an image processing circuit for processing image data from a CCD sensor. <P>SOLUTION: This clock control circuit comprises a clock request signal output circuit that determines duration of effective data in each module for performing image processing, and outputs a clock request signal to duration required for processing the effective data, and a clock generator for supplying the clock to the module corresponding to the duration when the clock request signal from each module is active. The clock is supplied only for the duration required by each module. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock control circuit, and more particularly to a clock control circuit of an image processing circuit for a CCD sensor.

  A clock to each module for performing image processing in a camera image processing circuit for a CCD (Charge Coupled Devices) sensor is always supplied from the clock generation circuit, and image data from the CCD sensor is obtained. Since the clock to all modules is operating during the receiving period, the current consumed in the clock line is large.

  A mechanism for controlling clock supply / stop for the clock generation circuit by software is generally known, but with this mechanism, it is not possible to control by software that the clock is stopped only during the period of invalid data from the CCD sensor. Therefore, the clock is always supplied to all modules while the sensor is operating.

A conventional clock generation circuit will be described with reference to FIG.
The image processing circuit of FIG. 1 includes a CCD sensor, modules 1, 2, and 3 and a clock generator. The image processing circuit is connected to the outside (memory or the like).
In FIG. 1, for example, the module 1 is a noise reduction module. Also, the module 2 is expressed as a combination of three colors of red (R), green (G), and blue (B) from raw (raw) data in a format that preserves data recorded by the video device as it is. The conversion module converts the data into RGB (Red-Green-Blue) data. Further, the module 3 is a resize module. The clock generator is a clock generator that supplies a clock to each module. At this time, while the image from the CCD sensor is being captured, a clock is supplied from the clock generator to each of the three modules. Further, in an LSI (Large Scale Integration), a current proportional to the clock frequency is consumed on the clock line from the clock generator to the circuit of each module.

As a related technique, Japanese Patent Laid-Open No. 11-328111 (Patent Document 1) discloses a clock synchronous bus circuit.
This prior art relates to a clock synchronous bus circuit having a bus unit as at least three or more bus components. The clock synchronous bus circuit includes a clock generator capable of supplying and stopping a bus clock independently for each bus unit, a first bus unit as a bus master and a second bus as a target in a certain bus cycle. When the unit performs an input / output operation on the bus, the clock supply to the third bus unit not related to the bus cycle is stopped, and the clock supply to the third bus unit is resumed at the end of the bus cycle. It comprises control means for controlling the clock generator.

Japanese Patent Laid-Open No. 11-149437 (Patent Document 2) discloses a data transfer memory device.
The data transfer memory device has a function of transferring data on one system bus, and includes a plurality of memory devices controlled by a data processing unit that processes the data. Each of the plurality of memory devices includes a return clock input / output unit that inputs / outputs a return clock generated based on a clock output from the data processing unit, and a return clock output from the return clock input / output unit Output activation means for activating the output of the data based on a data output enable signal generated based on the above. This data transfer memory device is a technology related to a return clock of a memory system, and performs output activation and data output of each memory device with a return clock and an output enable signal generated by a memory device farthest from the data processing unit. .

Japanese Patent Application Laid-Open No. 8-234861 (Patent Document 3) discloses a low power consumption processor.
This low power consumption processor is characterized in that means for enabling or disabling separate clock inputs of a plurality of circuit blocks of a processor for processing a program is provided outside the processor. That is, it is possible to have a clock control circuit outside the processor, and to stop the clock supply to the unused circuit of the processor by a control signal from the processor.

Japanese Patent Application Laid-Open No. 5-150870 (Patent Document 4) discloses a power consumption reduction method for an arithmetic circuit.
This arithmetic circuit power consumption reduction method includes a switch for turning on and off the supply of a clock to each functional block and a control for each switch in the arithmetic circuit having a plurality of functional blocks configured by semiconductor circuits based on a CMOS process. And a control block for controlling the clock supply to each functional block, and the power supply of the arithmetic circuit is reduced by controlling the clock supply sequence for each functional block by a program.

Japanese Unexamined Patent Publication No. 2003-271986 (Patent Document 5) discloses a three-dimensional graphic drawing apparatus.
The three-dimensional graphic drawing apparatus includes a three-dimensional data storage unit that stores three-dimensional data, a geometry processing unit that inputs the three-dimensional data from the three-dimensional data storage unit and performs geometry processing to obtain vertex data, and the geometry Rendering processing means for performing rendering processing on the vertex data output from the processing means to generate pixel data, and a frame buffer for storing the pixel data generated by the rendering processing means.
Further, the present invention is characterized by further comprising a clock control means for controlling operations of the geometry processing means and the rendering processing means by a clock signal supplied to the geometry processing means and the rendering processing means.

Japanese Unexamined Patent Publication No. 2005-215757 (Patent Document 6) discloses a signal processing apparatus.
This signal processing apparatus is an apparatus that processes an information signal by a plurality of signal processing circuits having different processing functions. The signal processing device receives clock generation means for generating an operation clock, and a request signal for requesting an operation clock generated for each of the plurality of signal processing circuits, and outputs the request signal to the plurality of signal processing circuits. Arbitration means that performs arbitration processing on the request signal according to the assigned priority order, and selectively supplies the operation clock obtained by the clock generation means to the plurality of signal processing circuits according to the arbitration result. It is characterized by that. In this signal processing device, the clock request signal from the signal processing circuit is arbitrated in accordance with the priority order and the clock is supplied to one of the circuits, so that a plurality of processing circuits cannot operate simultaneously.

JP 11-328111 A JP-A-11-149437 JP-A-8-234861 Japanese Patent Laid-Open No. 5-150870 JP 2003-271986 A JP 2005-215757 A

  In the prior art, even when the CCD sensor is in operation, the image processing circuit in the LSI does not need to operate during the period in which the data in the vertical synchronization period and the horizontal synchronization period is invalid. The clock supplied from the clock generator to the module can be stopped during this period. However, in these periods, it is too short for the CPU to control the supply and stop of the clock to each module to the clock generator by software. If the clock frequency of the CPU is sufficiently higher than the clock to each module, the clock supply stop may be realized by software control, but the current consumption on the CPU side increases. Further, since each module of the image processing circuit processes data from the CCD sensor in a bucket relay manner, the timing at which each module processes valid data varies depending on the module as shown in FIG. In order for the CPU to detect these timings and perform clock control, the clock frequency of the CPU needs to be sufficiently higher than the clock frequency of the module, and current consumption on the CPU side increases. For this reason, it is difficult to perform clock supply stop control by software in accordance with the timing of the valid data processing period of each module.

  In the following, means for solving the problem will be described using the numbers used in [Best Mode for Carrying Out the Invention] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

Clock request signal output circuit (2, 3, 4) that determines the period of valid data in each of a plurality of modules that perform different image processing and outputs a clock request signal in a period necessary for processing valid data When,
A clock control circuit comprising: a clock generator (5) that receives the clock request signal and supplies a clock to a module from which the clock request signal is output during a period in which the clock request signal is active.

  When the modules of the image processing circuit do not operate, the clocks to those modules can be automatically stopped, and the current consumption of the LSI can be reduced. The reason is that a buffer circuit for accurately propagating the clock waveform is inserted in the clock line to each module, so the clock line changes to HIGH / LOW at the rising / falling timing of the clock signal. Therefore, since the transistors constituting the buffer repeatedly charge / discharge the wiring load capacitance, current is consumed in this portion, but consumption of these currents can be suppressed by stopping the clock. Because.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 3 is a block diagram showing a configuration including a clock control mechanism of the image processing circuit of the present invention.
The image processing circuit of the present invention includes a CCD sensor module 1 (sensor in FIG. 3), a noise reduction module 2 (module 1 in FIG. 3), a color conversion module 3 (module 2 in FIG. 3), and a resizing module 4 ( 3 includes a module 3), a CPU 5, and a clock generator 6 (clock generator of FIG. 3).

  The CCD sensor module 1 outputs RAW (raw) data. The RAW data is a format in which data recorded by the video device is stored as it is. The noise reduction module 2 receives the raw data from the CCD sensor module 1, refers to the information on the surrounding pixels of interest, determines that the dot whose data changes significantly is noise, and averages it with the surrounding pixel information Output data. The color conversion module 3 inputs the RAW data from the noise reduction module 2, converts it to the YUV format, and outputs it. The YUV format is a format in which a color is represented by three pieces of information: a luminance signal (Y), a difference between the luminance signal and the blue component (U), and a difference between the luminance signal and the red component (V). The resizing module 4 inputs the YUV format data from the color conversion module 3, enlarges / reduces the input image data, and outputs it. The CPU 5 receives a command from the host device and performs parameter setting for each module, error processing, and the like. The clock generator 6 starts a clock for the CPU 5 and generates a clock for each module.

  The CCD sensor module 1 and the noise reduction module 2 are connected via an image data bus 7. A synchronization signal (vertical synchronization signal, horizontal synchronization signal) output from the CCD sensor module 1 is input to the noise reduction module 2 via the image data bus 7. The noise reduction module 2 and the color conversion module 3 are connected via an image data bus 8. The vertical synchronization signal and horizontal synchronization signal output from the noise reduction module 2 are input to the color conversion module 3 via the image data bus 8. The color conversion module 3 and the resizing module 4 are connected via an image data bus 9. The vertical synchronization signal and horizontal synchronization signal output from the color conversion module 3 are input to the resizing module 4 via the image data bus 9. Image data output from the resizing module 4 is output from the image processing circuit to the outside (memory 10 or the like). The vertical synchronization signal and horizontal synchronization signal output from the resizing module 4 are also output to the outside from the image processing circuit.

  A clock from the clock generator 6 is input to each of the noise reduction module 2 (module 1), the color conversion module 3 (module 2), and the resizing module 4 (module 3). A clock request signal from each module is input to the clock generator 6. At this time, each module includes a clock request signal output circuit (not shown) that outputs a clock request signal, and the clock generator 6 includes a clock supply circuit (not shown) that outputs a clock.

Next, the operation will be described.
FIG. 4 is a schematic diagram of image data output from the CCD sensor module 1. In FIG. 4, one frame (one screen) is composed of five lines. At this time, as shown in FIG. 5, valid data for five lines is included between the vertical synchronization signals.

  Image data output from the CCD sensor module 1 is input to the noise reduction module 2 via the image data bus 7. The data format of the image data bus in this part is the RAW format. The noise reduction module 2 is informed of the start of a frame of image data by a vertical synchronization signal output from the CCD sensor module 1 and the start of one line of image data by a horizontal synchronization signal. The image data whose noise has been reduced by the noise reduction module 2 is input to the color conversion module 3 via the image data bus 8. The data format of the image data bus in this part is RAW data. The noise reduction module 2 outputs a vertical synchronization signal to the color conversion module 3 at the start of a frame of noise-reduced image data and a horizontal synchronization signal at the start of a line. The YUV format data converted by the color conversion module 3 is input to the resize module 4 via the image data bus 9. The color conversion module 3 outputs a vertical synchronization signal to the resizing module 4 at the start of the frame of the color-converted image data and a horizontal synchronization signal at the start of the line. The image whose image size has been enlarged or reduced by the resizing module 4 is output from the image processing circuit to the outside. The resizing module 4 outputs a vertical synchronizing signal at the start of a frame of enlarged or reduced image data and a horizontal synchronizing signal at the start of a line.

  The noise reduction module 2 outputs a clock request signal to the clock generator 6 when the vertical synchronization signal output from the CCD sensor module 1 is inactive and when the horizontal synchronization signal is inactive. The clock generator 6 supplies a clock to the noise reduction module 2 only while the clock request signal from the noise reduction module 2 is active.

  The color conversion module 3 outputs a clock request signal to the clock generator 6 during a period in which the vertical synchronization signal output from the noise reduction module 2 is inactive and a period in which the horizontal synchronization signal is inactive. The clock generator 6 supplies a clock to the color conversion module 3 only while the clock request signal from the color conversion module 3 is active.

  The resizing module 4 outputs a clock request signal to the clock generator 6 during a period in which the vertical synchronization signal output from the color conversion module 3 is inactive and a period in which the horizontal synchronization signal is inactive. The clock generator 6 supplies a clock to the resizing module 4 only while the clock request signal from the resizing module 4 is active.

  Thus, the clock request signal is generated as shown in FIG.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 6 is a block diagram showing a configuration of an image processing circuit according to the second embodiment of the present invention. In FIG. 3, each module transmits a clock request signal to the clock generator 6. In this embodiment, each module transmits to the clock generator 6 a clock request signal of a module that processes data next.

  The CCD sensor module 1 transmits a vertical synchronization signal, a horizontal synchronization signal, and image data to the noise reduction module 2 that processes image data next, and is active only for a period during which the noise reduction module 2 operates to the clock generator 6. The clock request signal is transmitted.

  Similarly, the following modules transmit to the clock generator 6 a clock request signal for a module that processes image data next.

  Even in this configuration, a clock request signal can be generated so that a clock signal can be supplied from the clock generator 6 only during a period during which each module operates.

Next, the configuration and operation of the best mode for carrying out the present invention will be described using specific examples.
As one of the algorithms of the noise reduction module 2, referring to the same color data on both sides of interest, if the value of the data of extreme attention is different from both sides, it is determined as noise, and the data of interest is an average of both sides There is a method of using data. At this time, since there is no image data in the vertical synchronization section and the horizontal synchronization section, it is not necessary to operate the noise reduction circuit. Therefore, the noise reduction module 2 generates a signal that becomes active at a time other than the vertical synchronization interval and the horizontal synchronization interval as the clock request signal, and outputs the signal to the clock generator 6.

  When the clock request signal received from the noise reduction becomes active, the clock generator 6 releases the clock gate for the noise reduction module 2 and supplies the clock to the noise reduction module 2.

  When the noise reduction module 2 does not need to operate, the clock generator 6 stops supplying the clock to the noise reduction module 2, so that the current consumed by the clock line can be suppressed.

  When the period in which each module does not require a clock is several clocks before and after the synchronization signal, the operation is performed as shown in FIG.

  The CPU 5 sets a vertical synchronization parameter and a horizontal synchronization parameter in a counter (not shown) provided in the clock generator 6 so that the clock is supplied only during the valid data period. At this time, a vertical synchronization parameter and a horizontal synchronization parameter may be set in a register (not shown) provided in the clock generator 6 so that the counter reads the parameter set in the register. Parameters can be set for the front side and rear side of each synchronization signal. When receiving the vertical synchronization signal, the clock generator 6 starts counting for the front side and the rear side for the vertical synchronization. When the vertical synchronization rear side count reaches the set value, the clock request signal is changed to active. When the vertical synchronization pre-count reaches the set value, the clock request signal is changed to inactive. When the horizontal synchronization signal is received, the front count for horizontal synchronization and the count for the rear side are started. When the horizontal synchronization rear count reaches a set value, the clock request signal is changed to active. When the horizontal synchronization pre-count reaches the set value, the clock request signal is changed to inactive. Thereby, it is possible to provide a period during which the clock generator 6 does not output a clock to each module before and after the clock request signal output from each module.

  As described above, the clock control circuit of the present invention controls the clock supplied to a plurality of modules that perform image processing in the image processing circuit for the CCD sensor.

  An object of the present invention is to detect the period during which each module is processing valid data with respect to a plurality of modules that perform image processing in an image processing circuit for a CCD sensor, and to detect only the necessary period. The control for supplying the clock to each module is executed to reduce the current consumption of the entire circuit.

  For this reason, the clock control mechanism for image processing circuit according to the present invention includes a plurality of modules that perform different image processing, and a clock request signal in a period necessary for determining valid data periods and processing valid data in each module. And a clock generator for supplying a clock to a module corresponding to a period in which the clock request signal from each module is active. The clock generator stops the clock for each module by the number of set values counted by the counter before and after the clock request signal is activated, the register to which the value is set by the CPU, the counter, and the clock request signal. Is provided.

  The clock request signal output circuit actively changes the clock request signal to the clock generator other than the valid period of data input to each module, that is, the period of the vertical synchronization signal and the horizontal synchronization signal. The clock generator starts supplying the clock to the module that has output the clock request signal from the next clock after the clock request signal from each module becomes active. The clock supply to the module that has output the clock request signal is stopped from the next clock after the clock request signal from each module becomes inactive.

  If each module requires a clock several clocks before and after the synchronization signal, a counter is provided in the clock generator, and the clock generator can be adjusted from each module by appropriately increasing or decreasing the register value set in advance by the CPU. This is dealt with by providing a period during which the clock is not output before and after the received clock request signal.

  That is, the image processing circuit of the present invention is different in the timing at which each image processing module processes image data in an image processing circuit including a plurality of image processing modules. The image processing module is characterized in that it determines a period of valid data and generates a clock request signal only for a period necessary for processing valid data. A clock generator is provided that receives a clock request signal and supplies a clock to the module from which the clock request signal is output only during a period when the signal is active. The clock generator is characterized by having a function capable of stopping the clock output before and after the clock request signal according to the setting of the CPU. Each image processing module receives a clock supply from a clock generator independently.

The image processing circuit of the present invention is a synchronous type but not a bus circuit, and the connection form of the modules (modules 1, 2, 3) is such that the modules are connected by a dedicated I / F (interface), or the module And SDRAM are connected by DMA. Then, while each module operates simultaneously, a clock request signal is output only for a necessary period and a clock supply is received.
The image processing circuit of the present invention performs clock control inside the LSI. At this time, clock supply control is performed not by a program but by a function of H / W (hardware). Furthermore, a clock is supplied as soon as a request signal is received.

  As an application example of the present invention, use in a digital camera or an image processing circuit mounted on a mobile phone is conceivable. However, it is not limited to these examples.

FIG. 1 is a block diagram showing a conventional configuration diagram. FIG. 2 is a timing chart of the vertical synchronization signal and horizontal synchronization signal received by each module (modules 1, 2, and 3). FIG. 3 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. FIG. 4 shows the structure of frames and lines of image data. FIG. 5 is a timing chart of the vertical synchronization signal, horizontal synchronization signal, valid image data, and clock request signal in the configuration of FIG. FIG. 6 is a block diagram showing the configuration of the second exemplary embodiment of the present invention. FIG. 7 is a timing diagram of the synchronization signal, the front count, the rear count, and the clock request signal when the clock request signal is made inactive before and after the synchronization signal.

Explanation of symbols

1 Sensor (CCD sensor module)
2 Module 1 (Noise reduction module)
3 Module 2 (color conversion module)
4 Module 3 (Resize module)
5 CPU
6 Clock generator (clock generator)
7 Image data bus (between CCD sensor module and noise reduction module)
8 Image data bus (between noise reduction module and color conversion module)
9 Image data bus (between color conversion module and resizing module)
10 External (memory, etc.)

Claims (8)

A clock request signal output circuit for determining a period of valid data in each of a plurality of modules performing different image processing and outputting a clock request signal in a period necessary for processing valid data;
A clock control circuit comprising: a clock generator that receives the clock request signal and supplies a clock to a module that is an output source of the clock request signal during a period in which the clock request signal is active. The clock control circuit according to claim 1,
Each of the modules is a clock control circuit having different timing for processing image data. The clock control circuit according to claim 1,
Each of the modules is independently supplied with the clock from the clock generator. The clock control circuit according to claim 1,
Each of the modules transmits, as the clock request signal, a clock request signal of a module that processes data next to the clock generator. The clock control circuit according to claim 1,
The clock generator stops clock output before and after the clock request signal according to a setting from the CPU. The clock control circuit according to claim 1,
When receiving the vertical synchronization signal, the clock generator starts counting for the front side for vertical synchronization and counting for the rear side, and when the count for the rear side of vertical synchronization reaches a set value, the clock generator A clock control circuit that changes the clock request signal to inactive when the count for the pre-vertical synchronization side is set to a value that is changed to active. The clock control circuit according to claim 6,
A clock control circuit including valid data for the number of lines constituting one frame (one screen) of image data between the vertical synchronization signals. The clock control circuit according to claim 1,
When receiving the horizontal synchronization signal, the clock generator starts a count for the front side for horizontal synchronization and a count for the rear side, and when the count for the rear side of the horizontal synchronization reaches a set value, the clock generator A clock control circuit that changes the clock request signal to inactive when the horizontal synchronization pre-count reaches a set value;

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