TWI388863B - Test device, transmit circuit and control methods thereof - Google Patents

Description

Test device, transmission circuit, control method of test device, and control method of transmission circuit

The present invention relates to a test apparatus, a transmission circuit, a control method of the test apparatus, and a control method of the transmission circuit. More particularly, the present invention relates to a test device and a test device control method for testing a device to be tested, and a transfer circuit and a transfer circuit for transmitting data and a data enable signal indicating whether the data is valid from a transmitting circuit to a receiving circuit. Control method.

A test apparatus that tests a semiconductor or the like has a timing generator that generates a timing signal that specifies a change point of a test signal given to a device under test (for example, refer to Patent Document 1). The timing generator gives test cycle data indicating a delay time from the timing of the reference clock to the start timing of the test cycle, and timing data indicating the delay time from the start timing of the test cycle to the change point. Moreover, the timing generator uses a delay circuit to delay the reference clock by the delay time shown in the test period data and the timing data, thereby generating a timing signal.

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-361343. However, the test apparatus propagates the test period data generated by the period generator by a plurality of flip-flops connected in series, and gives it to the latter stage. Timing generator. However, in recent years, with the high performance of the device under test and the multi-pin, the number of bits of the test cycle data is increasing. Moreover, the number of segments of the flip-flop that propagates the test period data from the period generator to the timing generator is also increasing.

Moreover, the test device sometimes generates multiple timing signals over a range of test cycles. In this case, the timing generator can generate a plurality of timing signals within a range of one test period by alternately selecting and operating a plurality of delay circuits connected in parallel each time the test period data is given.

However, in recent years, with the high performance of the components to be tested, the number of timing signals that the test apparatus should generate in one test cycle range is increased, so that the number of delay circuits to be connected in parallel is increasing. The above aspects are the cause of the increase in power consumption of the test device.

In order to solve the above problems, in a first aspect of the present invention, a test apparatus for testing a device under test and a control method of the test device are provided, the test device comprising: a test period generator for generating a test in synchronization with a reference clock a period signal and a test period data, wherein the test period signal indicates a timing that becomes a reference for a start timing of the test period, the test period data indicates a delay amount from the test period signal to a start timing of the test period; and a timing generator, Generating a timing of receiving and receiving a signal between the test element and the test element specified by the test cycle data, and the test cycle generator includes: a cycle generation unit that generates the test cycle data and the foregoing a test period signal; the data acquisition unit acquires the test period data in synchronization with the reference clock, and outputs the data to the timing generator; and a clock gate unit, in a case where the period of the test period signal is not generated Stop the above information Measuring section for supplying the reference clock.

In a second aspect of the present invention, there is provided a transmission circuit and a control method of the transmission circuit, the transmission circuit transmitting data and a data enabling signal indicating whether the data is valid from a transmitting circuit to a receiving circuit, the transmitting circuit comprising: The data acquisition unit acquires the data from the transmission circuit in synchronization with the reference clock and outputs the data to the reception circuit, and the clock valve unit receives the data enable signal indicating that the data is invalid from the transmission circuit. At this time, the supply of the reference clock to the data acquisition unit is stopped.

In a third aspect of the present invention, a test apparatus for testing a device under test and a control method of the test device are provided, the test device comprising: a timing data generation unit that generates timing data and a timing enable signal, wherein the timing is The data pair specifies a timing of generating a timing signal at a timing of receiving and receiving a signal with the device under test, wherein the timing enable signal indicates whether the timing data is valid; and the counting unit operates in synchronization with the reference clock, from the timing data After receiving the valid timing data, the generating unit outputs the timing after counting the reference clock corresponding to the number of upper side data indicating the time in the unit of the period of the reference clock, which is included in the time series data. The lower side data other than the upper side data of the data and the timing enable signal indicating that the time series data is valid; and the clock valve part, the number of the upper side data included in the time series data that is not valid in the counting unit When the counting is performed, the supply of the base to the counting unit is stopped. Clock.

Furthermore, the summary of the above invention does not recite all the essential features of the present invention, and subcombination of these feature groups may also be an invention.

The above described features and advantages of the present invention will be more apparent from the following description.

Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments do not limit the invention of the claims. Moreover, all combinations of the features described in the embodiments are not necessarily limited to the details of the invention.

Fig. 1 also shows the configuration of the test apparatus 10 of the present embodiment and the device under test 200. The test apparatus 10 gives a test signal to the device under test 200, and compares the response signal output from the device under test 200 with an expected value based on the test signal, thereby testing the device under test 200. The test apparatus 10 includes a pattern generation unit 20, a test period generator 22, a timing generator 24, a waveform shaping unit 26, a driver 28, a level comparator 30, a timing comparator 32, and a determination unit. 34.

The pattern generating portion 20 generates a test pattern for designating a waveform of a test signal given to the device under test 200 and an expected value pattern for designating a logical value corresponding to a response signal to be output from the device under test 200 corresponding to the giving of the test signal. Further, the pattern generation unit 20 generates data specifying the test period, which is a reference for specifying the timing of the waveform change (edge) of the test signal and the comparison timing of the response signal and the expected value. Moreover, the pattern generating portion 20 generates a delay data indicating a delay time from the start timing of the test period to the timing of the waveform change of the test signal, or the self-test period, in each test cycle. The delay time from the start timing to the comparison timing of the response signal and the expected value.

The test cycle generator 22 generates a test cycle signal which is a reference for the start timing of the test cycle and a test cycle data indicating the delay amount from the test cycle signal to the start timing of the test cycle in synchronization with the reference clock. As an example, the test period generator 22 may receive the data specifying the test period from the pattern generation unit 20, and generate test period data based on the received data. And, the test period generator 22 generates the generated test period data and the test period signal in synchronization with the reference clock.

The timing generator 24 generates a timing at which a signal is received and received between the device under test 200, using the start timing of the test period specified by the test period data as a reference. Here, the period of the reference clock that generates the test period signal is referred to as: "the test period signal indicates a valid period", and the period of the reference clock that does not generate the test period signal is referred to as: "the reference period signal indicates an invalid period. 』. Further, in the present embodiment, in the case of the case of the effective test period data, the test period data acquired in the timing at which the test period signal indicates effective is indicated; in the case of the data called the invalid test period data, it is indicated in the case The test period signal indicates the test period data acquired in the invalid timing. That is, in the present embodiment, the test period signal functions as a signal indicating whether the test period data is valid or invalid. As an example, the timing generator 24 may generate a pulse as a pulse from a timing specified by the valid test period data and delayed by a delay time specified by the delay data corresponding to the test period. Timing signal.

The waveform shaping unit 26 generates a test signal for shaping the test pattern by using the timing signal given from the timing generator 24 as a reference. That is, the waveform shaping unit 26 generates a test signal having a waveform which is a waveform designated by the test pattern and which is a waveform whose level changes in the timing of the timing signal.

The driver 28 supplies the test signal generated by the waveform shaping portion 26 to the device under test 200. The level comparator 30 receives the response signal output from the device under test 200 corresponding to the test signal, and outputs a logic value signal indicating a logical value corresponding to the level of the received response signal.

The timing comparator 32 takes in the logic value represented by the logic value signal output from the level comparator 30 at the timing of the timing signal given from the timing generator 24. The determination unit 34 compares the logical value taken in by the timing comparator 32 with the expected value specified by the expected value pattern generated by the pattern generation unit 20, and outputs the comparison result. As an example, the determination unit 34 may output a comparison result indicating a pass when the logical value taken in by the timing comparator 32 matches the expected value; and the logical value taken in the timing comparator 32 and When the expected values do not match, a comparison result indicating a failure is output.

FIG. 2 shows an example of the bit structure of the test period data outputted by the test period generator 22. The test period data indicates the timing at which the test period data is given to the timing generator 24 in synchronization with the reference clock of the test apparatus 10, that is, the timing from the timing generator 24 receiving the test period data to the data of the test period. The delay time from the start timing of the specified test cycle.

The test cycle data includes multiple bits. For example, in the example of FIG. 2, the test period data contains (J+K) bits (J, K are natural numbers).

As an example, a bit of the reference position of the test period data (for example, a bit at the n position in FIG. 2) indicates a delay time corresponding to one cycle (T time) of the reference clock. Moreover, the test period data is forwarded by one bit from the bit position of the reference position, and each bit represents 2 times, 4 times, 8 times of a period of the reference clock. . . 2 ^K times (K is a natural number) delay time. Moreover, the test period data is forwarded by one bit from the bit position of the reference position to the next bit, and each bit represents 1/2 times, 1/4 times, 1/8 times of a period of the reference clock. . . , 2 - ^J times (J is a natural number) delay time.

Hereinafter, in the present embodiment, a portion of the test period data indicating a delay time equal to or less than one cycle (T) of the reference clock is referred to as "lower bit of the test period data". Further, in the present embodiment, the portion of the test period data indicating the delay time of two cycles (2 × T) equal to or larger than the reference clock is referred to as "the upper bit of the test period data". That is, in the present embodiment, the test period data includes: an upper bit and a lower bit, wherein the upper bit indicates a delay time from the timing at which the timing generator 24 receives the test period data to the start timing of the test period. The time is greater than the unit of the period of the reference clock, and the lower bit represents the time less than or equal to the unit of the period of the reference clock.

(A) to (C) of FIG. 3 indicate the reference clock, the test period data output by the test period generator 22, and the test period signal. The test period generator 22 outputs the test period data and the test period signal as a pair in synchronization with the reference clock. Further, the test period generator 22 sequentially outputs the test period data and the valid test period signal in each test cycle. In this case, the test period generator 22 does not simultaneously output two test period data in one cycle of the reference clock.

Therefore, when a test cycle is less than two cycles of the reference clock (2×T), that is, from the start timing of the test cycle specified by a certain test cycle data to the data of the next test cycle When the interval between the start timings of the designated test cycles is less than two cycles, the test cycle generator 22 continuously outputs the two test cycle data at the interval of the reference clock cycle (T). That is, when the upper bit of the test period data is 0, the test period data and the next test period data are continuously output at intervals of the period of the reference clock.

Fig. 4 shows the configuration of the test cycle generator 22 of the present embodiment. The test cycle generator 22 has a cycle generation unit 38 and a transmission circuit 40.

The period generation unit 38 receives the data specifying the test period from the pattern generation unit 20, and generates the test period data and the test period signal in synchronization with the reference clock in accordance with the received data. The transmission circuit 40 acquires the test period data and the test period signal from the period generation unit 38 in synchronization with the reference clock, and transmits it to the timing generator 24.

Fig. 5 shows the configuration of the transmission circuit 40 of this embodiment. The transmission circuit 40 includes a lower bit acquiring flip-flop 42 , an upper bit acquiring flip-flop 44 , a test period signal acquiring flip-flop 46 , a data acquiring unit 48 , a detecting unit 50 , and a clock enable signal ( The clock enable signal 52, the first clock valve unit 54, the data switching unit 56, and the test period signal transmission circuit 58.

The lower bit acquiring flip-flop 42 acquires the lower bit of the test period data generated by the period generating portion 38 at the timing of the reference clock. The upper bit acquiring flip-flop 44 acquires the upper bit of the test period data generated by the period generating unit 38 at the timing of the reference clock. The test period signal acquisition flip-flop 46 acquires the test period signal generated by the period generation unit 38 at the timing of the reference clock.

The data acquisition unit 48 acquires the test period data in synchronization with the reference clock and outputs it to the timing generator 24. As an example, the data acquisition unit 48 may include a lower bit transfer circuit 60 and an upper bit transfer circuit 62. The lower bit transfer circuit 60 acquires the lower bit of the test period data in synchronization with the reference clock and outputs it to the timing generator 24. The lower bit transfer circuit 60 acquires the upper bit of the test period data in synchronization with the reference clock and outputs it to the timing generator 24.

The detecting unit 50 detects whether or not the upper bit of the test period data generated by the period generating unit 38 matches the predetermined value. In the present embodiment, 0 is set as a predetermined value of the upper bit. In other words, in the present embodiment, the detecting unit 50 detects whether or not the upper bit of the test period data generated by the period generating unit 38 is 0. Thereby, the detecting unit 50 can detect that the test period data and the next test period data are continuously outputted in the cycle of the reference clock. Further, the detecting unit 50 detects whether or not the cycle generating unit 38 generates a test cycle signal indicating that the test cycle data is invalid, that is, whether or not a cycle in which the test cycle signal is not generated is detected.

Further, the detecting unit 50 generates a clock enable signal indicating whether or not the reference clock for acquiring the upper bit is supplied to the data acquiring unit 48. More specifically, when the period generating unit 38 generates a test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or the test period data generated by the period generating unit 38, When the upper bit matches the predetermined value (0 in the present embodiment), the detecting unit 50 generates a clock enable signal indicating that the bit is invalid. Further, the period generating portion 38 generates a test period signal indicating that the test period data is valid (that is, when the period of the test period signal is generated) and the upper bit of the test period data generated by the period generating portion 38 and the predetermined value (at In the case where 0) does not coincide in the present embodiment, the detecting unit 50 generates a clock enable signal indicating that it is valid.

The clock enable signal transmission circuit 52 acquires and propagates the clock enable signal output from the detecting unit 50 in synchronization with the reference clock. As an example, the clock enable signal transmission circuit 52 can synchronize the clock enable signal output from the detecting unit 50 with the test period data propagated by the data acquisition unit 48 by the continuous connection of a plurality of segments. Counter to spread.

The first clock valve unit 54 receives the reference clock and supplies the received reference clock to the data acquisition unit 48 as a reference clock for acquiring the upper bit of the test period data. As an example, the first clock valve unit 54 supplies the received reference clock to the upper bit transfer circuit 62. Here, when the period generating unit 38 generates a test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or when the upper bit of the test period data is detected, When the predetermined value (0 in the present embodiment) coincides, the first clock valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the reference clock of the upper bit of the test period data. When the data acquisition unit 48 sequentially propagates the upper bits of the test period data by the plurality of flip-flops connected in series, the first clock valve unit 54 can be stopped in the plurality of flip-flops as an example. The forward and reverse of the test cycle data is supplied to the reference clock. More specifically, as an example, when the clock enable signal acquired by a certain flip-flop is synchronously propagated by the clock enable signal transmission circuit 52, when the supply of the reference clock is stopped, the first The one-time valve portion 54 can stop supplying the reference clock to the next-stage flip-flop in the upper bit transfer circuit 62.

In addition to the above, as an example, when the cycle generation unit 38 generates a test cycle signal indicating that the test cycle data is invalid (that is, when the cycle of the test cycle signal is not generated) The first clock valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the upper bit of the test period data and the reference clock of the bit other than the upper bit. As an example, when the cycle generation unit 38 generates a test cycle signal indicating that the test cycle data is invalid, the first clock valve unit 54 stops all the bits for acquiring the test cycle data. Baseline clock.

When the upper bit of the test period data is detected to coincide with the predetermined value (0 in the present embodiment), the data switching unit 56 replaces the predetermined value with the upper bit of the test period data output from the data acquisition unit 48. And supplied to the timing generator 24. In the present embodiment, when it is detected that the upper bit of the test period data is 0, the data switching unit 56 substitutes 0 for the upper bit from the data acquisition unit 48 and supplies it to the timing generator 24.

The test period signal transmission circuit 58 acquires and propagates the test period signal output from the period generation unit 38 in synchronization with the reference clock. As an example, the test period signal transmission circuit 58 can propagate the clock enable signal output from the period generating unit 38 by the continuously connected multi-segment flip-flops in synchronization with the test period data propagated by the data acquisition unit 48.

6 and 7 show an example of a specific circuit configuration of the transmission circuit 40. FIG. 6 shows an example of the configuration of the material acquisition unit 48 and the data switching unit 56. FIG. 7 shows an example of the configuration of the detecting unit 50, the clock enable signal transmitting circuit 52, the first clock valve unit 54, and the test period signal transmission circuit 58.

As an example, the lower bit transfer circuit 60 may include, for example, n flip-flops 64-1 to 64 which are continuously connected to the reference clock as shown in FIG. 6 (n is an integer equal to or greater than 2). n. The lower bit transfer circuit 60 thus acquires the lower bit of the test period data by the front-end flip-flop 64-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 64, and finally The segment flip-flop 64-n is output to the timing generator 24.

As an example, the upper bit transfer circuit 62 may include the same number (ie, n) of consecutively connected flip-flops 66 as shown in FIG. 6 and the flip-flops 64 included in the lower bit transfer circuit 60. 1~66-n. Thus, the upper bit transfer circuit 62 acquires the upper bit of the test period data by the front-end flip-flop 66-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 66, and finally The segment flip-flop 66-n is output to the timing generator 24. Further, each of the n flip-flops 66 included in the lower bit transfer circuit 60 operates in synchronization with the reference clock supplied via the first clock valve unit 54 described below.

As an example, the detecting unit 50 may include a detecting unit internal OR circuit 72 and a detecting unit internal AND circuit 74 as shown in FIG. 7 . The detection unit internal OR circuit 72 receives each of the upper bits of the test period data, and outputs a result obtained by OR-calculating the value of each bit. In such a detection unit internal OR circuit 72, when the test bit data upper bit is 0, it indicates that it is invalid, and when it is other than 0, it indicates a valid signal.

The detection unit internal circuit 74 outputs a result of performing an AND calculation on the output signal of the OR circuit 72 in the detection unit and the test cycle signal generated by the cycle generation unit 38. Then, the detection unit 50 outputs the output signal of the AND circuit 74 in the detection unit as a clock enable signal. Thereby, when the period generating unit 38 generates the test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or the upper level of the test period data generated by the period generating unit 38. When the element is 0, the detecting unit 50 can generate a clock enable signal indicating that it is invalid. Further, when the period generating unit 38 generates a test period signal indicating that the test period data is valid, and the upper bit of the test period data generated by the period generating unit 38 is other than 0, the detecting unit 50 can generate a clock indicating that it is valid. Can signal.

As an example, the clock enable signal transmitting circuit 52 may include the same number (ie, n) of consecutively connected flip-flops 76 as the flip-flop 66 included in the upper bit transfer circuit 62 as shown in FIG. -1~76-n. The clock enable signal transmitting circuit 52 acquires the clock enable signal output from the detecting unit 50 by the front-end flip-flop 76-1 in synchronization with the reference clock, and sequentially returns to the rear-stage flip-flop 76. propagation.

As an example, the first clock valve portion 54 may include the same number (ie, n) of gate circuits 78 as the flip-flops 66 included in the upper bit transfer circuit 62, as shown in FIG. -1~78-n. Each of the n gate circuits 78-1 to 78-n corresponds to each of the n flip-flops 66-1 to 66-n included in the upper bit transfer circuit 62. Each of the n gate circuits 78-1 to 78-n receives the reference clock and supplies it to the corresponding flip-flop 66 included in the upper bit transfer circuit 62.

Further, each of the n gate circuits 78-1 to 78-n receives a clock enable signal input to the corresponding flip-flop 76 in the clock enable signal transmission circuit 52. And, if the received clock enable signal is valid, the corresponding flip-flops 66 included in the respective upper bit transfer circuits 62 of the n gate circuits 78-1 to 78-n are supplied with the reference clock; If the received clock enable signal is invalid, the corresponding flip-flop 66 included in the upper bit transfer circuit 62 is stopped from supplying the reference clock. Thereby, when the upper bit transfer circuit 62 sequentially propagates the upper bit of the test period data by the n flip-flops 66-1 to 66-n connected in series, the first clock valve portion 54 can The reference clock is supplied to the flip-flop 66 that propagates the test period data among the plurality of flip-flops 66-1 to 66-n.

As an example, the data switching unit 56 may include one or more data switching unit internal AND circuits 68 corresponding to the values of the respective bits of the test period data as shown in FIG. 6. The output of the AND circuit 68 in the one or more data switching sections is the value of the corresponding bit of the test period data output by the upper bit transfer circuit 62 and the flip-flop 76 of the final segment of the clock enable signal transfer circuit 52- The clock-energy signal output by n is a signal obtained by AND calculation.

Then, the data switching unit 56 outputs the output signal of the AND circuit 68 in the data switching unit as the upper bit of the test period data to the timing generator 24. Thereby, when the test period data output by the upper bit transfer circuit 62 is valid and the upper bit of the test cycle data is not detected to be 0 (that is, when the clock enable signal is valid), the data switching unit The value output from the upper bit transfer circuit 62 can be directly used as the upper bit of the test period data, and output to the timing generator 24.

Moreover, when the test period data output by the upper bit transfer circuit 62 is invalid, or when the upper bit of the test cycle data is 0 (that is, when the clock enable signal is invalid), The data switching unit 56 can output 0 to the timing generator 24 as the upper bit of the test period data. Thereby, when the test period data output from the upper bit transfer circuit 62 is invalid, the material switching unit 56 can prohibit the output of the useless data to the timing generator 24. Further, when it is detected that the upper bit of the test period data is 0, the data switching unit 56 can output the correct material to the timing generator 24.

As an example, the test period signal transmission circuit 58 may include the same number (ie, n) of consecutively connected flip-flops 80-1 as the flip-flop 66 included in the upper bit transfer circuit 62 as shown in FIG. ~80-n. The test period signal transmission circuit 58 acquires the test period signal output from the period generation unit 38 by the front-end flip-flop 80-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 80, and The flip-flop 80-n from the final stage is output to the timing generator 24.

(A) to (N) of FIG. 8 show an example of a timing chart of each signal in the transmission circuit 40. Furthermore, this example shows a timing chart in the case where the test period data of the 8-bit output from the period generating unit 38 and the test period signal are transmitted to the timing generator 24 by the three-segment flip-flop connected in series. An example. Moreover, the test period data of this example includes a 4-bit upper bit and a 4-bit lower bit.

(A) of Fig. 8 shows the reference clock. The RATE_IN of (B) of Fig. 8 indicates the test period signal generated by the period generating portion 38. The RATEDT[7:0]_IN of (C) of Fig. 8 indicates the test period data generated by the period generating unit 38.

Gckl_1 of (D) of FIG. 8 indicates the reference clock of the first-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_1[3:0] of Fig. 8(E) indicates the value of the lower bit of the test period data acquired by the first-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_1[7:4] of Fig. 8(F) indicates the value of the lower bit of the test period data acquired by the first-stage flip-flop 66 of the upper bit transfer circuit 62.

Gckl_2 of (G) of FIG. 8 indicates the reference clock of the second-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_2[3:0] of (H) of FIG. 8 indicates the value of the lower bit of the test period data acquired by the second-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_2[7:4] of (I) of Fig. 8 indicates the value of the lower bit of the test period data acquired by the second-stage flip-flop 66 of the upper bit transfer circuit 62.

Gckl_3 of (J) of FIG. 8 indicates the reference clock of the third-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_3[3:0] of (K) of FIG. 8 indicates the value of the lower bit of the test period data acquired by the third-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_3[7:4] of (L) of Fig. 8 indicates the value of the lower bit of the test period data acquired by the third-stage flip-flop 66 of the upper bit transfer circuit 62.

The RATE_OUT of (M) of FIG. 8 indicates the test period signal output from the transmission circuit 40 to the timing generator 24. The RATEDT[7:0]_OUT of (N) of FIG. 8 indicates the test period data output from the transfer circuit 40 to the timing generator 24.

As shown in (C) of FIG. 8, the cycle generation unit 38 sequentially generates test cycle data (RATE1) having a value of "0x0C", test cycle data (RATE2) having a value of "0x23", and a test having a value of "0x37". Cycle data (RATE3), test cycle data (RATE4) with a value of "0x05", and test cycle data (RATE5) with a value of "0xF1".

Here, the test period data (RATE2) whose value is "0x23", the test period data (RATE3) whose value is "0x37", and the upper level of the test period data (RATE5) whose value is "0xF1" are not 0. In this case, the first clock valve unit 54 sets each reference clock corresponding to the test period data (RATE1, RATE3, RATE5) as shown in (D), (G), and (J) of FIG. It is supplied to the upper bit transfer circuit 62.

In contrast, the test period data (RATE1) having a value of "0x0C" and the upper bit of the test period data (RATE4) having a value of "0x05" are 0. Therefore, other test period data (RATE2, RATE5) are generated in the cycle of the next reference clock of the test period data. In this case, the first clock valve portion 54 stops the supply of the upper bit transfer circuit 62 and the test period data (RATE1, RATE4) as shown in (D), (G), and (J) of FIG. Corresponding reference clocks. Thereby, when the upper bit of the test period data is 0, the first clock valve portion 54 can reduce the power consumed in the upper bit transfer circuit 62.

As shown in (L) and (M) of FIG. 8, the test period data (RATE1) having a value of "0x0C" and the test period data (RATE4) having a value of "0x05" are output to the timing generator 24. At this time, the data switching unit 56 outputs the value of the upper bit by replacing it with "0". Thereby, when the supply of the reference clock to the upper bit transfer circuit 62 is stopped and the upper bit transfer circuit 62 does not transmit the correct value, the data switching unit 56 can replace the test cycle with the correct value in the final stage. The data is output to the timing generator 24.

Further, as shown in (B) of FIG. 8, the test period signal from the test period data (RATE2) having a value of "0x23" to the test period data (RATE3) having a value of "0x37" is invalid. Moreover, the test period signal from the test period data (RATE3) having a value of "0x37" to the test period data (RATE4) having a value of "0x05" is also invalid. In this case, as shown in (D), (G), and (J) of FIG. 8, the first clock valve unit 54 stops the supply of the upper bit transfer circuit 62 during the period in which the test period signal indicates invalid. Baseline clock. Thereby, the first clock valve portion 54 can reduce the power consumed in the upper bit transfer circuit 62 when the test period data indicates that it is invalid.

As described above, when the self-cycle generating unit 38 generates a test cycle signal indicating that the output test cycle data is invalid, or when detecting that the value of the upper bit of the test cycle data matches the predetermined value, the present embodiment The transmission circuit 40 of the form stops supplying the reference clock to the data acquisition unit 48 for acquiring and transmitting the upper bit of the test period data. Further, when it is detected that the value of the upper bit of the test period data coincides with the predetermined value, the transfer circuit 40 outputs the predetermined value instead of the value of the upper bit of the test period data output from the data acquisition unit 48 to the timing. Generator 24.

Thereby, according to the transfer circuit 40, the effective test period data can be propagated from the period generating portion 38 to the timing generator 24, and the reference clock for propagating the invalid test period data can be stopped, thereby reducing power consumption. Further, according to the transmission circuit 40, when the upper bit of the valid test period data is a predetermined value, the reference clock for spreading the upper bit of the valid test period data can be stopped, thereby reducing power consumption.

In particular, when the upper bit of the test period data is 0, the effective test period data continuously propagates at the interval of the reference clock, and thus the power consumption becomes large. Therefore, when the upper bit of the test period data is 0, the power consumption can be efficiently reduced by stopping the reference clock of the upper bit for spreading the effective test period data.

Furthermore, in such a transfer circuit 40, the upper bit transfer circuit 62 of the material acquisition portion 48 may be a higher bit unit replacing the test period data (i.e., a bit portion representing a time greater than the unit of the period of the reference clock) And constructing at least one bit (hereinafter referred to as a target bit) predetermined in the test period data to the timing generator 24. In this case, the lower bit transfer circuit 60 propagates the bit other than the target bit in the test cycle data to the timing generator 24.

Further, in this case, the detecting unit 50 detects whether or not the target bit coincides with a predetermined value. Further, in this case, when the period generating portion 38 generates a test period signal indicating that the test period data is invalid, or when detecting that the target bit in the test period data coincides with the predetermined value, the first time The pulse valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the reference clock of the target bit. Further, in this case, when it is detected that the target bit in the test period data coincides with the predetermined value, the material switching unit 56 replaces the target bit from the material acquisition unit 48 with the predetermined value to the timing generator 24. supply. Even with the above configuration, the transmission circuit 40 can stop the reference clock of the target bit for propagating the valid test period data, thereby reducing power consumption.

Further, such a transmission circuit 40 can be included in other devices than the test device 10. That is, the transmitting circuit 40 can transmit the data and the data enabling signal indicating whether the data is valid from the transmitting circuit to the receiving circuit.

In this case, the transmission circuit 40 receives the test period data and the test period signal instead of the self-cycle generation unit 38, and receives the data and the data enable signal from the transmission circuit. Further, the transfer circuit 40 outputs the test period data and the test period signal to the timing generator 24, and outputs the data and the data enable signal to the receiving circuit. Thereby, according to the transmission circuit 40, even when the data and the data enable signal are transmitted from the transmission circuit to the reception circuit, the power consumption can be reduced.

Fig. 9 shows the configuration of the timing generator 24 of the present embodiment. The timing generator 24 includes a timing data generation unit 110, a distribution unit 112, a plurality of count delay units 114 (114-1 to 114-m), a first synthesis unit 116, a second synthesis unit 118, and a micro delay unit 120.

The timing data generating unit 110 generates timing data and a timing enable signal, wherein the timing data indicates a timing of generating a timing signal indicating a timing of receiving a signal with the device under test 200, and the timing energizing signal indicates timing data. is it effective. The timing data indicates the delay time from the timing at which the timing data is received to the timing at which the timing signal is generated, with an accuracy smaller than the period of the reference clock.

As an example, the time series data generating unit 110 may include an adding unit 132 that adds the test period data received from the test period generator 22 to the delay data given from the pattern generating unit 20. The time series data generation unit 110 can output the addition result of the addition unit 132 as time series data. Further, the timing data generating unit 110 can delay the test period signal received from the test period generator 22 by the time taken by the calculation processing of the test period data and the delay data, and output it as a timing enable signal.

The distribution unit 112 distributes the valid time series data and the timing enable signal sequentially output from the time series data generation unit 110 to one of the plurality of count delay units 114. Each time the timing data generating unit 110 outputs the valid time series data and the timing enable signal, the allocating unit 112 arbitrarily selects one of the plurality of counting delay units 114 and supplies the selected one of the counting delay units 114 to the selected one. Timing data and timing enable signals.

Each of the plurality of count delay sections 114 receives the timing data and the timing enable signal distributed by the distribution section 112. Each of the plurality of count delay units 114 separates the received time-series data into: a data portion indicating a delay time in units of a period greater than or equal to a reference clock, which is included in the time-series data, that is, an upper-side data, and the The data portion other than the upper side data contained in the time series data, that is, the lower side data. As an example, the upper side data may be data indicating a delay time from the timing of receiving the time series data to the generation timing of the timing signal in terms of the accuracy of the period unit of the reference clock. The lower side data may be data indicating a component of the period of the delay time that is less than the reference clock period.

Each of the plurality of count delay units 114 counts the reference clock from the upper side data included in a part of the time series data, starting from the timing at which the valid time series data is received. Further, each of the plurality of count delay units 114 starts counting the timing data, and counts the reference clock in accordance with the upper side data, and then outputs the timing enable signal. Further, each of the plurality of count delay units 114 outputs the lower side data included in the time series data in synchronization with the timing enable signal.

The first synthesizing unit 116 multiplexes the timing enable signals output from the respective count delay units 114 into one signal, and supplies them to the micro delay unit 120. As an example, the first synthesizing unit 116 synthesizes the timing enable signals output from the plurality of count delay units 114 into one signal by the OR calculation, and supplies them to the micro delay unit 120.

The second synthesizing unit 118 multiplexes the lower side data included in the time series data output from each of the plurality of count delay units 114 into one signal, and supplies the data to the micro delay unit 120. As an example, the second synthesizing unit 118 multiplexes the lower side data output from each of the plurality of count delay units 114 into one signal by the OR calculation, and supplies the data to the micro delay unit 120. In the case where the other allocation unit 112 outputs the valid lower side data, each of the plurality of count delay units 114 outputs 0 as the lower side data.

The micro-delay unit 120 delays the timing enable signal received from the first synthesizing unit 116 by the time corresponding to the lower-side data included in the time series data received from the second synthesizing unit 118. The micro delay unit 120 may be a variable delay device that delays the received signal by a time corresponding to the given set value. The micro delay unit 120 supplies the delayed timing enable signal to the waveform shaping unit 26 or the timing comparator 32 of the subsequent stage as a timing signal indicating the timing at which the signal is transmitted and received with the device under test 200.

According to the timing generator 24 having such a configuration, the timing enable signal can be delayed by the period precision of the reference clock by the plurality of count delay sections 114. Further, according to the timing generator 24, the micro-delay unit 120 can delay the timing enable signal delayed by each of the plurality of count delay units 114 and further reduce the accuracy of the period of the reference clock.

(A) to (E) of FIG. 10 show an example of a timing chart of the timing enable signal input to the plurality of count delay sections 114. (A) of Fig. 10 shows a reference clock. (B) of FIG. 10 shows the timing enable signal received by the distribution unit 112.

(C) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the first counting delay unit 114-1. (D) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the second counting delay unit 114-2. (E) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the third counting delay unit 114-3.

Each time the timing data generation unit 110 receives the timing enable signal, the distribution unit 112 sequentially selects the plurality of count delay units 114 one by one and allocates the received timing enable signal. For example, the distribution unit 112 assigns the timing enable signal received at time t21 to the first count delay unit 114-1 as shown in FIG. 10(C). Further, as shown in (D) of FIG. 10, the distribution unit 112 distributes the timing enable signal received at the next time t22 at time t21 to the second count delay unit 114-2. Further, as shown in FIG. 10(E), the distribution unit 112 assigns the timing enable signal received at the next time t23 at the time t22 to the third count delay unit 114-3.

(A) to (H) of FIG. 11 show an example of a timing chart of the timing enable signal and the lower side data output from the plurality of count delay units 114.

(A) of Fig. 11 shows a timing enable signal output from the first count delay unit 114-1. (B) of Fig. 11 shows the lower side data output from the first counting delay unit 114-1. (C) of Fig. 11 shows the timing enable signal output from the second count delay portion 114-2. (D) of Fig. 11 shows the lower side data output from the second counting delay unit 114-2. (E) of Fig. 11 shows the timing enable signal output from the third count delay portion 114-3. (F) of Fig. 11 shows the lower side data outputted from the third counting delay unit 114-3.

(E) of FIG. 11 shows the timing enable signal output from the first synthesizing section 116. (F) of Fig. 11 shows the lower side data output from the second synthesizing unit 118.

The first synthesizing unit 116 multiplexes the timing energizing signals respectively output from the respective plurality of counting delay units 114 into one signal, and supplies them to the micro delay unit 120. Similarly, the second synthesizing unit 118 multiplexes the lower side data included in the time series data output from each of the plurality of count delay units 114 into one signal, and supplies the data to the micro delay unit 120.

In this manner, the allocating unit 112 selects the plurality of counting delay units 114 one by one, and interleaves the delay processing of the period unit of the reference clock. Thereby, according to the timing generator 24, even if the timing signal specified in a certain test period exceeds the test period and is generated within the next test period, the result is that a plurality of timing signals are generated within the range of the next test period. At the same time, timing signals can be continuously generated without causing flaws in the action.

FIG. 12 shows the configuration of the count delay unit 114. Each of the plurality of count delay sections 114 has the same configuration. The counting delay unit 114 includes a counting unit 140, a state holding unit 142, and a second clock valve unit 144.

The counting unit 140 operates in synchronization with the reference clock given from the second clock valve unit 144. After receiving the valid time series data from the time series data generating unit 110, the counting unit 140 performs the reference clock on the upper side data indicating the time in units of the period equal to or longer than the reference clock, which is included in the time series data. After the counting, the lower side data other than the upper side data of the time series data and the timing enable signal indicating that the time series data is valid are output. As an example, when the state holding unit 142 holds a state signal indicating that the count value has reached a value after counting the number of data on the upper side, the counting unit 140 can output a timing enable indicating that the time series data is valid. signal.

As an example, the counting unit 140 may include a zero detecting unit 150, an inverting circuit 152, a counter 154, a first AND circuit 156, a first flip-flop 158, and a second AND circuit 160. The zero detecting unit 150 outputs a signal indicating that the counter 154 has a count value of 0, and outputs a signal indicating that the counter 154 has a count value of 0 or not. The inverting circuit 152 inverts the logic of the output signal of the zero detecting portion 150 and supplies it to the DEC terminal of the counter 154.

When the timing enable signal given from the allocating unit 112 indicates that it is valid, the counter 154 acquires the upper side data of the time series data output from the time series data generating unit 110 as the count value. Further, when the signal given to the DEC terminal indicates that it is valid (that is, when the count value of the counter 154 is other than 0), the counter 154 decreases the acquired count value one by one in synchronization with the given reference clock. .

The first AND circuit 156 outputs a timing enable signal indicating that the output signal of the zero detecting unit 150 is valid and the state signal output from the state holding unit 142 indicates that it is valid. When the timing enable signal given from the self-allocation unit 112 indicates that it is valid, the first flip-flop 158 acquires the lower-side data of the time series data output from the time series data generating unit 110. When the output signal of the zero detecting unit 150 indicates that the state signal output by the state holding unit 142 is valid, the second AND circuit 160 outputs the lower side data acquired by the first flip-flop 158.

The counting unit 140 having such a configuration can count the reference clock corresponding to the value shown in the upper side data included in the time series data after receiving the valid time series data, and output the lower side data after the counting and A timing enable signal indicating that the timing data is valid.

The state holding unit 142 holds a state signal indicating whether or not the counting unit 140 is in the count of the number of upper side data included in the valid time series data. As an example, the state holding unit 142 can output a state signal indicating that it is valid when the counting unit 140 is counting, and indicating that it is invalid when the counting unit 140 is not counting.

As an example, the state holding unit 142 may include a first OR circuit 162 and a second flip-flop 164. When the output signal of the zero detecting unit 150 of the counting unit 140 indicates that it is valid (that is, when the count value of the counter 154 is 0), or when the timing energizing signal given by the self-allocation unit 112 indicates that it is valid. At the time, the first OR circuit 162 outputs a signal indicating that it is valid. The second flip-flop 164 operates in synchronization with the reference clock. When the output signal of the first OR circuit 162 indicates that it is valid, the second flip-flop 164 acquires the timing enable signal given from the distribution unit 112. When the self-allocation portion 112 gives a timing enable signal indicating that it is valid, the first OR circuit 162 thus starts to hold a value indicating that it is valid. Further, the first OR circuit 162 starts to hold a value indicating that it is invalid, corresponding to the count value of the counter 154 becoming zero. Subsequently, the first OR circuit 162 continues to hold the value indicating invalid until the next time it is given a valid timing enable signal.

When the counting unit 140 does not count the number of upper side data included in the valid time series data, the second clock valve unit 144 stops supplying the reference clock to the counting unit 140. More specifically, the second clock valve unit 144 starts to supply the reference clock to the counting unit 140 in response to receiving the timing enable signal indicating that the timing data is valid. Further, the second clock valve unit 144 stops the supply of the reference clock to the counting unit 140 in response to the fact that the count value of the counting unit 140 has reached the value obtained by counting the number of data on the upper side.

As an example, the second clock valve portion 144 may include a second OR circuit 166 and a gate circuit 168. When the output signal of the zero detecting unit 150 of the counting unit 140 indicates that it is invalid (that is, when the count value of the counter 154 is other than 0), or when the timing energizing signal given by the self-allocation unit 112 indicates that it is valid. At the time, the second OR circuit 166 outputs a clock enable signal indicating that it is valid.

Gate circuit 168 receives a clock enable signal from second OR circuit 166. Further, when the clock enable signal indicates that it is valid (that is, when the count value of the counter 154 is other than 0, or when the timing enable signal given from the distribution unit 112 indicates that it is valid), the gate circuit 168 supplies the reference clock to the counter 154 and the first flip-flop 158 in the counting unit 140. When the clock enable signal indicates that it is invalid, the gate circuit 168 stops supplying the reference clock to the counter 154 and the first flip-flop 158 in the counting unit 140.

In more detail, the second clock valve unit 144 starts to supply the reference clock to the counter 154 and the first flip-flop 158 in response to receiving the timing enable signal indicating that the timing data is valid. Further, the second clock valve portion 144 stops supplying the reference clock to the counter 154 and the first flip-flop 158 corresponding to the count value of the counter 154 having reached zero.

The counting delay unit 114 supplies the reference clock to the counting unit 140 while the counting unit 140 is operating normally, and stops the supply of the reference clock to the counting unit 140 while the counting unit 140 is not operating normally. Thereby, the counting delay unit 114 can reduce the current consumption of the counting unit 140.

(A) to (I) of FIG. 13 show an example of a timing chart of each signal in the count delay unit 114. (A) of Fig. 13 shows a reference clock. (B) of FIG. 13 shows the timing enable signal received by the count delay unit 114. (C) of FIG. 13 shows the timing enable signal received by the counting delay unit 114. (D) of Fig. 13 shows the count value of the counter 154.

(E) of FIG. 13 shows a state signal output from the second flip-flop 164. (F) of Fig. 13 shows the lower side data held by the first flip-flop 158. (G) of FIG. 13 shows the reference clocks given to the counter 154 and the first flip-flop 158. (H) of FIG. 13 shows the timing enable signal output from the counting delay unit 114. (I) of FIG. 13 shows the lower side data output by the counting delay unit 114.

As shown in FIG. 13(B), the count delay unit 114 receives a timing enable signal indicating that it is valid from the allocating unit 112 at time t41. When the self-allocation unit 112 receives the timing enable signal indicating that it is valid, the second flip-flop 164 maintains a value indicating that it is valid from the timing of the next reference clock as shown in FIG. 13(E).

Further, when the self-allocation unit 112 receives the timing enable signal indicating that it is valid, the gate circuit 168 starts the counter 154 at the timing of the next reference clock (time t42) as shown in (G) of FIG. The first flip-flop 158 supplies a reference clock (gclk). As a result, as shown in (D) of FIG. 13, the counter 154 takes in the upper side data (for example, 0x8) of the time series data in the timing at which the timing enable signal is received as the count value, and then decreases one by one (decrement). ) count value. Further, as shown in (F) of FIG. 13, the first flip-flop 158 takes in the lower side data (for example, 0xC) of the time series data in the timing at which the timing enable signal is received.

As shown in (H) of FIG. 13, the first AND circuit 156 outputs a timing enable signal when the count value of the counter 154 reaches 0 at time t43. Further, as shown in (I) of FIG. 13, the second AND circuit 160 outputs the lower side data held by the first flip-flop 158 in synchronization with the output timing enable signal of the first AND circuit 156.

Further, as shown in (G) of FIG. 13, when the count value of the counter 154 reaches 0, the gate circuit 168 stops supplying the counter 154 and the first flip-flop 158 at the timing of the next reference clock (time t44). Reference clock (gclk). Further, as shown in (E) of FIG. 13, when the count value of the counter 154 reaches 0, the second flip-flop 164 maintains a value indicating that it is invalid from the timing of the next reference clock.

In this manner, the counting delay unit 114 can supply the reference clock to the counting unit 140 while the counting unit 140 is operating normally, and stop supplying the reference clock to the counting unit 140 while the counting unit 140 is not operating normally. Thereby, the counting delay unit 114 can reduce the current consumption of the counting unit 140.

Further, the counting delay unit 114 may be included in other devices than the testing device 10 as a counting circuit. That is, the count delay unit 114 can function as a counter circuit that counts data given from the transmission circuit.

In this case, the count delay unit 114 receives the timing data and the timing enable signal instead of the timing data generation unit 110, and receives the data and the data enable signal from the transmission circuit. Further, the count delay unit 114 outputs a data enable signal instead of the output timing enable signal. Thereby, the count delay unit 114 can reduce the power consumption even when the number of pieces of data indicated by the data given from the transmission circuit is counted.

The invention has been described above using the embodiments, but the technical scope of the invention is not limited to the scope disclosed in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be added to the above embodiments. It is to be understood that the scope of the patent application is intended to be included in the technical scope of the invention.

It should be noted that the order of execution of the processes, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings is not specifically stated as the first. ", first", etc., and as long as the pre-processed output is not used in post-processing, it can be implemented in any order. The operation flow in the patent application scope, the specification, and the drawings, even if it is used for the sake of convenience, "first", "second", etc., does not mean that it must be implemented in this order.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Test device

20. . . Pattern generation department

twenty two. . . Test cycle generator

twenty four. . . Timing generator

26. . . Waveform forming department

28. . . driver

30. . . Level comparator

32. . . Timing comparator

34. . . Judgment department

38. . . Cycle generation department

40. . . Transmission circuit

42. . . Lower bit acquisition flip-flop

44. . . Upper bit acquisition flip-flop

46. . . Test cycle signal acquisition flip-flop

48. . . Data acquisition department

50. . . Detection department

52. . . Clock shaping signal transmission circuit

54. . . First clock valve

56. . . Data switching department

58. . . Test cycle signal transmission circuit

60. . . Lower bit transfer circuit

62. . . Upper bit transfer circuit

64, 64-1~64-n, 66, 66-1~66-n, 76, 76-1~76-n, 80, 80-1~80-n. . . Positive and negative

68. . . AND circuit in data switching unit

72. . . Detection unit internal OR circuit

74. . . In-circuit AND circuit

78, 78-1~78-n, 168. . . Gate circuit

110. . . Timing data generation department

112‧‧‧Distribution Department

114, 114-1~114-m‧‧‧ Counting delay

116‧‧‧First Synthesis Department

118‧‧‧Second Synthesis Department

120‧‧‧Micro Delay Department

132‧‧‧Additional Department

140‧‧‧Counting Department

142‧‧‧State Maintenance Department

144‧‧‧Second clock valve

150‧‧‧ Zero Detection Department

152‧‧‧Reversing circuit

154‧‧‧ counter

156‧‧‧First AND circuit

158‧‧‧First forward and reverse

160‧‧‧Second AND circuit

162‧‧‧First OR circuit

164‧‧‧second flip-flop

166‧‧‧Second OR circuit

200‧‧‧tested components

T21, t22, t23, t41, t42, t43, t44‧‧‧

Fig. 1 also shows the configuration of the test apparatus 10 of the present embodiment and the device under test 200.

FIG. 2 shows an example of the bit structure of the test period data outputted by the test period generator 22.

(A) to (C) of FIG. 3 indicate the reference clock, the test period data output by the test period generator 22, and the test period signal.

Fig. 4 shows the configuration of the test cycle generator 22 of the present embodiment.

Fig. 5 shows the configuration of the transmission circuit 40 of this embodiment.

FIG. 6 shows an example of the configuration of the material acquisition unit 48 and the data switching unit 56.

FIG. 7 shows an example of the configuration of the detecting unit 50, the clock enable signal transmitting circuit 52, the first clock valve unit 54, and the test period signal transmission circuit 58.

(A) to (N) of FIG. 8 show an example of a timing chart of each signal in the transmission circuit 40.

Fig. 9 shows the configuration of the timing generator 24 of the present embodiment.

(A) to (E) of FIG. 10 show an example of a timing chart of the timing enable signal input to the plurality of count delay sections 114.

(A) to (H) of FIG. 11 show an example of a timing chart of the timing enable signal and the lower side data output from the plurality of count delay units 114.

FIG. 12 shows the configuration of the count delay unit 114.

(A) to (I) of FIG. 13 show an example of a timing chart of each signal in the count delay unit 114.

10. . . Test device

20. . . Pattern generation department

twenty two. . . Test cycle generator

twenty four. . . Timing generator

26. . . Waveform forming department

28. . . driver

30. . . Level comparator

32. . . Timing comparator

34. . . Judgment department

200. . . Tested component

Claims (14)

A test device for testing a component under test, the test device comprising: a test cycle generator for generating a test cycle signal and a test cycle data in synchronization with a reference clock, wherein the test cycle signal is indicative of a start timing of the test cycle a timing of the reference, wherein the test period data indicates a delay amount from the test period signal to a start timing of the test period; and the timing generator generates a start timing of the test period specified by the test period data as a reference The timing of the signal is received between the tested components, and the test cycle generator includes: a cycle generating unit that generates the test cycle data and the test cycle signal; and a data acquisition unit that acquires the test cycle data in synchronization with the reference clock. And outputting to the timing generator; the detecting unit detects whether a predetermined number of upper bits in the test period data generated by the period generating unit is 0; and the clock valve unit does not generate the test period signal When, or in the above inspection When the detecting unit detects that the upper bit of the test period data is 0, the sampling unit stops supplying the reference clock to the data acquiring unit, so that the acquisition of the upper bit is prevented. The test device of claim 1, wherein the clock valve portion is in a period in which the test period signal is not generated. In a case, or when detecting that the at least one bit in the test period data matches the predetermined value, stopping the supply of the reference data acquisition unit for acquiring the reference clock of the at least one bit, the test period The generator further includes: a data switching unit that replaces the at least one bit from the data acquiring unit when detecting that the at least one bit in the test period data matches the predetermined value It is supplied to the above timing generator. The test apparatus of claim 2, wherein the period generating unit generates the test period data and the test period signal, wherein the test period data includes: the upper bit and a lower bit, wherein the upper bit The element indicates a time greater than a unit of a period of the reference clock in a time from the start timing of the test period, and the lower bit indicates a time equal to or less than a unit of a period of the reference clock, and the data switching unit detects When the upper bit of the test cycle data is 0, the upper bit from the data acquisition unit is replaced with 0 and supplied to the timing generator. The test apparatus according to claim 3, wherein the data acquisition unit includes: a lower bit transfer circuit that acquires the test cycle data by the frontmost flip-flop in synchronization with the reference clock a lower bit, and sequentially propagates to the rear of the flip-flop, and outputs from the flip-flop of the final segment to the timing generator; and The upper bit transfer circuit acquires the upper bit of the test period data by the front-end flip-flop in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop, and from the final segment The counter is output to the timing generator, and the test period generator includes: a clock enable signal transmitting circuit that acquires, by the front-end flip-flop, synchronously with the reference clock to indicate whether or not the supply is for acquiring the upper level a clock enable signal of the above reference clock of the bit, and sequentially propagates to the flip-flop of the subsequent stage; and a test period signal transmission circuit that acquires the above by the front-end flip-flop in synchronization with the reference clock Testing the periodic signal, and sequentially propagating to the rear-stage flip-flop, and outputting from the flip-flop of the final segment to the timing generator, and the clock valve portion is propagated by the clock-energy signal transmitting circuit When a certain period of the clock enable signal indicates that the supply of the reference clock is stopped, the supply of the reference clock to the next flip-flop in the upper bit transfer circuit is stopped. The test apparatus according to claim 4, wherein the data switching unit receives the clock enable signal indicating that the supply of the reference clock is stopped from the final stage of the clock enable signal transmission circuit. At this time, 0 is substituted for the upper bit of the test period data output from the final stage of the upper bit transfer circuit, and is output to the timing generator. A transmission circuit that records data and indicates whether the above data is valid The data enable signal is transmitted from the transmitting circuit to the receiving circuit, the data comprising: a predetermined number of upper bits, the upper bit indicating a time greater than a period of the period of the reference clock; and one or more lower bits The lower bit indicates a time unit that is less than or equal to a period of the period of the reference clock, and the transmission circuit further includes: a data acquisition unit that acquires the data from the transmission circuit in synchronization with the reference clock and to the receiving circuit And a detection unit that detects whether the predetermined number of the upper bits in the test period data generated by the detection period generating unit is 0; and the clock valve unit receives the data indicating that the data is invalid from the transmitting circuit In the case of the energy signal, or when the detection unit detects that the upper bit of the data is 0, the supply of the reference clock to the data acquisition unit is stopped, so that the acquisition of the upper bit is prevented. The transmission circuit of claim 6, further comprising: a detecting unit, detecting whether a predetermined at least one bit in the data matches a predetermined value, and the clock valve portion is received from the transmitting circuit When the data enabling signal is invalid, or when detecting that the at least one bit in the data matches the predetermined value, the supply of the data acquiring unit is stopped to acquire the at least one bit. The above reference clock of the element, the transmission circuit further includes: a data switching unit that detects the above-mentioned resources When the at least one bit in the material matches the predetermined value, the predetermined value is supplied to the receiving circuit instead of the at least one bit from the data acquiring unit. A test device for testing a component to be tested, the test device comprising: a timing data generating section, generating timing data and a timing enable signal, wherein the timing data pair indicates a timing of receiving and receiving a signal between the component to be tested The timing signal generation timing is specified, and the timing enable signal indicates whether the timing data is valid; the counting unit operates in synchronization with the reference clock, and after receiving the valid timing data from the timing data generation unit, and the timing data The counting unit displays the number of upper side data indicating the time in units of the period of the reference clock, and the counting unit outputs the lower side data other than the upper side data of the time series data, and The timing enable signal indicating that the time series data is valid; and the clock valve unit stops supplying the counting unit when the counting unit does not count the number of the upper side data included in the valid time series data. The above reference clock. The test apparatus according to claim 8, wherein the clock valve unit starts to supply the reference clock to the counting unit in response to receiving the timing enable signal indicating that the timing data is valid, and corresponds to The count value of the counting unit reaches a value obtained by counting the number of the upper side data, and the supply of the reference clock to the counting unit is stopped. The test apparatus according to claim 9, further comprising: a state holding unit that holds a state signal indicating whether the counting unit is in a count of the number of the upper side data included in the valid time series data, and the above When the state holding unit holds the state signal indicating that the count is reached, and the count value reaches a value obtained by counting the number of the upper side data, the counting unit outputs the timing enable signal indicating that the time series data is valid. The test apparatus according to claim 10, further comprising: a plurality of the counting unit, the clock valve unit, and the state holding unit; and a distribution unit that sequentially outputs the time series data generating unit The above-described timing data that is valid and the timing enable signal indicating that the timing data is valid are allocated to each of the plurality of groups. A control device for testing a test device, wherein the test device includes: a test cycle generator that generates a test cycle signal and a test cycle data in synchronization with a reference clock, wherein the test cycle signal a timing indicating a timing of starting the test cycle, the test cycle data indicating a delay amount from the test cycle signal to a start timing of the test cycle; and a timing generator for starting the test cycle specified by the test cycle data The timing is used as a reference and is generated in the same component as the above Interleaving the timing of the signal, and the test cycle generator includes: a period generating unit that generates the test period data and the test period signal; and a data acquisition unit that acquires the test period data in synchronization with the reference clock and to the timing a detector output, wherein the detecting unit detects whether a predetermined number of upper bits in the test period data generated by the period generating unit is 0; and when the test period signal is not generated, or in the detecting unit When the above-mentioned upper bit of the test cycle data is 0, the supply of the reference clock to the data acquisition unit is stopped, so that the acquisition of the bit is prevented. A control method for a transmission circuit, wherein the transmission circuit transmits data and a data enabling signal indicating whether the data is valid from a transmitting circuit to a receiving circuit, wherein the data includes: a predetermined number of upper bits, wherein the upper bit indicates greater than a time unit of a period of a period of the reference clock; and one or more lower bits indicating a time unit of a period less than or equal to a period of the reference clock, the transmission circuit including: a data acquisition unit, Acquiring the above-mentioned data from the transmitting circuit in synchronization with the reference clock and outputting to the receiving circuit; and detecting unit detecting whether the predetermined number of the upper bits is 0; When the data transmission signal indicating that the data is invalid is received from the transmission circuit, or when the detection unit detects that the upper bit of the data is 0, the supply of the data acquisition unit to the data acquisition unit is stopped. The reference clock is such that the acquisition of the above upper bits is prevented. A control device for testing a test device, wherein the test device includes: a timing data generating unit that generates timing data and a timing enable signal, wherein the timing data pair is represented by the tested component Specifying a timing of generating a timing signal between timings, wherein the timing enable signal indicates whether or not the timing data is valid; and the counting unit operates in synchronization with the reference clock to receive the valid timing data from the timing data generating unit After that, the counting unit outputs the upper side of the time series data after the reference clock is counted in accordance with the number of upper side data indicating the time in the unit of the period of the reference clock, which is included in the time series data. The lower side data other than the data, and the timing enable signal indicating that the time series data is valid, and when the counting unit does not count the number of the upper side data included in the valid time series data, the above is stopped. The counting unit supplies the reference clock.