JPWO2009147797A1 - Test apparatus, transmission circuit, test apparatus control method, and transmission circuit control method - Google Patents

Abstract

A test apparatus for testing a device under test, which indicates a test cycle signal indicating a reference timing of a test cycle start timing in synchronization with a reference clock, and a delay amount from the test cycle signal to the test cycle start timing A test cycle generator for generating test cycle data, and a timing generator for generating a timing for transmitting / receiving a signal to / from the device under test based on the start timing of the test cycle specified by the test cycle data The test cycle generator includes a cycle generator that generates test cycle data and a test cycle signal, a data acquisition unit that acquires test cycle data in synchronization with the reference clock, and outputs the test cycle data to the timing generator, and a test cycle Clock gate that stops the supply of the reference clock to the data acquisition unit in the cycle when no signal is generated If, to provide a test apparatus having a.

Description

The present invention relates to a test apparatus, a transmission circuit, a test apparatus control method, and a transmission circuit control method. In particular, the present invention relates to a test apparatus for testing a device under test, a control method for the test apparatus, a transmission circuit for transmitting data and a data enable signal indicating whether the data is valid from the transmission circuit to the reception circuit, and transmission The present invention relates to a circuit control method. This application is related to the following Japanese application and claims priority from the following Japanese application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
1. Japanese Patent Application No. 2008-144581 Application date June 2, 2008

  A test apparatus for testing a semiconductor or the like includes a timing generator that generates a timing signal that designates a change point of a test signal to be applied to a device under test (for example, see Patent Document 1). The timing generator is given test cycle data indicating a delay time from the timing of the reference clock to the start timing of the test cycle, and timing data indicating a delay time from the start timing of the test cycle to the change point. Then, the timing generator uses the delay circuit to generate a timing signal by delaying the reference clock by the delay time indicated in the test cycle data and the timing data.

JP 2004-361343 A

  By the way, the test apparatus propagates the test cycle data generated by the cycle generator through a plurality of continuously connected flip-flops, and gives it to the subsequent timing generator. However, in recent years, the number of bits of test cycle data has increased as the device under test has been improved in performance and increased in the number of pins. Also, the number of flip-flop stages that propagate test cycle data from the cycle generator to the timing generator is increasing.

  Further, the test apparatus may generate a plurality of timing signals within the range of one test cycle. In such a case, the timing generator selects and operates a plurality of delay circuits connected in parallel one by one every time the test cycle data is given, thereby operating a plurality of delay circuits within the range of one test cycle. This timing signal can be generated.

  However, in recent years, the number of timing signals to be generated within the range of one test cycle has increased with the increase in performance of devices under test, and the number of delay circuits to be connected in parallel has increased. It has increased. The above points have caused the power consumption of the test apparatus to increase.

  In order to solve the above problems, in the first aspect of the present invention, a test apparatus for testing a device under test, which is a test indicating a timing that is a reference of a start timing of a test cycle in synchronization with a reference clock A test cycle generator that generates a cycle signal and a test cycle data representing a delay amount from the test cycle signal to a test cycle start timing, and the test cycle start timing specified by the test cycle data as a reference. A timing generator for generating a timing for transmitting / receiving a signal to / from a test device, and the test cycle generator includes a cycle generator for generating the test cycle data and the test cycle signal, and a reference clock. Synchronously, the data acquisition unit for acquiring the test cycle data and outputting it to the timing generator, and the test cycle signal If the produced not even cycle, the test device having a clock gate unit stopping the supply of the reference clock to the data acquisition unit, and a control method of such a test device.

  According to a second aspect of the present invention, there is provided a transmission circuit for transmitting data and a data enable signal indicating whether or not the data is valid from a transmission circuit to a reception circuit, wherein the transmission is performed in synchronization with a reference clock. A data acquisition unit that acquires the data from the circuit and outputs the data to the reception circuit; and the reference clock for the data acquisition unit when the data enable signal indicating that the data is invalid is received from the transmission circuit. And a control method for such a transmission circuit.

  According to a third aspect of the present invention, there is provided a test apparatus for testing a device under test, wherein the timing data designates the generation timing of a timing signal indicating the timing of transmitting / receiving a signal to / from the device under test, and the timing A timing data generation unit that generates a timing enable signal indicating whether or not data is valid, and operates in synchronization with a reference clock, and is included in the timing data after receiving the valid timing data from the timing data generation unit The timing enable signal indicating the validity of the timing data and the lower side data other than the upper side data of the timing data after counting the reference clocks by the number of higher side data representing the time in units equal to or greater than the cycle of the reference clock And a counting unit that outputs And a clock gate unit that stops the supply of the reference clock to the count unit when the count unit does not count the number of higher-order data included in the valid timing data. Provided is a method for controlling a simple test apparatus.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

FIG. 1 shows a configuration of a test apparatus 10 according to this embodiment together with a device under test 200. FIG. 2 shows an example of the bit configuration of the test cycle data output from the test cycle generator 22. FIG. 3 shows a reference clock, test cycle data output from the test cycle generator 22, and a test cycle signal. FIG. 4 shows a configuration of the test cycle generator 22 according to the present embodiment. FIG. 5 shows a configuration of the transmission circuit 40 according to the present embodiment. FIG. 6 shows an example of the configuration of the data acquisition unit 48 and the data switching unit 56. FIG. 7 shows an exemplary configuration of the detection unit 50, the clock enable signal transmission circuit 52, the first clock gate unit 54, and the test cycle signal transmission circuit 58. FIG. 8 shows an example of a timing chart of each signal in the transmission circuit 40. FIG. 9 shows a configuration of the timing generator 24 according to the present embodiment. FIG. 10 shows an example of a timing chart of the timing enable signal input to the plurality of counter delay units 114. FIG. 11 shows an example of a timing chart of timing enable signals and lower-order data output from the plurality of counter delay units 114. FIG. 12 shows the configuration of the counter delay unit 114. FIG. 13 shows an example of a timing chart of each signal in the counter delay unit 114.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are invented. It is not always essential to the solution.

  FIG. 1 shows a configuration of a test apparatus 10 according to this embodiment together with a device under test 200. The test apparatus 10 tests the device under test 200 by applying a test signal to the device under test 200 and comparing the response signal output from the device under test 200 with an expected value in accordance with the test signal. The test apparatus 10 includes a pattern generator 20, a test cycle generator 22, a timing generator 24, a waveform shaping unit 26, a driver 28, a level comparator 30, a timing comparator 32, and a determination unit 34. .

  The pattern generator 20 designates a test pattern for designating the waveform of the test signal to be applied to the device under test 200 and a logical value of the response signal to be output from the device under test 200 in response to the provision of the test signal. Generate an expected value pattern. The pattern generator 20 also generates data specifying a test cycle that serves as a reference for specifying the timing of the waveform change (edge) of the test signal and the comparison timing between the response signal and the expected value. In addition, the pattern generation unit 20 delays from the start timing of the test cycle to the timing of waveform change of the test signal or the delay from the start timing of the test cycle to the comparison timing of the response signal and the expected value for each test cycle. Generate delay data representing time.

  The test cycle generator 22 generates test cycle data representing a test cycle start timing and a delay amount from the test cycle signal to the test cycle start timing in synchronization with the reference clock. As an example, the test cycle generator 22 may receive data designating a test cycle from the pattern generator 20 and generate test cycle data according to the received data. The test cycle generator 22 generates the generated test cycle data and test cycle signal in synchronization with the reference clock.

  The timing generator 24 generates a timing for transmitting / receiving a signal to / from the device under test 200 based on the start timing of the test cycle specified by the test cycle data. Here, the cycle of the reference clock in which the test cycle signal is generated is referred to as a cycle in which the test cycle signal is valid, and the cycle of the reference clock in which the test cycle signal is not generated is referred to as a cycle in which the reference cycle signal is invalid. . In the present embodiment, in the case of valid test cycle data, it indicates test cycle data acquired at a timing when the test cycle signal is valid, and in the case of invalid test cycle data, at a timing where the test cycle signal is valid. The acquired test cycle data is shown. That is, in the present embodiment, the test cycle signal functions as a signal indicating whether the test cycle data is valid or invalid. For example, the timing generator 24 generates a timing signal that is a pulse at a timing delayed by a delay time specified by delay data corresponding to the test cycle from a timing specified by valid test cycle data. Good.

  The waveform shaping unit 26 generates a test signal obtained by shaping a test pattern with reference to the timing signal supplied from the timing generator 24. That is, the waveform shaping unit 26 generates a test signal having a waveform designated by the test pattern and having a waveform whose level changes at the timing of the timing signal.

  The driver 28 supplies the test signal generated by the waveform shaping unit 26 to the device under test 200. The level comparator 30 receives the response signal output from the device under test 200 according to the test signal, and outputs a logic value signal representing a logic value according to the level of the received response signal.

  The timing comparator 32 takes in the logical value represented by the logical value signal output from the level comparator 30 at the timing of the timing signal provided from the timing generator 24. The determination unit 34 compares the logical value captured by the timing comparator 32 with the expected value specified by the expected value pattern generated by the pattern generation unit 20 and outputs a comparison result. For example, when the logical value captured by the timing comparator 32 matches the expected value, the determination unit 34 outputs a comparison result representing a path, and the logical value captured by the timing comparator 32 matches the expected value. If not, a comparison result indicating failure may be output.

  FIG. 2 shows an example of the bit configuration of the test cycle data output from the test cycle generator 22. The test cycle data includes the test cycle data from the timing at which the test cycle data is synchronized with the reference clock of the test apparatus 10 given to the timing generator 24, that is, the timing at which the timing generator 24 receives the test cycle data. Represents the delay time until the start timing of the test cycle specified by.

  The test cycle data includes a plurality of bits. For example, in the example of FIG. 2, the test cycle data includes (J + K) bits (J and K are natural numbers).

As an example, the test cycle data represents a delay time corresponding to one cycle (T time) of the reference clock when the bit at the reference position (for example, the bit at the position n in FIG. 2). Each time the test cycle data advances from the bit at the reference position to one higher bit, each bit is delayed by 2 times, 4 times, 8 times, ... 2 ^K times (K is a natural number) of one cycle of the reference clock. Represents time. In addition, every time the test cycle data advances from the bit at the reference position to the lower one bit, each bit is 1/2, 1/4, 1/8,..., 2- ^J of one cycle of the reference clock. The delay time is doubled (J is a natural number).

  Hereinafter, in the present embodiment, a portion representing a delay time of one cycle (T) or less of the reference clock in the test cycle data is referred to as a lower bit of the test cycle data. In the present embodiment, a portion representing a delay time of two cycles (2 × T) or more of the reference clock in the test cycle data is referred to as an upper bit of the test cycle data. In other words, in the present embodiment, the test cycle data includes upper bits indicating a unit time larger than the cycle of the reference clock in the delay time from the timing when the timing generator 24 receives the test cycle data to the start timing of the test cycle. It includes lower bits that indicate time in units that are less than the period of the reference clock.

  FIG. 3 shows a reference clock, test cycle data output from the test cycle generator 22, and a test cycle signal. The test cycle generator 22 outputs the test cycle data and the test cycle signal as a pair in synchronization with the reference clock. Further, the test cycle generator 22 sequentially outputs test cycle data and a test cycle signal indicating validity for each test cycle. In this case, the test cycle generator 22 does not simultaneously output two or more test cycle data in one cycle of the reference clock.

  Therefore, when a certain test cycle is less than 2 cycles (2 × T) of the reference clock, that is, from the start timing of the test cycle specified by a certain test cycle data, the start of the test cycle specified by the next test cycle data When the interval up to the timing is less than two cycles, the test cycle generator 22 continuously outputs the two test cycle data at intervals of the reference clock cycle (T). That is, when the upper bit of the test cycle data is 0, the test cycle data and the next test cycle data are continuously output at the interval of the reference clock cycle.

  FIG. 4 shows a configuration of the test cycle generator 22 according to the present embodiment. The test cycle generator 22 includes a cycle generator 38 and a transmission circuit 40.

  The cycle generator 38 receives data designating a test cycle from the pattern generator 20, and generates test cycle data and a test cycle signal in synchronization with the reference clock according to the received data. The transmission circuit 40 acquires test cycle data and a test cycle signal from the cycle generator 38 and transmits them to the timing generator 24 in synchronization with the reference clock.

  FIG. 5 shows a configuration of the transmission circuit 40 according to the present embodiment. The transmission circuit 40 includes a lower bit acquisition flip-flop 42, an upper bit acquisition flip-flop 44, a test cycle signal acquisition flip-flop 46, a data acquisition unit 48, a detection unit 50, and a clock enable signal transmission circuit 52. A first clock gate unit 54, a data switching unit 56, and a test cycle signal transmission circuit 58.

  The lower bit acquisition flip-flop 42 acquires the lower bits of the test cycle data generated by the cycle generator 38 at the timing of the reference clock. The upper bit acquisition flip-flop 44 acquires the upper bits of the test cycle data generated by the cycle generator 38 at the timing of the reference clock. The test cycle signal acquisition flip-flop 46 acquires the test cycle signal generated by the cycle generator 38 at the timing of the reference clock.

  The data acquisition unit 48 acquires test cycle data in synchronization with the reference clock and outputs it to the timing generator 24. As an example, the data acquisition unit 48 may include a lower bit transmission circuit 60 and an upper bit transmission circuit 62. The lower bit transmission circuit 60 acquires the lower bits of the test cycle data in synchronization with the reference clock and outputs it with the timing generator 24. The lower bit transmission circuit 60 acquires the upper bits of the test cycle data in synchronization with the reference clock and outputs it with the timing generator 24.

  The detection unit 50 detects whether or not the upper bits of the test cycle data generated by the cycle generation unit 38 match a predetermined value. In the present embodiment, 0 is set as a predetermined value of the upper bits. That is, in the present embodiment, the detection unit 50 detects whether or not the upper bit of the test cycle data generated by the cycle generation unit 38 is 0. Thereby, the detection unit 50 can detect the case where the test cycle data and the next test cycle data are continuously output in the cycle of the reference clock. Further, the detection unit 50 detects whether or not the cycle generation unit 38 has generated a test cycle signal indicating that the test cycle data is invalid, that is, whether or not the cycle has not been generated.

  Then, the detection unit 50 generates a clock enable signal indicating whether or not to supply the reference clock used for acquiring the upper bits to the data acquisition unit 48. More specifically, the detection unit 50 generates a test cycle signal indicating that the test cycle data is invalid (that is, a cycle in which the test cycle signal is not generated) or the cycle generation unit 38. A clock enable signal indicating invalidity is generated when the upper bits of the test cycle data in which the error occurs coincides with a predetermined value (0 in this embodiment). The detection unit 50 also generates a test cycle signal indicating that the test cycle data is valid (that is, in a cycle in which the test cycle signal is generated) and the test generated by the cycle generation unit 38. When the upper bits of the cycle data do not match a predetermined value (0 in this embodiment), a clock enable signal indicating validity is generated.

  The clock enable signal transmission circuit 52 acquires and propagates the clock enable signal output from the detection unit 50 in synchronization with the reference clock. For example, the clock enable signal transmission circuit 52 propagates the clock enable signal output from the detection unit 50 through a plurality of flip-flops that are continuously connected in synchronization with the test cycle data propagated by the data acquisition unit 48. Good.

  The first clock gate unit 54 receives the reference clock, and supplies the received reference clock to the data acquisition unit 48 as a reference clock used for acquiring the upper bits of the test cycle data. For example, the first clock gate unit 54 supplies the received reference clock to the upper bit transmission circuit 62.

  Here, the first clock gate unit 54 generates a test cycle signal indicating that the test cycle data is invalid (that is, a cycle in which no test cycle signal is generated) or a test cycle. When it is detected that the upper bits of the data match a predetermined value (0 in this embodiment), the data acquisition unit 48 supplies the reference clock used to acquire the upper bits of the test cycle data. Stop. If the data acquisition unit 48 sequentially propagates the upper bits of the test cycle data by a plurality of flip-flops that are continuously connected, the first clock gate unit 54, for example, The supply of the reference clock to the flip-flop that propagates the periodic data may be stopped. More specifically, as an example, the first clock gate unit 54 stops the supply of the reference clock by a clock enable signal acquired by a flip-flop at a certain stage, which is propagated synchronously by the clock enable signal transmission circuit 52. In this case, the supply of the reference clock to the next flip-flop in the upper bit transmission circuit 62 may be stopped.

  In addition to the above, the first clock gate unit 54, for example, when the cycle generator 38 generates a test cycle signal indicating invalidity of the test cycle data (that is, in a cycle in which no test cycle signal is generated). In addition, the data acquisition unit 48 may be configured to stop the supply of the reference clock used for acquiring the upper bits and the bits other than the upper bits of the test cycle data. For example, when the cycle generator 38 generates a test cycle signal indicating that the test cycle data is invalid, the first clock gate unit 54 is configured to stop the reference clock used to acquire all the bits of the test cycle data. It may be.

  When the data switching unit 56 detects that the upper bits of the test cycle data match a predetermined value (0 in the present embodiment), the data switching unit 56 outputs the upper cycle of the test cycle data output from the data acquisition unit 48. Instead of bits, a predetermined value is supplied to the timing generator 24. In the present embodiment, the data switching unit 56 supplies 0 to the timing generator 24 instead of the upper bits from the data acquisition unit 48 when the upper bits of the test cycle data are detected as 0.

  The test cycle signal transmission circuit 58 acquires and propagates the test cycle signal output from the cycle generator 38 in synchronization with the reference clock. For example, the test cycle signal transmission circuit 58 propagates the clock enable signal output from the cycle generator 38 through a plurality of stages of flip-flops continuously connected in synchronization with the test cycle data propagated by the data acquisition unit 48. It's okay.

  6 and 7 show an example of a specific circuit configuration of the transmission circuit 40. FIG. FIG. 6 shows an example of the configuration of the data acquisition unit 48 and the data switching unit 56. FIG. 7 shows an exemplary configuration of the detection unit 50, the clock enable signal transmission circuit 52, the first clock gate unit 54, and the test cycle signal transmission circuit 58.

  As an example, the low-order bit transmission circuit 60 operates in synchronization with a reference clock as shown in FIG. 6, and n (n is an integer of 2 or more) continuously connected flip-flops 64-1 to 64-64. -N may be included. Such a lower bit transmission circuit 60 obtains the lower bits of the test cycle data in synchronization with the reference clock by the first flip-flop 64-1, sequentially propagates it to the subsequent flip-flop 64, and the last-stage flip-flop 64-1 Output from the flip-flop 64-n to the timing generator 24.

  As an example, the upper bit transmission circuit 62 has the same number (ie, n) of flip-flops 66-1 to 66-as the number of flip-flops 64 included in the lower bit transmission circuit 60 as shown in FIG. n may be included. Such an upper bit transmission circuit 62 acquires the upper bits of the test cycle data by the flip-flop 66-1 at the first stage in synchronization with the reference clock, and sequentially propagates it to the flip-flop 66 at the subsequent stage. Output from the flip-flop 66-n to the timing generator 24. Each of the n flip-flops 66 included in the lower bit transmission circuit 60 operates in synchronization with a reference clock provided via a first clock gate unit 54 described later.

  As an example, the detection unit 50 may include a detection unit OR circuit 72 and a detection unit AND circuit 74 as illustrated in FIG. 7. The in-detector OR circuit 72 receives each of the upper bits of the test cycle data and outputs the result of OR operation of the value of each bit. Such an in-detector OR circuit 72 outputs a signal indicating invalidity when the upper bit of the test cycle data is 0, and valid when it is not 0.

  The in-detector AND circuit 74 outputs a result obtained by ANDing the output signal of the in-detector OR circuit 72 and the test cycle signal generated by the cycle generator 38. And such a detection part 50 outputs the output signal of the AND circuit 74 in a detection part as a clock enable signal. As a result, the detection unit 50 causes the cycle generator 38 to generate a test cycle signal indicating that the test cycle data is invalid (that is, a cycle in which the test cycle signal is not generated) or the cycle generator 38 When the upper bit of the generated test cycle data is 0, a clock enable signal indicating invalidity can be generated. The detection unit 50 is enabled when the cycle generation unit 38 generates a test cycle signal indicating the validity of the test cycle data, and the upper bits of the test cycle data generated by the cycle generation unit 38 are other than 0. A clock enable signal can be generated.

  As an example, the clock enable signal transmission circuit 52 has the same number (that is, n) of flip-flops 76-1 to 76 as the number of flip-flops 66 included in the upper bit transmission circuit 62 as shown in FIG. -N may be included. Such a clock enable signal transmission circuit 52 acquires the clock enable signal output from the detection unit 50 in synchronization with the reference clock by the first flip-flop 76-1 and sequentially propagates it to the subsequent flip-flop 76. .

  As an example, as shown in FIG. 7, the first clock gate unit 54 includes the same number (that is, n) of gate circuits 78-1 to 78-n as the flip-flop 66 included in the upper bit transmission circuit 62. It's okay. Each of the n gate circuits 78-1 to 78-n corresponds to each of the n flip-flops 66-1 to 66-n included in the upper bit transmission circuit 62. Each of the n gate circuits 78-1 to 78-n receives the reference clock and supplies it to the corresponding flip-flop 66 included in the upper bit transmission circuit 62.

  Further, each of the n gate circuits 78-1 to 78-n receives a clock enable signal input to the corresponding flip-flop 76 in the clock enable signal transmission circuit 52. Each of the n gate circuits 78-1 to 78-n supplies the reference clock to the corresponding flip-flop 66 included in the upper bit transmission circuit 62 and receives the received clock enable signal if the received clock enable signal is valid. If the clock enable signal is invalid, the supply of the reference clock to the corresponding flip-flop 66 included in the upper bit transmission circuit 62 is stopped. As a result, the first clock gate unit 54 has a plurality of high-order bit transmission circuits 62 in the case where the high-order bits of the test cycle data are sequentially propagated by the n flip-flops 66-1 to 66 -n that are continuously connected. The supply of the reference clock to the flip-flop 66 that propagates the test cycle data among the flip-flops 66-1 to 66-n can be stopped.

  As an example, the data switching unit 56 may include one or a plurality of in-data switching unit AND circuits 68 corresponding to the values of the respective bits of the test cycle data, as shown in FIG. Each of the one or more AND circuits 68 in the data switching unit outputs the value of the corresponding bit of the test cycle data output from the upper bit transmission circuit 62 and the flip-flop 76-n at the final stage of the clock enable signal transmission circuit 52. A signal obtained by ANDing the clock enable signal is output.

  Then, the data switching unit 56 outputs the output signal of the data switching unit AND circuit 68 to the timing generator 24 as the upper bits of the test cycle data. Thereby, the data switching unit 56 is when the test cycle data output from the upper bit transmission circuit 62 is valid and the upper bit of the test cycle data is not detected as 0 (that is, when the clock enable signal is valid). The value output by the upper bit transmission circuit 62 can be output to the timing generator 24 as it is as the upper bits of the test cycle data.

  Further, such a data switching unit 56 is configured such that when the test cycle data output from the upper bit transmission circuit 62 is invalid or when the upper bit of the test cycle data is detected as 0 (that is, the clock enable signal is invalid). ), 0 can be output to the timing generator 24 as the upper bits of the test cycle data. As a result, the data switching unit 56 can prohibit the timing generator 24 from outputting unnecessary data when the test cycle data output from the upper bit transmission circuit 62 is invalid. Further, the data switching unit 56 can output correct data to the timing generator 24 when the upper bit of the test cycle data is detected as 0.

  As an example, the test cycle signal transmission circuit 58 has the same number (that is, n) of flip-flops 80-1 to 80 as the flip-flop 66 included in the upper bit transmission circuit 62 as shown in FIG. -N may be included. Such a test cycle signal transmission circuit 58 acquires the test cycle signal output from the cycle generator 38 by the first flip-flop 80-1 in synchronization with the reference clock, and sequentially propagates it to the subsequent flip-flop 80. Then, the data is output from the flip-flop 80-n at the final stage to the timing generator 24.

  FIG. 8 shows an example of a timing chart of each signal in the transmission circuit 40. This example is an example of a timing chart in the case where 8-bit test cycle data and test cycle signals output from the cycle generator 38 are transmitted to the timing generator 24 by continuously connected three-stage flip-flops. Indicates. Further, the test cycle data of this example includes 4 bits of upper bits and 4 bits of lower bits.

  FIG. 8A shows a reference clock. RATE_IN in FIG. 8B indicates a test cycle signal generated by the cycle generator 38. RATEDT [7: 0] _IN in (C) of FIG. 8 indicates test cycle data generated by the cycle generator 38.

  In FIG. 8D, gckl — 1 indicates a reference clock that the first clock gate unit 54 supplies to the first-stage flip-flop 66 of the upper bit transmission circuit 62. RATEDT_1 [3: 0] in FIG. 8E indicates the value of the lower bit of the test cycle data acquired by the first-stage flip-flop 64 of the lower bit transmission circuit 60. RATEDT_1 [7: 4] in (F) of FIG. 8 indicates the value of the lower bit of the test cycle data acquired by the first-stage flip-flop 66 of the upper bit transmission circuit 62.

  8 indicates a reference clock that the first clock gate unit 54 supplies to the second-stage flip-flop 66 of the upper bit transmission circuit 62. RATEDT_2 [3: 0] in FIG. 8H indicates the value of the lower bit of the test cycle data acquired by the second-stage flip-flop 64 of the lower bit transmission circuit 60. RATEDT_2 [7: 4] in (I) of FIG. 8 indicates the value of the lower bit of the test cycle data acquired by the second-stage flip-flop 66 of the upper bit transmission circuit 62.

  8 indicates a reference clock that the first clock gate unit 54 supplies to the third-stage flip-flop 66 of the upper bit transmission circuit 62. RATEDT_3 [3: 0] in FIG. 8K indicates the value of the lower bit of the test cycle data acquired by the third-stage flip-flop 64 of the lower bit transmission circuit 60. RATEDT — 3 [7: 4] in (L) of FIG. 8 indicates the value of the lower bit of the test cycle data acquired by the third-stage flip-flop 66 of the upper bit transmission circuit 62.

  RATE_OUT in (M) of FIG. 8 indicates a test cycle signal output from the transmission circuit 40 to the timing generator 24. RATEDT [7: 0] _OUT in (N) of FIG. 8 indicates test cycle data output from the transmission circuit 40 to the timing generator 24.

  As shown in FIG. 8C, the cycle generator 38 has the test cycle data (RATE1) with the value “0x0C”, the test cycle data (RATE2) with the value “0x23”, and the value “0x37”. Test cycle data (RATE3), test cycle data (RATE4) having a value of “0x05”, and test cycle data (RATE5) having a value of “0xF1” are sequentially generated.

  Here, the test cycle data (RATE2) having a value of “0x23”, the test cycle data (RATE3) having a value of “0x37”, and the test cycle data (RATE5) having a value of “0xF1” are not 0 in the upper bits. In such a case, the first clock gate unit 54 corresponds to these test cycle data (RATE1, RATE3, RATE5) as shown in (D), (G), and (J) of FIG. The reference clock is supplied to the upper bit transmission circuit 62.

  In contrast, the test cycle data (RATE1) having a value of “0x0C” and the test cycle data (RATE4) having a value of “0x05” have a high-order bit of 0. Therefore, other test cycle data (RATE2, RATE5) are generated in the cycle of the reference clock next to these test cycle data. In such a case, as shown in FIGS. 8D, 8G, and 8J, the first clock gate unit 54 has the upper rank of each reference clock corresponding to these test cycle data (RATE1, RATE4). The supply to the bit transmission circuit 62 is stopped. Thereby, the first clock gate unit 54 can reduce the power consumed in the upper bit transmission circuit 62 when the upper bit of the test cycle data is 0.

  Further, as shown in (L) and (M) of FIG. 8, the data switching unit 56 receives test cycle data (RATE1) having a value of “0x0C” and test cycle data (RATE4) having a value of “0x05”. When outputting to the timing generator 24, the value of the upper bit is replaced with "0" and output. Thereby, when the supply of the reference clock to the upper bit transmission circuit 62 is stopped and the upper bit transmission circuit 62 does not transmit a correct value, the data switching unit 56 replaces the test period with the correct value in the final stage. Data can be output to the timing generator 24.

  Further, as shown in FIG. 8B, the test cycle signal from the test cycle data (RATE2) having a value “0x23” to the test cycle data (RATE3) having a value “0x37” indicates invalidity. ing. Also, the test cycle signal from the test cycle data (RATE3) having a value of “0x37” to the test cycle data (RATE4) having a value of “0x05” also indicates invalidity. In such a case, as shown in (D), (G), and (J) of FIG. 8, the first clock gate unit 54 is configured to output each reference clock during the period in which the test cycle signal is invalid. Supply to the upper bit transmission circuit 62 is stopped. Thus, the first clock gate unit 54 can reduce the power consumed in the upper bit transmission circuit 62 when the test cycle data indicates invalidity.

  As described above, the transmission circuit 40 according to the present embodiment generates a test cycle signal indicating that the test cycle data output from the cycle generator 38 is invalid, or the value of the upper bit of the test cycle data is set in advance. When it is detected that the value matches the predetermined value, the supply of the reference clock for acquiring and propagating the upper bits of the test cycle data to the data acquisition unit 48 is stopped. Then, when it is detected that the value of the upper bit of the test cycle data matches a predetermined value, the transmission circuit 40 replaces the value of the upper bit of the test cycle data output from the data acquisition unit 48. The predetermined value is output to the timing generator 24.

  Thereby, according to the transmission circuit 40, the valid test cycle data can be propagated from the cycle generator 38 to the timing generator 24, and the reference clock used for the propagation of the invalid test cycle data is stopped to consume power. Can be reduced. Further, according to the transmission circuit 40, when the high-order bits of the valid test cycle data have a predetermined value, the reference clock used for the propagation of the high-order bits of the valid test cycle data is stopped and the power consumption is reduced. Can be reduced.

  In particular, when the high order bit of the test cycle data is 0, effective test cycle data is continuously propagated at intervals of the reference clock, so that power consumption increases. Therefore, when the upper bit of the test cycle data is 0, the power consumption can be efficiently reduced by stopping the reference clock used for propagation of the higher bit of the effective test cycle data.

  In such a transmission circuit 40, the high-order bit transmission circuit 62 of the data acquisition unit 48 replaces the high-order bits of the test cycle data (that is, the bit portion indicating the unit time larger than the cycle of the reference clock) with the test A configuration may be adopted in which at least one predetermined bit (hereinafter referred to as a target bit) of the periodic data is propagated to the timing generator 24. In this case, the lower bit transmission circuit 60 propagates bits other than the target bit in the test cycle data to the timing generator 24.

  In this case, the detection unit 50 detects whether or not the target bit matches a predetermined value. Further, in this case, the first clock gate unit 54 is configured such that the cycle generator 38 generates a test cycle signal indicating that the test cycle data is invalid, or the target bit in the test cycle data matches a predetermined value. When this is detected, the data acquisition unit 48 stops supplying the reference clock used for acquiring the target bit. In this case, when it is detected that the target bit in the test cycle data matches a predetermined value, the data switching unit 56 replaces the target bit from the data acquisition unit 48 with a predetermined value. The value is supplied to the timing generator 24. Even with such a configuration, the transmission circuit 40 can reduce the power consumption by stopping the reference clock used for propagation of the target bit of the valid test cycle data.

  Furthermore, such a transmission circuit 40 may be provided in a device other than the test apparatus 10. That is, the transmission circuit 40 may transmit data and a data enable signal indicating whether or not the data is valid from the transmission circuit to the reception circuit.

In this case, the transmission circuit 40 receives data and a data enable signal from the transmission circuit instead of receiving the test period data and the test period signal from the period generator 38. Then, the transmission circuit 40 outputs data and a data enable signal to the receiving circuit instead of outputting the test cycle data and the test cycle signal to the timing generator 24. Thereby, according to the transmission circuit 40, power consumption can be reduced even when data and a data enable signal are transmitted from the transmission circuit to the reception circuit.

  FIG. 9 shows a configuration of the timing generator 24 according to the present embodiment. The timing generator 24 includes a timing data generation unit 110, a distribution unit 112, a plurality of counter delay units 114 (114-1 to 114-m), a first synthesis unit 116, a second synthesis unit 118, Delay unit 120.

  The timing data generation unit 110 generates timing data that specifies the generation timing of a timing signal that indicates the timing for transmitting and receiving signals to and from the device under test 200, and a timing enable signal that indicates whether the timing data is valid. . The timing data represents the delay time from the timing at which the timing data is received to the timing signal generation timing with an accuracy smaller than the cycle of the reference clock.

  For example, the timing data generation unit 110 may include an addition unit 132 that adds the test cycle data received from the test cycle generator 22 and the delay data provided from the pattern generation unit 20. The timing data generation unit 110 may output the addition result by the addition unit 132 as timing data. Further, the timing data generation unit 110 may delay the test cycle signal received from the test cycle generator 22 by the time consumed by the addition processing of the test cycle data and the delay data, and output the delayed signal as a timing enable signal.

  The distribution unit 112 distributes valid timing data and timing enable signals sequentially output from the timing data generation unit 110 to any one of the plurality of counter delay units 114. The distribution unit 112 cyclically selects any one of the plurality of counter delay units 114 each time valid timing data and a timing enable signal are output from the timing data generation unit 110, and selects the selected counter delay. Valid timing data and a timing enable signal are supplied to the unit 114.

  Each of the plurality of counter delay units 114 receives the timing data and the timing enable signal distributed by the distribution unit 112. Each of the plurality of counter delay units 114 converts the received timing data into higher-order data that is a data portion representing a delay time in units equal to or greater than the period of the reference clock included in the timing data, and the higher-order data included in the timing data. The data is separated into lower data, which is another data portion other than the side data. For example, the higher-order data may be data that represents the delay time from the timing at which the timing data is received to the timing at which the timing signal is generated, with accuracy in units of the reference clock. The lower-order data may be data representing a component that is less than the period of the reference clock in the delay time.

  Each of the plurality of counter delay units 114 counts the reference clock for the higher-order data included in a part of the timing data from the timing when the valid timing data is received. Then, each of the plurality of counter delay units 114 outputs a timing enable signal after counting the upper data reference clocks from the timing at which the timing data is received. Further, each of the plurality of counter delay units 114 outputs lower-order data included in the timing data in synchronization with the timing enable signal.

  The first synthesis unit 116 multiplex-synthesizes the timing enable signals output from each of the plurality of counter delay units 114 and supplies the resultant signals to the micro delay unit 120 as one signal. As an example, the first synthesizing unit 116 synthesizes the timing enable signals output from each of the plurality of counter delay units 114 into one signal by OR operation and supplies the synthesized signal to the micro delay unit 120.

  The second synthesizing unit 118 multiplex-synthesizes the lower-order data included in the timing data output from each of the plurality of counter delay units 114 and supplies the result to the micro delay unit 120 as one signal. For example, the second synthesizing unit 118 multiplex-synthesizes the lower-order data output from each of the plurality of counter delay units 114 by OR operation and supplies the result to the micro delay unit 120 as one signal. Each of the plurality of counter delay units 114 outputs 0 as lower side data when the other distribution unit 112 outputs valid lower side data.

  The minute delay unit 120 delays the timing enable signal received from the first synthesis unit 116 by a time corresponding to the lower-order data included in the timing data received from the second synthesis unit 118. The minute delay unit 120 may be a variable delay element that delays the received signal by a time corresponding to a given set value. The minute delay unit 120 supplies the delayed timing enable signal to the subsequent waveform shaping unit 26 or the timing comparator 32 as a timing signal indicating the timing at which signals are transmitted to and received from the device under test 200.

  According to the timing generator 24 having such a configuration, the timing enable signal can be delayed by the plurality of counter delay units 114 with the periodic accuracy of the reference clock. Furthermore, according to such a timing generator 24, the timing enable signal delayed by each of the plurality of counter delay units 114 can be further delayed by the minute delay unit 120 with an accuracy less than the period of the reference clock.

  FIG. 10 shows an example of a timing chart of the timing enable signal input to the plurality of counter delay units 114. FIG. 10A shows a reference clock. FIG. 10B shows a timing enable signal received by the distribution unit 112.

  FIG. 10C shows a timing enable signal that the first counter delay unit 114-1 receives from the distribution unit 112. FIG. 10D shows a timing enable signal that the second counter delay unit 114-2 receives from the distribution unit 112. FIG. 10E shows a timing enable signal that the third counter delay unit 114-3 receives from the distribution unit 112.

  Each time the distribution unit 112 receives a timing enable signal from the timing data generation unit 110, the distribution unit 112 selects the plurality of counter delay units 114 one by one in order and distributes the received timing enable signal. For example, the distribution unit 112 distributes the timing enable signal received at time t21 to the first counter delay unit 114-1, as illustrated in FIG. Further, as shown in FIG. 10D, the distribution unit 112 distributes the timing enable signal received at time t22 next to time t21 to the second counter delay unit 114-2. Further, as shown in FIG. 10E, the distribution unit 112 distributes the timing enable signal received at time t23 next to time t22 to the third counter delay unit 114-3.

  FIG. 11 shows an example of a timing chart of timing enable signals and lower-order data output from the plurality of counter delay units 114.

  FIG. 11A shows a timing enable signal output from the first counter delay unit 114-1. (B) of FIG. 11 shows the lower-order data output from the first counter delay unit 114-1. FIG. 11C shows the timing enable signal output from the second counter delay unit 114-2. (D) of FIG. 11 shows the lower-order data output from the second counter delay unit 114-2. FIG. 11E shows a timing enable signal output from the third counter delay unit 114-3. (F) of FIG. 11 shows lower-order data output from the third counter delay unit 114-3.

  FIG. 11E shows a timing enable signal output from the first combining unit 116. (F) of FIG. 11 shows the lower-order data output from the second synthesis unit 118.

  The first synthesizing unit 116 multiplex-synthesizes the timing enable signals output separately from each of the plurality of counter delay units 114 and supplies them to the micro delay unit 120 as one signal. Similarly, the second synthesizing unit 118 multiplex-synthesizes the lower-order data included in the timing data separately output from each of the plurality of counter delay units 114 and supplies the result to the micro delay unit 120 as one signal.

  In this way, the distribution unit 112 cyclically selects a plurality of counter delay units 114 one by one, and interleaves and executes delay processing in units of reference clock cycles. Thereby, according to the timing generator 24, as a result of the timing signal specified in a certain test cycle being generated within the range of the next test cycle beyond the test cycle, a plurality of signals are generated in the range of the next test cycle. Even when the timing signal is generated, the timing signal can be continuously generated without causing the operation to fail.

  FIG. 12 shows the configuration of the counter delay unit 114. Each of the plurality of counter delay units 114 has the same configuration. The counter delay unit 114 includes a count unit 140, a state holding unit 142, and a second clock gate unit 144.

  The count unit 140 operates in synchronization with the reference clock provided from the second clock gate unit 144. After receiving valid timing data from the timing data generating unit 110, the counting unit 140 counts the reference clocks by the number of higher-order data representing the time in units equal to or more than the cycle of the reference clock included in the timing data, Lower-order data other than the higher-order data of the timing data and a timing enable signal indicating the validity of the timing data are output. For example, the count unit 140 holds a state signal indicating that the state holding unit 142 is counting, and the count value becomes a value after counting the number of higher-order data. A timing enable signal indicating the validity of the timing data may be output.

  For example, the count unit 140 may include a zero detection unit 150, an inverting circuit 152, a counter 154, a first AND circuit 156, a first flip-flop 158, and a second AND circuit 160. The zero detection unit 150 outputs a signal indicating validity when the count value of the counter 154 is zero, and outputs a signal indicating invalidity when the count value of the counter 154 is other than zero. The inverting circuit 152 inverts the logic of the output signal of the zero detection unit 150 and supplies the inverted signal to the DEC terminal of the counter 154.

  The counter 154 acquires the higher-order data of the timing data output from the timing data generation unit 110 as the count value when the timing enable signal provided from the distribution unit 112 is valid. When the signal supplied to the DEC terminal indicates validity (that is, when the count value of the counter 154 is other than 0), the counter 154 sets the acquired count value one by one in synchronization with the supplied reference clock. Decrease.

  The first AND circuit 156 outputs a timing enable signal indicating validity when the output signal of the zero detection unit 150 indicates validity and the state signal output by the state holding unit 142 indicates validity. The first flip-flop 158 obtains lower-order data of the timing data output from the timing data generation unit 110 when the timing enable signal provided from the distribution unit 112 is valid. The second AND circuit 160 outputs the lower-order data acquired by the first flip-flop 158 when the output signal of the zero detection unit 150 is valid and the status signal output by the status holding unit 142 is valid.

  After receiving valid timing data, the counting unit 140 having such a configuration counts the reference clock for the value indicated in the upper data included in the timing data, and after counting, the lower data and the timing data A timing enable signal indicating validity can be output.

  The state holding unit 142 holds a state signal indicating whether the count unit 140 is counting the number of higher-order data included in valid timing data. For example, the state holding unit 142 may output a status signal indicating that the count unit 140 is valid when the count unit 140 is counting, and invalid when the count unit 140 is not counting.

  As an example, the state holding unit 142 may include a first OR circuit 162 and a second flip-flop 164. In the first OR circuit 162, when the output signal of the zero detection unit 150 of the count unit 140 indicates validity (that is, when the count value of the counter 154 is 0), or the timing enable signal provided from the distribution unit 112 is valid. Is output, a signal indicating validity is output. The second flip-flop 164 operates in synchronization with the reference clock, and acquires the timing enable signal provided from the distribution unit 112 when the output signal of the first OR circuit 162 indicates valid. When the timing enable signal indicating validity is given from the distribution unit 112, the first OR circuit 162 starts holding a value indicating validity. Then, the first OR circuit 162 starts holding a value indicating invalidity in response to the count value of the counter 154 becoming zero. Thereafter, the first OR circuit 162 continues to hold the value indicating invalidity until the next timing enable signal indicating validity is provided.

  The second clock gate unit 144 stops the supply of the reference clock to the count unit 140 when the count unit 140 does not count the number of higher-order data included in valid timing data. More specifically, the second clock gate unit 144 starts supplying the reference clock to the count unit 140 in response to receiving a timing enable signal indicating that the timing data is valid. Then, the second clock gate unit 144 stops the supply of the reference clock to the count unit 140 when the count value of the count unit 140 becomes a value after counting the number of higher-order data.

  For example, the second clock gate unit 144 may include a second OR circuit 166 and a gate circuit 168. The second OR circuit 166 receives the timing enable signal given from the distribution unit 112 when the output signal of the zero detection unit 150 of the count unit 140 indicates invalidity (that is, when the count value of the counter 154 is other than 0). When it indicates valid, a clock enable signal indicating valid is output.

  The gate circuit 168 receives the clock enable signal from the second OR circuit 166. When the clock enable signal indicates validity (that is, when the count value of the counter 154 is other than 0 or when the timing enable signal provided from the distribution unit 112 indicates validity), the gate circuit 168 The reference clock is supplied to the counter 154 and the first flip-flop 158. When the clock enable signal indicates invalidity, the gate circuit 168 stops supplying the reference clock to the counter 154 and the first flip-flop 158 in the count unit 140.

  More specifically, the second clock gate unit 144 starts supplying the reference clock to the counter 154 and the first flip-flop 158 in response to receiving the timing enable signal indicating the validity of the timing data. Then, the second clock gate unit 144 stops supplying the reference clock to the counter 154 and the first flip-flop 158 in response to the count value of the counter 154 becoming zero.

  Such a counter delay unit 114 supplies a reference clock to the count unit 140 during a period when the count unit 140 operates effectively, and a reference clock for the count unit 140 during a period when the count unit 140 does not operate effectively. Stop supplying. Thereby, the counter delay unit 114 can reduce the current consumption of the count unit 140.

  FIG. 13 shows an example of a timing chart of each signal in the counter delay unit 114. FIG. 13A shows a reference clock. FIG. 13B shows a timing enable signal received by the counter delay unit 114. FIG. 13C shows a timing enable signal received by the counter delay unit 114. FIG. 13D shows the count value of the counter 154.

  FIG. 13E shows a status signal output from the second flip-flop 164. FIG. 13F shows lower-order data held by the first flip-flop 158. FIG. 13G shows a reference clock given to the counter 154 and the first flip-flop 158. (H) in FIG. 13 shows a timing enable signal output from the counter delay unit 114. (I) in FIG. 13 shows lower-order data output from the counter delay unit 114.

  As shown in FIG. 13B, the counter delay unit 114 receives a timing enable signal indicating validity from the distribution unit 112 at time t41. When receiving the timing enable signal indicating validity from the distribution unit 112, the second flip-flop 164 starts holding the value indicating validity from the timing of the next reference clock, as shown in FIG. 13E. .

  When receiving a timing enable signal indicating validity from the distribution unit 112, the gate circuit 168, as shown in FIG. 13G, at the timing of the next reference clock (time t42), the counter 154 and the first Supply of the reference clock (gclk) to the flip-flop 158 is started. As a result, as shown in FIG. 13D, the counter 154 fetches the higher-order data (for example, 0x8) of the timing data at the timing when the timing enable signal is received as the count value, and thereafter the count value is set to 1. Decrement by one. Further, as shown in FIG. 13F, the first flip-flop 158 takes in lower-order data (for example, 0xC) of the timing data at the timing when the timing enable signal is received.

  As shown in FIG. 13H, the first AND circuit 156 outputs a timing enable signal at time t43 when the count value of the counter 154 reaches zero. Further, as shown in FIG. 13I, the second AND circuit 160 outputs the lower-order data held by the first flip-flop 158 in synchronization with the output of the timing enable signal from the first AND circuit 156. To do.

  Then, as shown in FIG. 13G, when the count value of the counter 154 reaches 0, the gate circuit 168 receives the counter 154 and the first flip-flop 158 at the next reference clock timing (time t44). The supply of the reference clock (gclk) to is stopped. Further, as shown in FIG. 13E, when the count value of the counter 154 reaches 0, the second flip-flop 164 starts holding a value indicating invalidity from the timing of the next reference clock.

  As described above, the counter delay unit 114 supplies the reference clock to the count unit 140 during a period in which the count unit 140 operates effectively, and the reference clock for the count unit 140 in a period during which the count unit 140 does not operate effectively. Supply can be stopped. Thereby, the counter delay unit 114 can reduce the current consumption of the count unit 140.

  Furthermore, such a counter delay unit 114 may be provided as a counter circuit in a device other than the test apparatus 10. That is, the counter delay unit 114 may function as a counter circuit that counts data supplied from the transmission circuit.

  In this case, the counter delay unit 114 receives data and a data enable signal from the transmission circuit instead of receiving timing data and a timing enable signal from the timing data generation unit 110. The counter delay unit 114 outputs a data enable signal instead of outputting a timing enable signal. Thereby, the counter delay unit 114 can reduce power consumption even when the number of data represented by the data given from the transmission circuit is counted.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.

10 test devices, 20 pattern generators, 22 test cycle generators, 24 timing generators, 26 waveform shaping units, 28 drivers, 30 level comparators, 32 timing comparators, 34 determination units, 38 cycle generators, 40 transmission circuits, 42 Low-order bit acquisition flip-flop, 44 High-order bit acquisition flip-flop, 46 Test period signal acquisition flip-flop, 48 Data acquisition unit, 50 Detection unit, 52 Clock enable signal transmission circuit, 54 First clock gate unit, 56 Data switching Unit, 58 test cycle signal transmission circuit, 60 lower bit transmission circuit, 62 upper bit transmission circuit, 64 flip-flop, 66 flip-flop, 68 data switching unit AND circuit, 72 detection unit OR circuit, 74 detection unit AND circuit, 76 Flop, 78 gate circuit, 80 flip-flop, 110 timing data generation unit, 112 distribution unit, 114 counter delay unit, 116 first synthesis unit, 118 second synthesis unit, 120 minute delay unit, 132 addition unit, 140 count unit, 142 state holding unit, 144 second clock gate unit, 150 zero detection unit, 152 inverting circuit, 154 counter, 156 first AND circuit, 158 first flip-flop, 160 second AND circuit, 162 first OR circuit, 164 second flip-flop 166 2nd OR circuit, 168 gate circuit, 200 device under test

Claims (15)

A test apparatus for testing a device under test,
A test cycle generator for generating a test cycle signal indicating a timing that is a reference for a test cycle start timing and test cycle data representing a delay amount from the test cycle signal to the start timing of the test cycle in synchronization with a reference clock; ,
A timing generator for generating a timing for transmitting / receiving a signal to / from the device under test with reference to a start timing of a test cycle specified by the test cycle data;
With
The test cycle generator is
A cycle generator for generating the test cycle data and the test cycle signal;
A data acquisition unit that acquires the test cycle data in synchronization with the reference clock and outputs the data to the timing generator;
A clock gate unit for stopping supply of the reference clock to the data acquisition unit in a cycle in which the test cycle signal is not generated;
Test equipment with The test cycle generator further includes a detection unit that detects whether or not at least one predetermined bit in the test cycle data generated by the cycle generation unit matches a predetermined value,
When the clock gate unit detects a cycle in which the test cycle signal is not generated, or when it is detected that the at least one bit in the test cycle data matches the predetermined value, Stopping the supply of the reference clock used by the data acquisition unit to acquire the at least one bit;
The test cycle generator, when it is detected that the at least one bit in the test cycle data matches the predetermined value, instead of the at least one bit from the data acquisition unit, The test apparatus according to claim 1, further comprising a data switching unit that supplies the predetermined value to the timing generator.   The detection unit detects whether or not a high-order bit having a predetermined number of bits matches the predetermined value as the at least one bit in the test cycle data generated by the cycle generation unit. Item 3. The test apparatus according to Item 2. The cycle generator includes the upper bit indicating a unit time larger than the reference clock cycle and a lower bit indicating a unit time less than the reference clock cycle in the time until the start timing of the test cycle. Generating periodic data and the test periodic signal;
The detection unit detects whether the upper bit is 0;
The clock gate unit is used by the data acquisition unit to acquire the upper bit in a cycle in which the test cycle signal is not generated or when the upper bit of the test cycle data is detected as 0. Stop supplying the reference clock;
The data switching unit supplies 0 to the timing generator instead of the upper bit from the data acquisition unit when the upper bit of the test cycle data is detected as 0. The test apparatus described. The data acquisition unit
In synchronization with the reference clock, the lower bits of the test cycle data are acquired by the first flip-flop, sequentially propagated to the subsequent flip-flop, and output from the final flip-flop to the timing generator. A lower bit transmission circuit;
In synchronization with the reference clock, the upper bits of the test cycle data are acquired by the first flip-flop, sequentially propagated to the subsequent flip-flop, and output from the final flip-flop to the timing generator. An upper bit transmission circuit;
Including
The test cycle generator is
A clock enable that obtains a clock enable signal indicating whether or not to supply the reference clock used for obtaining the upper bits in synchronization with the reference clock by a first flip-flop and sequentially propagates it to a subsequent flip-flop. A signal transmission circuit;
Synchronized with the reference clock, the test cycle signal is acquired by the first flip-flop, sequentially propagated to the subsequent flip-flop, and output from the final flip-flop to the timing generator. Circuit,
Have
When the clock enable signal propagated by the clock enable signal transmission circuit indicates that the clock enable signal at a certain stage stops the supply of the reference clock, the clock gate unit at the next stage flip-flop in the upper bit transmission circuit The test apparatus according to claim 4, wherein the supply of the reference clock to is stopped.   The data switching unit is output from the final stage of the upper bit transmission circuit when receiving the clock enable signal indicating that the supply of the reference clock is stopped from the final stage of the clock enable signal transmission circuit. The test apparatus according to claim 5, wherein 0 is output to the timing generator instead of the upper bits of the test cycle data. A transmission circuit for transmitting data and a data enable signal indicating whether the data is valid from a transmission circuit to a reception circuit,
A data acquisition unit that acquires the data from the transmission circuit and outputs the data to the reception circuit in synchronization with a reference clock;
A clock gate unit for stopping supply of the reference clock to the data acquisition unit when the data enable signal indicating that the data is invalid is received from the transmission circuit;
A transmission circuit comprising: A detector for detecting whether or not at least one predetermined bit in the data matches a predetermined value;
The clock gate unit detects when the data enable signal indicating that the data is invalid is received from the transmission circuit, or when the at least one bit in the data matches the predetermined value. The data acquisition unit stops supplying the reference clock used to acquire the at least one bit,
Further, when it is detected that the at least one bit in the data matches the predetermined value, the predetermined value is replaced with the at least one bit from the data acquisition unit. The transmission circuit according to claim 7, further comprising a data switching unit that supplies the reception circuit. A test apparatus for testing a device under test,
A timing data generation unit for generating timing data for specifying timing generation of a timing signal indicating timing for transmitting / receiving a signal to / from the device under test and a timing enable signal indicating whether the timing data is valid;
Reference clocks corresponding to the number of higher-order data that operate in synchronization with a reference clock and represent time in units equal to or greater than the period of the reference clock included in the timing data after receiving the valid timing data from the timing data generator A counting unit that outputs the timing enable signal indicating the validity of the timing data and lower-order data other than the higher-order data of the timing data,
A clock gate unit that stops supply of the reference clock to the count unit when the count unit does not count the number of higher-order data included in the valid timing data;
A test apparatus comprising: The clock gate unit is
In response to receiving the timing enable signal indicating the validity of the timing data, the supply of the reference clock to the count unit is started,
The test apparatus according to claim 9, wherein the supply of the reference clock to the count unit is stopped in response to the count value of the count unit becoming a value after counting the number of higher-order data. A state holding unit for holding a state signal indicating whether the count unit is counting the number of higher-order data included in the valid timing data;
The counting unit holds the state signal indicating that the state holding unit is counting, and when the count value becomes a value after counting the number of higher-order data, The test apparatus according to claim 10, wherein the timing enable signal indicating validity of timing data is output. A plurality of sets of the count unit, the clock gate unit, and the state holding unit,
A distribution unit that distributes the effective timing data sequentially output from the timing data generation unit and the timing enable signal indicating the validity of the timing data to each of the plurality of sets;
The test apparatus according to claim 11, further comprising: A control method of a test apparatus for testing a device under test,
The test apparatus comprises:
A test cycle signal for generating a test cycle signal representing a delay amount from the test cycle signal to the start timing of the test cycle in synchronism with the reference clock; ,
A timing generator for generating a timing for transmitting / receiving a signal to / from the device under test with reference to a start timing of a test cycle specified by the test cycle data;
With
The test cycle generator is
A cycle generator for generating the test cycle data and the test cycle signal;
A data acquisition unit for acquiring the test cycle data in synchronization with the reference clock and outputting the data to the timing generator;
A test apparatus control method for stopping supply of the reference clock to the data acquisition unit in a cycle in which the test cycle signal is not generated. A transmission circuit control method for transmitting data and a data enable signal indicating whether the data is valid from a transmission circuit to a reception circuit,
The transmission circuit includes a data acquisition unit that acquires the data from the transmission circuit and outputs the data to the reception circuit in synchronization with a reference clock,
A method for controlling a transmission circuit, wherein when the data enable signal indicating that the data is invalid is received from the transmission circuit, the supply of the reference clock to the data acquisition unit is stopped. A control method of a test apparatus for testing a device under test,
The test apparatus comprises:
A timing data generation unit for generating timing data for specifying timing generation of a timing signal indicating timing for transmitting / receiving a signal to / from the device under test and a timing enable signal indicating whether the timing data is valid;
Reference clocks corresponding to the number of higher-order data that operate in synchronization with a reference clock and represent time in units equal to or greater than the period of the reference clock included in the timing data after receiving the valid timing data from the timing data generator And counting unit for outputting the lower side data other than the upper side data of the timing data and the timing enable signal indicating the validity of the timing data,
A control method of a test apparatus that stops supply of the reference clock to the count unit when the count unit does not count the number of higher-order data included in the valid timing data.

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