CN116684722B - MIPI C-PHY signal receiving device, MIPI C-PHY signal receiving method and camera module testing system - Google Patents

Abstract

The invention discloses an MIPI C-PHY signal receiving device, a method and a camera module testing system, wherein the device receives an LP signal in a C-PHY signal through an LP decoding module, analyzes and obtains an LP waveform sequence, and sends the LP waveform sequence to a control state machine; the control state machine analyzes the LP signals to obtain LP analysis data; the data recovery module performs edge detection on the sampling result of the HS signal to obtain an edge detection result; the symbol decoding module decodes the signal line level state sequence into a symbol value; the serial-parallel conversion module finds a synchronous word from the symbol value and converts serial data into parallel data; the character demapping module demaps the parallel data into actual data, can realize the function of receiving the C-PHY signal and recovering the transmission data, does not need a special C-PHY physical decoding device, reduces the data transmission cost and improves the data transmission rate and the transmission efficiency.

Description

MIPI C-PHY signal receiving device, MIPI C-PHY signal receiving method and camera module testing system

Technical Field

The present invention relates to the field of image data processing technologies, and in particular, to an MIPI C-PHY signal receiving apparatus and method, and a camera module testing system.

Background

With the development of digital camera technology, the resolution of the camera is continuously improved, and the data transmission rate is also higher and higher; the mobile industry processor channel limited port Physical layer interface (Mobile Industry Processor Interface Channel-limited-Physical, MIPI C-PHY) interface can achieve higher data transmission rate with lower line rate due to the coding characteristic of the interface; there are also more cameras that use MIPI C-PHY as a physical interface.

In order to detect a camera using the MIPI C-PHY interface, it is necessary to receive image data using a device; typically, the receiving device of the MIPI C-PHY would use a separate bridge or a field programmable gate array (Field Programmable Gate Array, FPGA) or micro control unit (Microcontroller Unit, MCU) supporting the MIPI C-PHY physical interface to implement the data receiving function; however, such bridges and FPGA/MCUs are typically expensive and cannot be custom configured for the underlying physical interface.

Disclosure of Invention

The invention mainly aims to provide an MIPI C-PHY signal receiving device, an MIPI C-PHY signal receiving method and a camera module testing system, and aims to solve the technical problems that in the prior art, data receiving cannot carry out self-defined setting on a bottom physical interface, data transmission cost is high, and transmission rate and transmission efficiency are low.

In a first aspect, the present invention provides an MIPI C-PHY signal receiving device including an LP section and an HS section, wherein,

the LP section includes a LP decoding module, a control state machine, and a LP data buffer; the HS part comprises a data recovery module, a symbol decoding module, a serial-parallel conversion module, a character demapping module and an HS data buffer; the LP section establishing contact with the HS section through the control state machine;

the LP decoding module is used for receiving the LP signals in the C-PHY signals, calculating to obtain an LP clock, analyzing the LP signals according to the LP clock, analyzing to obtain an LP waveform sequence, and sending the LP waveform sequence to a control state machine;

the control state machine is used for judging the physical link state of the current channel according to the LP waveform sequence and switching the LP and HS transmission modes;

the data recovery module is used for receiving the sampling result of the HS signal under the HS signal analysis mode, carrying out edge detection on the sampling result to obtain an edge detection result, and recovering the edge detection result into a signal line level state sequence;

the symbol decoding module is used for receiving the signal line level state sequence sent by the data recovery module and decoding the signal line level state sequence into a symbol value;

the serial-parallel conversion module is used for receiving the symbol value sent by the symbol decoding module, finding a synchronous word from the symbol value and converting serial data into parallel data;

the character demapping module is used for receiving the parallel data sent by the serial-parallel conversion module, demapping the parallel data into actual data, and sending the actual data to the HS data buffer for buffering.

Optionally, the data recovery module includes an input delay unit, a clock management unit, a deserializing unit, and a data recovery unit; the input delay unit is connected with the deserializing unit, the clock management unit is respectively connected with the deserializing unit and the data recovery unit, and the deserializing unit is connected with the data recovery unit; wherein,,

the input delay unit is used for carrying out phase delay on the received differential signals;

the clock management unit is used for generating a pair of clocks with the frequency of about half of the data transmission rate and the phase difference of 90 degrees as sampling clocks, and simultaneously generating the other two clocks with the frequency of half of the sampling clocks for data recovery;

the deserializing unit is used for carrying out oversampling processing on the HS signal data according to the sampling clock to obtain a preliminary sampling result;

the data recovery unit is used for carrying out edge detection on the preliminary sampling result to obtain an edge detection result, taking a sampling value far away from data jump from the edge detection result as an actual sampling result, and recovering the actual sampling result into a signal line level state sequence according to the data recovery clock.

Optionally, the input delay unit is further configured to divide the HS signal data into two paths, one path enters the deserializing unit through the input delay unit with 0 phase delay, and the other path enters the deserializing unit through the input delay unit with 45 ° phase delay.

Optionally, the performing edge detection on the preliminary sampling result to obtain an edge detection result, specifically: and performing exclusive OR operation on adjacent sampling values of the preliminary sampling result, finding a target position of at least one data jump in a channel, acquiring edge position information corresponding to the target position, and taking the edge position information as an edge detection result.

Optionally, the symbol decoding module is configured to transform and decode the signal line level state sequence into a symbol value according to a preset decoding manner specified in the C-PHY protocol.

Optionally, the serial-parallel conversion module is configured to splice the serial data sent by the symbol decoding module into parallel data in a 21-bit parallel data format according to serial 7 symbol values according to a synchronization word.

Optionally, the character demapping module is configured to map any 16bit data in the parallel data to a symbol value sequence composed of 7 serial symbol values, demap the symbol value sequence according to a mapping diagram of a C-PHY protocol, obtain actual data, and send the actual data to the HS data buffer for buffering.

Optionally, the control state machine is configured to obtain state information in the LP waveform sequence, and when the state information is a LP-to-HS jump sequence, open an HS data analysis function; and when the state information is the LP state data transmission sequence, starting an LP data analysis function.

In a second aspect, to achieve the above object, the present invention further provides a MIPI C-PHY signal receiving method, including the steps of:

receiving an LP signal in a C-PHY signal, calculating to obtain an LP clock, analyzing the LP signal according to the LP clock, analyzing to obtain an LP waveform sequence, judging the physical link state of a current channel according to the LP waveform sequence, switching LP and HS transmission modes and judging a stop state, and starting an LP data analysis function when the state information is an LP state data transmission sequence, analyzing to obtain LP data;

when the state information is the jump sequence from LP to HS, starting the HS data analysis function: and receiving a sampling result of the HS signal, carrying out edge detection on the sampling result to obtain an edge detection result, recovering the edge detection result into a signal line level state sequence, decoding the signal line level state sequence into a symbol value, finding a synchronous word from the symbol value, converting serial data into parallel data, and demapping the parallel data into actual data and storing the actual data.

In order to achieve the above object, the present invention further provides a camera module testing system including the MIPI C-PHY signal receiving apparatus, where the camera module testing system further includes: the system comprises a camera, a C-PHY receiving circuit, a CSI protocol analysis module and an upper computer; wherein,,

the camera is used for acquiring image data of a target object and transmitting the image data to the C-PHY receiving circuit through the MIPI C-PHY interface;

the C-PHY receiving circuit is used for separating an MIPI C-PHY signal into an LP signal and an HS signal and transmitting the LP signal and the HS signal to the MIPI C-PHY signal receiving device;

the CSI protocol analysis module is used for receiving the C-PHY data packet sent by the MIPI C-PHY signal receiving device, analyzing the C-PHY data packet according to the CSI protocol, obtaining image data of a complete frame, and caching and uploading the image data to the upper computer.

According to the MIPI C-PHY signal receiving method, an LP decoding module is used for receiving an LP signal in a C-PHY signal, an LP clock is obtained through operation, the LP signal is analyzed according to the LP clock, an LP waveform sequence is obtained through analysis, and the LP waveform sequence is sent to a control state machine; the control state machine judges the physical link state of the current channel according to the LP waveform sequence, and performs LP and HS transmission mode switching; the data recovery module receives a sampling result of the HS signal in an HS signal analysis mode, performs edge detection on the sampling result to obtain an edge detection result, and recovers the edge detection result into a signal line level state sequence; the symbol decoding module receives the signal line level state sequence sent by the data recovery module and decodes the signal line level state sequence into a symbol value; the serial-parallel conversion module receives the symbol value sent by the symbol decoding module, finds a synchronous word from the symbol value, and converts serial data into parallel data; the character demapping module receives the parallel data sent by the serial-parallel conversion module, demaps the parallel data into actual data, and sends the actual data to the HS data buffer for buffering, so that the functions of receiving and transmitting data of the C-PHY signal can be realized, a special C-PHY physical decoding device is not needed, the analysis time of the C-PHY signal is shortened, the data transmission cost is reduced, complex clock recovery logic is omitted, the data is directly recovered, the number of channels can be freely increased and decreased according to the actual application condition, the system flexibility is improved, and the data transmission rate and the transmission efficiency are improved.

Drawings

Fig. 1 is a functional block diagram of a first embodiment of an MIPI C-PHY signal receiver according to the invention;

fig. 2 is a schematic diagram of a system block diagram of a MIPI C-PHY signal reception method according to the invention;

fig. 3 is a schematic diagram of a data recovery module in the MIPI C-PHY signal receiving method according to the present invention;

fig. 4 is a schematic diagram of signal sampling in the MIPI C-PHY signal reception method of the present invention;

FIG. 5 is a schematic diagram of a camera module testing system according to the present invention;

fig. 6 is a flowchart illustrating a first embodiment of a MIPI C-PHY signal reception method according to the invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The solution of the embodiment of the invention mainly comprises the following steps: receiving an LP signal in a C-PHY signal through an LP decoding module, calculating to obtain an LP clock, analyzing the LP signal according to the LP clock, analyzing to obtain an LP waveform sequence, and transmitting the LP waveform sequence to a control state machine; the control state machine judges the physical link state of the current channel according to the LP waveform sequence, and performs LP and HS transmission mode switching; the data recovery module receives a sampling result of the HS signal in an HS signal analysis mode, performs edge detection on the sampling result to obtain an edge detection result, and recovers the edge detection result into a signal line level state sequence; the symbol decoding module receives the signal line level state sequence sent by the data recovery module and decodes the signal line level state sequence into a symbol value; the serial-parallel conversion module receives the symbol value sent by the symbol decoding module, finds a synchronous word from the symbol value, and converts serial data into parallel data; the character demapping module receives the parallel data sent by the serial-parallel conversion module, demaps the parallel data into actual data, and sends the actual data to the HS data buffer for buffering, so that the technical problems that in the prior art, the data receiving cannot perform self-defined setting on a bottom physical interface, the data transmission cost is high, and the transmission rate and the transmission efficiency are low are solved.

Fig. 1 is a functional block diagram of a first embodiment of an MIPI C-PHY signal receiving apparatus according to the invention.

In a first embodiment of the MIPI C-PHY signal receiving device of the invention, the MIPI C-PHY signal receiving device includes a LP section and a HS section, wherein,

the LP section includes an LP decoding module 10, a control state machine 20, and an LP data buffer 30; the HS part includes a data recovery module 40, a symbol decoding module 50, a serial-parallel conversion module 60, a character demapping module 70, and an HS data buffer 80; the LP section establishes contact with the HS section through the control state machine 20.

It should be noted that, the Channel limited-port Physical layer interface (C-PHY) signal receiving apparatus includes a Low Power mode (LP) portion and a High Speed mode (HS) portion, as shown in fig. 1, the LP portion includes an LP decoding module 10, a control state machine 20, and an LP data buffer 30, and the HS portion includes a data recovery module 40, a symbol decoding module 50, a serial-parallel conversion module 60, a character demapping module 70, and an HS data buffer 80; the LP section establishes contact with the HS section through the control state machine 20.

In a specific implementation, an external circuit of a field programmable gate array (Field Programmable Gate Array, FPGA) may separate a High Speed (HS) portion and a Low Power mode (LP) portion of a limited port Physical layer interface (Mobile Industry Processor Interface Channel-limited-Physical, MIPI C-PHY) signal of a mobile industrial processor, so as to obtain a corresponding LP signal and an HS signal, and after processing the HS signal, an input HS signal may be obtained, so that the input HS signal may be transmitted back to the FPGA.

It will be appreciated that the FPGA external circuit can separate the LP and HS portions of the C-PHY signal to obtain the LP and HS signals.

The LP decoding module 10 is configured to receive an LP signal in the C-PHY signal, calculate to obtain an LP clock, parse the LP signal according to the LP clock, parse to obtain an LP waveform sequence, and send the LP waveform sequence to a control state machine.

It should be appreciated that after receiving the LP signal in the C-PHY signal, the LP decoding module recovers the LP, and then parses the LP signal according to the LP clock to parse to obtain a corresponding LP waveform sequence.

The control state machine 20 is configured to receive the LP waveform sequence sent by the LP decoding module 10, determine a physical link state of a current channel according to the LP waveform sequence, switch between an LP and an HS transmission mode, parse the LP signal according to the physical link state, obtain LP parse data, transfer the LP parse data into the LP data buffer 30, and control parse enable of an HS signal in the C-PHY signal according to the physical link state.

It can be understood that the control state machine generally realizes LP and HS transmission mode switching by switching an LP transmission function and an HS transmission function, determines whether the control state is in a STOP state by judging the current state, and can also judge the physical link state of the current channel according to the LP waveform sequence to perform LP and HS transmission mode switching, so as to analyze the LP signal according to the physical link state to obtain LP analysis data, and transmit the LP analysis data to the LP data buffer, and control the analysis enable of the HS signal in the C-PHY signal according to the physical link state, that is, whether different link states correspondingly start the enable of the HS signal analysis function.

The data recovery module 40 is configured to receive a sampling result of the HS signal in the HS signal analysis mode, perform edge detection on the sampling result, obtain an edge detection result, and recover the edge detection result into a signal line level state sequence.

It should be understood that the LP portion and the HS portion are performed substantially synchronously, and the data recovery module may receive a sampling result of the HS signal in the HS signal analysis mode, perform edge detection on the sampling result to obtain a corresponding edge detection result, and further recover the edge detection result into a signal line level state sequence, and send the signal line level state sequence to the symbol decoding module.

The symbol decoding module 50 is configured to receive the signal line level state sequence sent by the data recovery module 40, and decode the signal line level state sequence into a symbol value.

It will be appreciated that after the symbol decoding module receives the signal line level state sequence, the signal line level state sequence may be decoded into symbol values, and the symbol values may be sent to the serial-to-parallel conversion module.

The serial-parallel conversion module 60 is configured to receive the symbol value sent by the symbol decoding module 50, find a synchronization word from the symbol value, and convert serial data into parallel data.

It should be appreciated that after the serial-to-parallel conversion module receives the symbol values, a synchronization word may be found from the symbol values and serial data may be format converted to parallel data while the parallel data is sent to the character demapping module.

The character demapping module 70 is configured to receive the parallel data sent by the serial-parallel conversion module, demap the parallel data into actual data, and send the actual data to the HS data buffer 80 for buffering.

It can be understood that after the character demapping module receives the parallel data, the parallel data is demapped into actual data, and then the actual data is transferred into an HS data buffer for buffering.

In specific implementation, referring to fig. 2, fig. 2 is a schematic diagram of a system block diagram of the MIPI C-PHY signal receiving method of the present invention, as shown in fig. 2, an external circuit of the FPGA separates LP and HS parts of the C-PHY signal, and converts the HS signal of each channel into a form of a-B, B-C, C-a, which is transmitted to the FPGA.

The FPGA uses an embedded memory/phase-locked loop to generate a plurality of clocks for signal sampling, recovery and data analysis; the method comprises the steps that a deserializing unit in the FPGA samples an input HS signal in an oversampling mode by using a generated clock; the sampling result enters a data recovery module to carry out edge detection, and a transmitted signal line level state sequence is recovered according to the edge detection result; the symbol decoding module decodes the signal line level state sequence into a symbol value; the serial-parallel conversion module finds out a synchronous word from the symbol value sequence and converts serial data into parallel data; the character demapping module demaps the parallel data into actual data and transmits the actual data into the data caching unit for caching.

The LP decoding module receives the LP signal separated by the circuit, calculates to obtain an LP clock, and analyzes to obtain an LP waveform sequence; and the control state machine module judges the state of the current lane according to the LP waveform sequence and analyzes the LP data.

The C-PHY signal is divided into two parts, one part is LP and the other part is HS; the LP signal contains two types of information, one type is state information, which is used to represent the current CPHY channel state, and the corresponding function needs to be started according to the control information; for example, when the LP signal analyzes the jump sequence from LP to HS, it indicates that the current channel will start HS data transmission, and at this time, the HS data analysis function needs to be started; when the LP signal is analyzed to obtain an LP state data transmission sequence, the current channel is indicated to start LP data transmission, and the LP data analysis function is required to be started at this time; the other type of LP signals are LP data, when the LP state data transmission function is started, the LP data is needed to be obtained through analysis, the local sampling clock is not required to be completely consistent with the data transmission rate, a certain range of deviation is allowed, and the analysis result is not influenced.

The HS signal contains only image data; the HS signal obtains the data actually transmitted after sampling, edge detection, data recovery and decoding, and the obtained data is a data packet of the C-PHY; the complete frame of image data can be subsequently parsed from the data packet.

Only the status information in the LP signal, which indicates the type of data to be transmitted next, is correlated between the LP signal and the HS signal; LP data parsing and HS data parsing are two different functions, which do not work simultaneously, nor do they have direct data interaction.

Further, the data recovery module 40 includes an input delay unit, a clock management unit, a deserializing unit, and a data recovery unit; the input delay unit is connected with the deserializing unit, the clock management unit is respectively connected with the deserializing unit and the data recovery unit, and the deserializing unit is connected with the data recovery unit; wherein,,

the input delay unit is used for carrying out phase delay on the received differential signals;

the clock management unit is used for generating a pair of clocks with the frequency of about half of the data transmission rate and the phase difference of 90 degrees as sampling clocks, and simultaneously generating the other two clocks with the frequency of half of the sampling clocks for data recovery;

the deserializing unit is used for carrying out oversampling processing on the HS signal data according to the sampling clock to obtain a preliminary sampling result;

the data recovery unit is used for carrying out edge detection on the preliminary sampling result to obtain an edge detection result, taking a sampling value far away from data jump from the edge detection result as an actual sampling result, and recovering the actual sampling result into a signal line level state sequence according to the data recovery clock.

It should be noted that, the input HS signal may be sampled in the oversampling mode by using the generated clock by the deserializing unit in the FPGA, and the edge detection is performed after the sampling, to obtain the edge detection result.

It can be understood that the input HS signal is sampled by a deserializing unit in the FPGA using a clock, so as to obtain a sampling result of the HS signal.

It should be understood that the sampling result enters the data recovery module, and edge detection can be performed to obtain a corresponding edge detection result.

It should be understood that the data recovery module uses the over-sampling principle, uses the input delay and deserializing unit devices in the FPGA to realize the three-wire C-PHY HS signal sampling function for each lane, and comprehensively judges according to the three-wire edge signal, so as to recover the data.

Further, the performing edge detection on the preliminary sampling result to obtain an edge detection result specifically includes: and performing exclusive OR operation on adjacent sampling values of the preliminary sampling result, finding a target position of at least one data jump in a channel, acquiring edge position information corresponding to the target position, and taking the edge position information as an edge detection result.

The sampling result is input to a data recovery module, the data recovery module performs exclusive or operation on adjacent sampling values in the sampling result to find a position where data jump occurs, and edge position information corresponding to the position is obtained and is used as an edge detection result.

It can be understood that the general sampling result is transmitted to the data recovery unit for processing, the position where the data jump occurs is found by performing exclusive or operation on two adjacent sampling values, the edge position information corresponding to the position is obtained, and the edge position information is used as an edge detection result.

In a specific implementation, the number of channel lanes for receiving the C-PHY signal can be freely increased and reduced according to own requirements, so that the flexibility of the system is improved.

Furthermore, the input delay unit is further configured to divide the HS signal data into two paths, one path enters the deserializing unit through the input delay unit with 0 phase delay, and the other path enters the deserializing unit through the input delay unit with 45 ° phase delay.

In a specific implementation, the data recovery module can utilize a sampling principle, realize a three-wire C-PHY HS signal sampling function of each channel by using an input delay deserializing unit, and comprehensively judge according to three-wire edge signals so as to recover data; the data recovery module is shown in fig. 3, and fig. 3 is a schematic diagram of a data recovery module in the MIPI C-PHY signal receiving method according to the present invention, referring to fig. 3, where the clock management unit generates a pair of clocks with frequencies about half of the data transmission rate and phase difference of 90 ° as sampling clocks, and simultaneously generates two other clocks with frequencies about half of the sampling clocks for data recovery, where each HS signal input is divided into two paths for processing, and one path passes through an input delay module with 0 phase delay and enters the deserializing unit for oversampling processing; the other path of the sampling result is input into the deserializing unit for oversampling through the input delay module with 45-degree phase delay, and the sampling result of 4 times in one bit period can be obtained through the two paths of processing.

Correspondingly, a signal sampling schematic diagram is shown in fig. 4, fig. 4 is a signal sampling schematic diagram in the MIPI C-PHY signal receiving method of the present invention, four sampling results A, B, C, D are obtained in the diagram, and the sampling results are transmitted to a data recovery unit for processing; finding the position of the data jump by performing exclusive OR operation on two adjacent sampling values; because at least one of the three inputs A-B, B-C, C-A of each channel of the MIPI C-PHY jumps in each symbol, the edge information of the three inputs needs to be comprehensively processed at the same time, and further more accurate edge position information is obtained; according to the edge detection result, sampling values far away from data jump are taken as actual sampling results to be output; by utilizing the characteristic that one jump is needed to occur in A-B, B-C, C-A between adjacent line states of the C-PHY signal, and combining the over-sampling principle, complex clock recovery logic is omitted, and data can be recovered directly.

Further, the symbol decoding module is configured to transform and decode the signal line level state sequence into a symbol value according to a preset decoding manner specified in the C-PHY protocol.

It should be noted that, after the edge detection result is obtained, the transmitted signal line level state sequence can be recovered according to the edge detection result, the symbol decoding module can decode the signal line level state sequence into a symbol value sequence, and the characteristic that one of the adjacent line states of the C-PHY signal is needed to jump is utilized, and the complex clock recovery logic is omitted in combination with the oversampling principle to directly recover the data.

In a specific implementation, the symbol decoding module may convert the line state value recovered by the data recovery module into a symbol value according to a decoding manner specified in the C-PHY protocol.

Further, the serial-parallel conversion module is configured to splice the serial data sent by the symbol decoding module into parallel data in a 21-bit parallel data format according to serial 7 symbol values according to a synchronization word.

It should be understood that the serial-parallel conversion module can splice the subsequent data, i.e. the time data to be converted, into a format of 21bit parallel data according to 7 serial symbol values continuously according to the synchronous word to complete the serial-parallel conversion function.

Further, the character demapping module is configured to map any 16bit data in the parallel data to a symbol value sequence composed of 7 serial symbol values, demap the symbol value sequence according to a mapping diagram of a C-PHY protocol, obtain actual data, and send the actual data to the HS data buffer for buffering.

In a specific implementation, a mapping manner of actual data and symbol values is specified in the C-PHY protocol, and any 16-bit data can be mapped into a sequence consisting of 7 symbol values. And according to the mapping diagram of the C-PHY protocol, the demapping of the symbol value sequence can be completed, and the data actually transmitted are obtained.

Further, the control state machine is configured to obtain state information in the LP waveform sequence, and when the state information is a LP-to-HS jump sequence, open an HS data analysis function; and when the state information is the LP state data transmission sequence, starting an LP data analysis function.

The C-PHY signal is divided into two parts, one part is LP and the other part is HS; the LP signal contains two types of information, one type is state information, which is used to represent the current CPHY channel state, and the corresponding function needs to be started according to the control information; for example, when the LP signal analyzes the jump sequence from LP to HS, it indicates that the current channel will start HS data transmission, and at this time, the HS data analysis function needs to be started; when the LP signal is analyzed to obtain an LP state data transmission sequence, the current channel is indicated to start LP data transmission, and the LP data analysis function is required to be started at this time; the other type of LP signals are LP data, and when the LP state data transmission function is started, the LP data are needed to be analyzed and obtained; the C-PHY protocol does not specify the specific content of the LP data, and therefore needs to perform corresponding processing according to the actual situation of the transmitting end.

The HS signal contains only image data; the HS signal is sampled, edge detected, data recovered, decoded to obtain the data actually transmitted, and the data obtained at this time is the data packet of the C-PHY.

Only the status information in the LP signal, which indicates the type of data to be transmitted next, is correlated between the LP signal and the HS signal; LP data parsing and HS data parsing are two different functions, which do not work simultaneously, nor do they have direct data interaction.

In a specific implementation, the control state machine module analyzes the LP sequence to obtain a physical link state, and achieves functions of switching between LP and HS transmission modes, judging a STOP state, transmitting LP mode data and the like.

Based on the MIPI C-PHY signal receiving apparatus, a camera module testing system including the MIPI C-PHY signal receiving apparatus is provided, as shown in fig. 5, fig. 5 is a schematic diagram of the camera module testing system of the present invention, and referring to fig. 5, the camera module testing system includes a camera 90, a C-PHY receiving circuit 100, a CSI protocol parsing module 110, and an upper computer 120; wherein,,

the camera 90 is configured to acquire image data of a target object, and send the image data to the C-PHY receiving circuit 100 through an MIPI C-PHY interface;

the C-PHY receiving circuit 100 is configured to separate an MIPI C-PHY signal into an LP signal and an HS signal, and send the LP signal and the HS signal to the MIPI C-PHY signal receiving apparatus;

the CSI protocol parsing module 110 is configured to receive the C-PHY packet sent by the MIPI C-PHY signal receiving apparatus, parse the C-PHY packet according to the CSI protocol, obtain image data of a complete frame, and cache and upload the image data to the upper computer 120.

The C-PHY data packet is a data packet generated according to the LP signal analysis data and the HS signal analysis data sent by the MIPI C-PHY signal receiving device,

in a specific implementation, a C-PHY RX circuit separates an HS signal from an LP signal, the separated LP signal and the HS signal in a MIPI C-PHY RX system receiving circuit are processed to obtain a data packet which accords with a camera serial interface (Camera Serial Interface, CSI) protocol and the data packet is transmitted to a CSI protocol analysis module; the CSI protocol parsing module parses the image data from the data packet, and then transmits the image data to the upper computer, which is generally a PC terminal, through buffering and uploading, although other upper terminals may also be used, which is not limited in this embodiment.

The actual number of the C-PHY interface channels of cameras in the current market is different, and the actual number of the actually used cameras can be adjusted according to actual requirements, so that the actual number of the cameras needs to be flexibly adjusted to adapt to different cameras.

Referring to fig. 6, fig. 6 is a flowchart illustrating a first embodiment of the MIPI C-PHY signal reception method according to the invention.

In a first embodiment, the MIPI C-PHY signal receiving method includes the steps of:

and S10, receiving an LP signal in a C-PHY signal, calculating to obtain an LP clock, analyzing the LP signal according to the LP clock, analyzing to obtain an LP waveform sequence, judging the physical link state of a current channel according to the LP waveform sequence, switching LP and HS transmission modes, judging a stop state, and starting an LP data analysis function when the state information is an LP state data transmission sequence, analyzing to obtain LP data.

Step S20, when the state information is the jump sequence from LP to HS, starting the HS data analysis function: and receiving a sampling result of the HS signal, carrying out edge detection on the sampling result to obtain an edge detection result, recovering the edge detection result into a signal line level state sequence, decoding the signal line level state sequence into a symbol value, finding a synchronous word from the symbol value, converting serial data into parallel data, and demapping the parallel data into actual data and storing the actual data.

The steps of the C-PHY signal parsing method may refer to the embodiments of the functional modules of the MIPI C-PHY signal receiving apparatus of the present invention, and are not described herein.

According to the scheme, through receiving the LP signals in the C-PHY signals, calculating to obtain the LP clock, analyzing the LP signals according to the LP clock to obtain the LP waveform sequence, judging the physical link state of the current channel according to the LP waveform sequence, switching the LP and HS transmission modes and judging the stop state, and when the state information is the LP state data transmission sequence, starting the LP data analysis function to analyze to obtain the LP data; when the state information is the jump sequence from LP to HS, starting the HS data analysis function: the sampling result of the HS signal is received, edge detection is carried out on the sampling result, the edge detection result is obtained, the edge detection result is restored to a signal line level state sequence, the signal line level state sequence is decoded to a symbol value, a synchronous word is found from the symbol value, serial data is converted to parallel data, the parallel data is demapped to actual data and stored, the functions of receiving and restoring transmission data of a C-PHY signal can be achieved, a special C-PHY physical decoding device is not needed, the analysis time of the C-PHY signal is shortened, the data transmission cost is reduced, complex clock restoration logic is omitted, the number of channels can be freely increased and decreased according to actual application conditions, the system flexibility is improved, and the data transmission rate and the data transmission efficiency are improved.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (9)

1. An MIPI C-PHY signal receiving device, characterized in that the MIPI C-PHY signal receiving device comprises an LP section and an HS section, wherein,

the LP section includes a LP decoding module, a control state machine, and a LP data buffer; the HS part comprises a data recovery module, a symbol decoding module, a serial-parallel conversion module, a character demapping module and an HS data buffer; the LP section establishing contact with the HS section through the control state machine;

the LP decoding module is used for receiving the LP signals in the C-PHY signals, calculating to obtain an LP clock, analyzing the LP signals according to the LP clock, analyzing to obtain an LP waveform sequence, and sending the LP waveform sequence to a control state machine;

the control state machine is used for judging the physical link state of the current channel according to the LP waveform sequence and switching the LP and HS transmission modes;

the data recovery module is used for receiving the sampling result of the HS signal under the HS signal analysis mode, carrying out edge detection on the sampling result to obtain an edge detection result, and recovering the edge detection result into a signal line level state sequence;

the symbol decoding module is used for receiving the signal line level state sequence sent by the data recovery module and decoding the signal line level state sequence into a symbol value;

the serial-parallel conversion module is used for receiving the symbol value sent by the symbol decoding module, finding a synchronous word from the symbol value and converting serial data into parallel data;

the character demapping module is used for receiving the parallel data sent by the serial-parallel conversion module, demapping the parallel data into actual data, and sending the actual data to the HS data buffer for caching;

the data recovery module comprises an input delay unit, a clock management unit, a deserializing unit and a data recovery unit; the input delay unit is connected with the deserializing unit, the clock management unit is respectively connected with the deserializing unit and the data recovery unit, and the deserializing unit is connected with the data recovery unit; wherein,,

the input delay unit is used for carrying out phase delay on the received differential signals;

the clock management unit is used for generating a pair of clocks with half frequency of data transmission rate and 90-degree phase difference as sampling clocks, and simultaneously generating the other two clocks with half frequency of the sampling clocks for data recovery;

the deserializing unit is used for carrying out oversampling processing on the HS signal data according to the sampling clock to obtain a preliminary sampling result;

the data recovery unit is used for carrying out edge detection on the preliminary sampling result to obtain an edge detection result, taking a sampling value far away from data jump from the edge detection result as an actual sampling result, and recovering the actual sampling result into a signal line level state sequence according to the data recovery clock.

2. The MIPI C-PHY signal receiver of claim 1, wherein the input delay element is further configured to split the HS signal data into two paths, one path through the input delay element with a 0-phase delay, into the deserializing element, and the other path through the input delay element with a 45-phase delay, into the deserializing element.

3. The MIPI C-PHY signal receiver of claim 1, wherein the performing edge detection on the preliminary sampling result to obtain an edge detection result comprises: and performing exclusive OR operation on adjacent sampling values of the preliminary sampling result, finding a target position of at least one data jump in a channel, acquiring edge position information corresponding to the target position, and taking the edge position information as an edge detection result.

4. The MIPI C-PHY signal receiver of claim 1, wherein the symbol decoding module is configured to transform and decode the sequence of signal line level states into symbol values in accordance with a preset decoding scheme specified in the C-PHY protocol.

5. The MIPI C-PHY signal receiver of claim 1, wherein the serial-to-parallel conversion module is configured to concatenate serial data transmitted by the symbol-decoding module into parallel data in a 21-bit parallel data format according to consecutive 7 serial of the symbol values based on a synchronization word.

6. The MIPI C-PHY signal reception apparatus of claim 1, wherein the character demapping module is configured to map any one 16-bit data of the parallel data into a symbol value sequence consisting of 7 serial symbol values, demap the symbol value sequence according to a map of a C-PHY protocol to obtain actual data, and send the actual data to the HS data buffer for buffering.

7. The MIPI C-PHY signal receiver apparatus of claim 1, wherein the control state machine is configured to obtain state information in the LP waveform sequence, and to turn on an HS data parsing function when the state information is a LP-to-HS jump sequence; and when the state information is the LP state data transmission sequence, starting an LP data analysis function.

8. A MIPI C-PHY signal reception method, the MIPI C-PHY signal reception method comprising:

receiving an LP signal in a C-PHY signal, calculating to obtain an LP clock, analyzing the LP signal according to the LP clock, analyzing to obtain an LP waveform sequence, judging the physical link state of a current channel according to the LP waveform sequence, switching LP and HS transmission modes and judging a stop state, and starting an LP data analysis function when state information is an LP state data transmission sequence, analyzing to obtain LP data;

when the state information is the jump sequence from LP to HS, starting the HS data analysis function: receiving a sampling result of the HS signal, carrying out edge detection on the sampling result to obtain an edge detection result, recovering the edge detection result into a signal line level state sequence, decoding the signal line level state sequence into a symbol value, finding a synchronous word from the symbol value, converting serial data into parallel data, de-mapping the parallel data into actual data and storing the actual data;

performing phase delay on the received differential signal; generating a pair of clocks with half frequency of data transmission rate and 90-degree phase difference as sampling clocks, and simultaneously generating the other two clocks with half frequency of the sampling clocks for data recovery; performing oversampling processing on the HS signal data according to the sampling clock to obtain a preliminary sampling result; and carrying out edge detection on the preliminary sampling result to obtain an edge detection result, taking a sampling value far away from data jump from the edge detection result as an actual sampling result, and recovering the actual sampling result into a signal line level state sequence according to the data recovery clock.

9. A camera module testing system comprising the MIPI C-PHY signal receiver of claim 1, wherein the camera module testing system further comprises: the system comprises a camera, a C-PHY receiving circuit, a CSI protocol analysis module and an upper computer; wherein,,

the camera is used for acquiring image data of a target object and transmitting the image data to the C-PHY receiving circuit through the MIPI C-PHY interface;

the C-PHY receiving circuit is used for separating an MIPI C-PHY signal into an LP signal and an HS signal and transmitting the LP signal and the HS signal to the MIPI C-PHY signal receiving device;

the CSI protocol analysis module is used for receiving the C-PHY data packet sent by the MIPI C-PHY signal receiving device, analyzing the C-PHY data packet according to a CSI protocol, obtaining image data of a complete frame, and caching and uploading the image data to the upper computer;

the data recovery module in the MIPI C-PHY signal receiving device comprises an input delay unit, a clock management unit, a deserializing unit and a data recovery unit; the input delay unit is connected with the deserializing unit, the clock management unit is respectively connected with the deserializing unit and the data recovery unit, and the deserializing unit is connected with the data recovery unit; wherein,,

the input delay unit is used for carrying out phase delay on the received differential signals;

the clock management unit is used for generating a pair of clocks with half frequency of data transmission rate and 90-degree phase difference as sampling clocks, and simultaneously generating the other two clocks with half frequency of the sampling clocks for data recovery;

the deserializing unit is used for carrying out oversampling processing on the HS signal data according to the sampling clock to obtain a preliminary sampling result;

the data recovery unit is used for carrying out edge detection on the preliminary sampling result to obtain an edge detection result, taking a sampling value far away from data jump from the edge detection result as an actual sampling result, and recovering the actual sampling result into a signal line level state sequence according to the data recovery clock.