CN1581126A

CN1581126A - IIC bus control system and method for realizing same

Info

Publication number: CN1581126A
Application number: CN 03142276
Authority: CN
Inventors: 王世航; 房晏先
Original assignee: YIYUAN INTELLIGENT SCIENCE-TECHNOLOGY Co Ltd SHANGHAI
Current assignee: YIYUAN INTELLIGENT SCIENCE-TECHNOLOGY Co Ltd SHANGHAI
Priority date: 2003-08-15
Filing date: 2003-08-15
Publication date: 2005-02-16

Abstract

The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. When the bus is stand-by, the clock line and data line are set in high level, and when the chip microprocessor to be used for transmitting data is used to transmit the data, it is ste in low clock line, the receiving chip microprocessor can instantly produce interruption, and the receiving chip microprocessor uses the inverse first data line to receive the readiness answer signal, and transfer it into the chip microprocessor to be used for transmitting data, and said chip microprocessor can transmit serial data on the data line. It adopts same clock source, and its time sequence is synchronous, so that it does not produce time delay problem.

Description

Iic bus control system and its implementation

Invention field:

Multimachine serial expansion technique between the relevant single-chip microcomputer of the present invention refers in particular to the iic bus control system and its implementation in a shared clock source between a kind of multiple single chip microcomputer.

Background of invention:

In contemporary electronic systems, have numerous IC to carry out each other and with the communicating by letter of the external world.Each device all has a unique address, and can be single device that receives (for example: lcd driver) or (for example: storer) can receive the device that also can send.Transmitter or receiver can be operated in holotype or under pattern, and this transmission of depending on that chip whether must log-on data still only is addressed.For efficient that hardware is provided and the design of simplifying circuit, PHILIPS has developed a kind of simple two-way two-wire serial bus IIC that is used for inner IC control.Iic bus is supported any IC manufacturing process, and PHILIPS provides the profuse IIC of kind compatible chip with other manufacturers.As the control bus of a patent, the I2C industrial standard that become international.

Iic bus is a kind of simple, two-way, two-wire system, synchronous serial bus.Its only need two lines (serial time clock line SCL and serial data line SDA) can be between the device that is connected on the bus transmission information.This general line is a high performance serial bus, and possessing the required I2C of multi-host system is a multi-master bus, and promptly it can be by the device control of a plurality of connections.

Secondary data between the iic bus principal and subordinate machine transmits and is called a frame, is made up of enabling signal, address code, plurality of data byte, response bits and stop signal etc.When communication starts, initiatively send the address code (8) and the read-write of an enabling signal (when being high level on the scl line, producing a negative edge on the sda line), slave; When communication stopped, main frame sent a stop signal (when being high level on the scl line, producing a rising edge on the sda line).In data transfer procedure, when being high level on the scl line, must guarantee the data stabilization on the sda line; Transmit the data of a byte, must send out an answer signal by receiver.

Though special I IC Bus Interface Chip is arranged in the market, the optional scope in address is little, performance index are fixed, function singleness, use inconvenience.Electrical specification and communications protocol thereof according to iic bus, the FLEX10K series ISP device EPF10K10LC84-3 of employing ALTERA company can realize the communication interface of iic bus easily, and have at a high speed, easily debugging, can realize advantage such as ground Configuration Online neatly, reduced the construction cycle of system simultaneously widely.

The iic bus connected mode is because its superior performance, configuration mode has obtained in market to use very widely flexibly, it has realized the full duplex synchronous data transmission with two lines, can constitute multi-computer system and peripheral components expanding system easily by the utmost point, its outstanding feature is a hardware circuit to greatest extent, has saved Single Chip Microcomputer (SCM) system limited hardware resource.Chinese patent application 99816805.X has promptly disclosed a kind of system that adopts iic bus to connect.

Yet, the single-chip microcomputer that is generally using does not have integrated iic bus interface at present, and the asynchronous sequential of iic bus that determined of the physics of each device and work clock must farthest satisfy certain delay time, will inevitably reduce transmission speed like this.

Summary of the invention:

The present invention is exactly in order to overcome the deficiency of prior art, and a kind of iic bus control system is provided, thereby realizes that the sequential between single-chip microcomputer is synchronous.

The object of the present invention is achieved like this: the iic bus control system comprises at least two single-chip microcomputers and two lines that are connected with each single-chip microcomputer, one links to each other with the one-chip machine port position in two lines is the data line of bus, what link to each other with the exterior interrupt of single-chip microcomputer is the clock line of bus, and it is characterized in that: described iic bus control system further comprises the same clock source circuit that is connected by an interface with a plurality of single-chip microcomputers.

A kind of implementation method of iic bus control system, it comprises at least two single-chip microcomputers and two lines that are connected with each single-chip microcomputer, one links to each other with the one-chip machine port position in two lines is the data line of bus, what link to each other with the exterior interrupt of single-chip microcomputer is the clock line of bus, also comprise the clock source circuit that is connected with each single-chip microcomputer by an interface, implementation step is:

The first step, clock line and data line are set to high level when bus is standby;

In second step, the single-chip microcomputer that send data is put low clock line when sending data, simultaneously, receives single-chip microcomputer and interrupts at once;

The 3rd step will receive data line of single-chip microcomputer negate as accepting ready answer signal, reached the single-chip microcomputer that will send data;

In the 4th step, the single-chip microcomputer that send data sends serial data to receiving single-chip microcomputer on data line.

Because shared same clock source circuit between multiple single chip microcomputer of the present invention, so sequential is synchronous, promptly the saltus step of the port lines of two single-chip microcomputers is synchronous.Thereby improved communication speed, the advantage of clock synchronization and the rapid reaction of interruption have been made full use of, in whole communication process, need not consider uncertain delay operation, thereby the interface resource of single-chip microcomputer preciousness has improved serial rate again to greatest extent, make two MCU systems can hight coordinate ground is consistent work, become an organic whole.

In conjunction with can more being expressly understood essence of the present invention after the following drawings and Examples.

Brief description of drawingsfig:

Fig. 1 is an iic bus control system block diagram of the present invention.

Fig. 2 is that process flow diagram is interrupted in the reception of iic bus control system of the present invention.

Preferred embodiment

As shown in Figure 1, the iic bus control system comprises two single-chip microcomputers, be MCS-51, one of them is the first single-chip microcomputer, and one is the second single-chip microcomputer, be connected with two lines between two single-chip microcomputers, wherein one links to each other with the port position (P1.0) of single-chip microcomputer, is defined as the data line (SDA) of bus, and one is connected with the exterior interrupt (INT0) of single-chip microcomputer, be defined as clock line (SCL), two single-chip microcomputers all are connected with an interface in same clock source by an interface.

Consult Figure 1 and Figure 2, the step when carrying out data transmission between two single-chip microcomputers is:

The first step, bus must keep high level when bus is standby;

Second step, when will sending data, puts by the first single-chip microcomputer low clock line (SCL) earlier, and Party B's single-chip microcomputer can interrupt at once;

In the 3rd step, a data line of negate (SDA) is as accepting ready answer signal in interruption subroutine;

In the 4th step, the Party A obtains going up to second single-chip microcomputer transmission serial data at data line (SDA) at once behind the answer signal.

Because the public same clock of double mcu source, so sequential is synchronous, promptly the saltus step of the port lines of two single-chip microcomputers is synchronous, a clock line of every negate (SCL) sends 1 bit in process of transmitting, (example: MOV P1.0, a data line (SDA) (example: MOV C had once both been read in the every saltus step of clock line (SCL) when C) receiving, P1.0), need not consider latency issue, as seen, clock frequency high transfer rate more is fast more.

Claims

1, a kind of iic bus control system, it comprises at least two single-chip microcomputers and two lines that are connected with each single-chip microcomputer, one links to each other with the one-chip machine port position in two lines is the data line of bus, what link to each other with the exterior interrupt of single-chip microcomputer is the clock line of bus, and it is characterized in that: described iic bus control system further comprises the same clock source circuit that is connected by an interface with a plurality of single-chip microcomputers.

2, a kind of implementation method of iic bus control system, it comprises at least two single-chip microcomputers and two lines that are connected with each single-chip microcomputer, one links to each other with the one-chip machine port position in two lines is the data line of bus, what link to each other with the exterior interrupt of single-chip microcomputer is the clock line of bus, also comprise the clock source circuit that is connected with each single-chip microcomputer by an interface, implementation step is:

3, the implementation method of iic bus control system as claimed in claim 2 wherein promptly sends 1 bit as answer signal at the data line of the every negate of single-chip microcomputer that receives data.

4, the implementation method of iic bus control system as claimed in claim 3, data line is once read in the every saltus step of clock line when wherein receiving (SCL) one time.