CN109582616B

CN109582616B - Communication system and method based on serial bus

Info

Publication number: CN109582616B
Application number: CN201811480633.1A
Authority: CN
Inventors: 张洋; 张虎
Original assignee: Beijing Aiqi Technology Co ltd
Current assignee: BEIJING AIQI TECHNOLOGY CO., LTD.
Priority date: 2018-12-05
Filing date: 2018-12-05
Publication date: 2020-07-17
Anticipated expiration: 2038-12-05
Also published as: CN109582616A

Abstract

A communication system based on serial bus is prepared as using serial bus to hold serial bus and sending byte DATA byte by byte according to preset time interval when serial bus is idle, releasing serial bus and starting up bus interrupt mechanism after all byte DATA are sent out, triggering bus interrupt by receiving end and receiving 8 bit DATA in byte DATA byte by byte after bus is confirmed to be occupied, then releasing serial bus and starting up bus interrupt mechanism to process other task.

Description

Communication system and method based on serial bus

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a serial bus based communication system and method.

Background

Currently, a common bus mainly includes an SPI (Serial Peripheral Interface) bus and an IIC (Inter-Integrated Circuit) bus, where communication based on the SPI bus is limited to a master-slave mode, and an additional slave device needs to be provided with a CS signal line, so that expansion is limited. The communication based on the IIC bus is also limited to a master-slave mode, and the slave device actively transmits data to the master device only after receiving a read command transmitted by the master device. There is a lack of a serial bus that does not distinguish between master-slave, half-duplex, and synchronous.

Disclosure of Invention

The present application aims to provide a communication system and method based on a serial bus to solve the technical problems mentioned in the above background.

According to a first aspect, the present application provides a communication system based on a serial bus, the system comprising a transmitting end, a receiving end and a serial bus, wherein the serial bus comprises three signal lines of a BUSY line, a DATA line and a C L K line, the three signal lines all have a high priority of low level, the BUSY pin, the DATA pin and the C L K pin of the transmitting end and the receiving end are respectively connected to the BUSY line, the DATA line and the C L K line of the serial bus, characterized in that the transmitting end is turned off a bus interrupt mechanism, the state of the serial bus is determined to be idle according to the read levels on the BUSY line and the C L K line, when the state of the serial bus is idle, byte DATA is transmitted byte by byte at preset time intervals, after transmission of all byte DATA is completed, the serial bus is released, the bus interrupt mechanism is turned on, wherein the flow of transmitting each byte DATA is that the BUSY pin is controlled to output low level, namely, the low level is set, when it is determined that DATA is high level, that DATA is DATA has been processed, the DATA is set to high level, the DATA pin is set to be high level, the DATA pin is detected, the DATA pin is returned to be read, the high level, the serial bus pin is returned to the high level, the serial bus interrupt mechanism is triggered, the serial bus interrupt mechanism is started to be read, and the serial bus interrupt level, the serial bus interrupt level when the serial bus interrupt level is detected, the serial bus is returned to be read, the high byte DATA, the serial bus pin, the serial bus is returned to be read, the serial bus is returned to be sent to be a high byte level, the.

In some embodiments, the sending end judges whether the state of the serial bus is idle according to the read levels on the BUSY line and the C L K line, the method includes continuously reading the levels on the BUSY line and the C L K line in a preset time until the levels on the BUSY line and the C L K line are both high levels, namely judging that the state of the serial bus is idle, if the preset time is exceeded, judging that the state of the serial bus is occupied, controlling a BUSY pin to output a low level and randomly delaying for a period of time after the state of the serial bus is judged to be idle, controlling the BUSY pin to output a high level, continuously reading the levels on the BUSY line and the C L K line again in the preset time until the levels on the BUSY line and the C L K line are both high levels, and finally judging that the state of the serial bus is idle, otherwise judging that the state of the serial bus is occupied.

In some embodiments, the transmitting end transmits byte data byte by byte at preset time intervals, including: the sending end repeatedly executes the following steps until all byte data are sent completely: and sending one byte of data, judging whether all the byte of data are sent completely, and delaying the time interval if not.

In some embodiments, the specific process of respectively transmitting and receiving a bit of DATA by a transmitting end and a receiving end is that the transmitting end controls a DATA pin to output bit DATA of 1 or 0 by using a high level and a low level, and simultaneously controls a C L K pin to output a low level of 25 microseconds, namely, the level on a C L K line is set to be a low level from the high level, the receiving end continuously detects whether the level on a C L K line is a low level within a preset time, and if the level is a low level, the C L K pin is controlled to output a low level of 25 microseconds, and simultaneously reads the bit DATA on the DATA line, and after 25 microseconds, the receiving end controls a C L K pin to output a high level as a response, the transmitting end controls a C L K pin to output a high level, and continuously reads the level on a C L K line within a preset time and judges whether the level is a high level, namely, whether all the receiving ends have responded, and if the level is a high level, the receiving end further judges whether the level of 8 bit of DATA is completely transmitted, and the receiving end continuously reads the level on the C L K line and judges whether the level is a high level, and further receives the 8 bit of the DATA.

In some embodiments, whether the sending terminal or the receiving terminal, the releasing serial bus controls the BUSY pin to output high level, controls the C L K pin to output high level, and controls the DATA pin to output low level.

The second aspect of the invention provides a communication method based on a serial bus, which comprises the steps of closing a bus interrupt mechanism, judging whether the state of the serial bus is idle or not according to the read levels on a BUSY line and a C L K line, and transmitting byte DATA byte by byte according to a preset time interval when the state of the serial bus is idle, wherein the process of transmitting each byte DATA comprises the steps of controlling a BUSY pin to output a low level, namely setting the BUSY from a high level to a low level, transmitting bit DATA in the byte by DATA bit at a falling edge of C L K after determining that the DATA is the high level, ensuring that a response signal that the C L K returned by a receiving end is the high level is received when transmitting the next bit DATA, controlling the DATA pin to output the high level, controlling the C L K pin to output the low level and the BUSY pin to output the high level when judging that unsent byte DATA exist after transmitting each byte DATA, releasing the serial bus interrupt mechanism and opening the bus interrupt mechanism after transmitting all byte DATA.

In some embodiments, the determining whether the state of the serial bus is idle according to the read levels on the BUSY line and the C L K line includes continuously reading the levels on the BUSY line and the C L K line within a preset time until the levels on the BUSY line and the C L K line are both high levels, that is, determining that the state of the serial bus is idle, and if the preset time is exceeded, determining that the state of the serial bus is occupied, controlling the BUSY pin to output a low level, delaying randomly for a period of time, controlling the BUSY pin to output a high level, continuously reading the levels on the BUSY line and the C L K line again within the preset time until the levels on the BUSY line and the C L K line are both high levels, and finally determining that the state of the serial bus is idle, otherwise determining that the state of the serial bus is occupied.

In some embodiments, the sending byte data byte by byte at preset time intervals includes: the following steps are repeatedly executed until all byte data are sent completely: and sending one byte of data, judging whether all the byte of data are sent completely, and delaying the time interval if not.

The third aspect of the invention provides a serial bus-based communication method which comprises the steps of monitoring the level on a BUSY line in real time, triggering bus interruption and suspending processing of other tasks when the fact that the level on the BUSY line is changed from high level to low level is detected, setting DATA to be high level as a response after the fact that BUSY is confirmed to be low level, reading bit DATA on the DATA one by one when C L K is low level, setting C L K to be high level as a response after each bit DATA is read, releasing the serial bus after one byte of DATA is received, starting a bus interruption mechanism, and continuing processing of other tasks.

In some embodiments, reading the bit DATA on the DATA one by one when the C L K is at a low level, setting the C L K to a high level as a response after reading each bit DATA, including continuously detecting whether the level on the C L K line is at a low level within a preset time, controlling the C L K pin to output a low level for 25 microseconds if the level is at a low level, simultaneously reading the bit DATA on the DATA line, controlling the C L K pin to output a high level as a response after 25 microseconds, continuously reading the level on the C L K line and determining whether the level is at a high level within a preset time, that is, determining whether other terminals on the serial bus have responded, further determining whether the reception of all 8 bit DATA is completed if the level is at a high level, and repeating the above steps until the reception of all 8 bit DATA is completed if the level is not completed.

According to the communication system and method based on the serial bus, the sending end and the receiving end output high levels or low levels at different moments by controlling BUSY and C L K, DATA3 pins, the fact that the sending end and the receiving end do not distinguish master-slave, half-duplex and synchronous data transmission is achieved, byte data are transmitted intermittently and synchronously, the receiving end can be guaranteed to process other tasks within the interval time of receiving the two byte data, and the overall performance of the system is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is an exemplary system architecture diagram in which the present application may be applied;

FIG. 2 is a timing diagram of one embodiment of a serial bus based communication system according to the present application;

FIG. 3 is a flow diagram of an alternative arbitration for serial bus idle state in an embodiment of a serial bus based communication system according to the present application;

FIG. 4 is a flow diagram of one embodiment of a serial bus based communication method according to the present application;

fig. 5 is a flowchart of a transmitting end transmitting one byte of data according to an embodiment of a serial bus based communication method of the present application;

FIG. 6 is a flow diagram for one embodiment of a serial bus based communication method according to the present application;

FIG. 7 is a flow chart of yet another embodiment of a serial bus based communication method according to the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

As shown in FIG. 1, FIG. 1 illustrates an exemplary system architecture 100 to which embodiments of the serial bus based communication system and method of the present application may be applied.

The communication system and method based on the serial bus can be applied to electronic equipment such as robots and toy unmanned planes. These electronic devices are typically configured with a plurality of different types of sensors. As shown in fig. 1, the system architecture 100 may include a geomagnetic sensor 101, an infrared radar 102, a laser sensor 103, a serial bus 104, and a master 105. The geomagnetic sensor 101, the infrared radar 102, the laser sensor 103, and the main controller 105 are interconnected with each other via a serial bus 104, and the main controller 105, as the brain of the robot, communicates with electronic components such as motors and sensors to transmit data or instructions. It should be understood that the type and number of terminals in fig. 1 are merely illustrative. There may be any number and variety of terminals, depending on implementation needs.

The serial bus based on the application can realize the communication without distinguishing the master-slave, half-duplex and synchronization, so that each terminal connected to the serial bus can be used as a sending terminal and a receiving terminal. When a terminal on the serial bus is used as a sending end to send data, other devices on the serial bus become receiving ends, and the steps of receiving byte data sent by the sending end by each receiving end are the same. The application layer at the receiving end processes all the received byte data, for example, analyzes a destination address from the received byte data, compares the destination address with the destination address of the application layer itself, determines whether the two addresses are consistent, discards the received byte data if the two addresses are not consistent, and executes or processes the instruction or information carried in the byte data if the addresses are consistent.

The serial bus comprises 3 signal lines, namely a C L K clock line, a DATA DATA line and a BUSY state line, wherein the 3 signal lines are respectively connected with a pull-up resistor and a power supply, the pull-up resistor clamps an uncertain signal at a high level, when the serial bus is idle, the levels of the BUSY line and the C L K line are high levels, and the level of the DATA line is low level.

With continued reference to FIG. 2, a timing diagram 200 of one embodiment of a serial bus based communication system in accordance with the present application is shown.

The system of this embodiment includes a sending end and at least one receiving end, and each receiving end receives byte data and has the same flow with the sending end, so only one sending end is shown here.

As shown in fig. 2, the timing diagram 200 includes the following steps:

in step 201, the sending end turns off the bus interrupt mechanism, and decides whether the state of the serial bus is idle or not according to the read levels on the BUSY line and the C L K line.

In this embodiment, the terminal, whether it is a transmitting terminal or a receiving terminal, is internally configured with a processor for processing different tasks such as processing instructions or data, performing operations, and the like. By way of example, tasks that require master processing include, but are not limited to: receiving instructions sent by a mobile phone or a remote controller, controlling the rotation of each motor, and carrying out positioning and obstacle avoidance analysis and the like according to data collected by the sensors. When the receiving end processes other tasks and the transmitting end needs to transmit data to the receiving end, the receiving end can suspend processing other tasks by triggering the bus interrupt of the receiving end, and then receives the data on the serial bus. In order to prevent the task of triggering the bus interrupt of the sender to interrupt sending data when the sender sends data, the sender prepares to receive data, so the sender needs to close the bus interrupt mechanism of the sender before sending data through the serial bus.

The method comprises the steps that at one moment, a serial bus can only support one sending end to send DATA, the state of the serial bus is divided into idle state and occupied state, only in the idle state, the sending end can occupy the serial bus to send DATA, in the idle state, the levels on a BUSY line and a C L K line are both high levels, the level on a DATA line is low level, the sending end continuously reads the levels on the BUSY line and a C L K line within preset time until the levels on the BUSY line and the C L K line are both high levels, namely the state of the serial bus is judged to be idle, and the state of the serial bus is judged to be occupied if the preset time is exceeded and the levels on the BUSY line and the C L K line are not high levels.

In some optional implementation manners of this embodiment, in order to reduce the probability that a plurality of terminals simultaneously determine that the state of the serial bus is idle and all occupy the serial bus to cause a transmission error, after determining that the state of the serial bus is idle for the first time, the sending end controls the BUSY pin to output a low level first, and after delaying for a period of time randomly, controls the BUSY pin to output a high level, and determines the state of the serial bus again, and if the state of the serial bus is still idle, the state of the serial bus is determined to be idle, and specific steps are shown in fig. 3.

Step 20101, BUSY ═ 0 or C L K ═ 0?

If at least one of the levels on the BUSY line and the C L K line is low, indicating that the state of the serial bus is occupied, starting a timer to count time, and executing step 20102, and if the levels on the BUSY line and the C L K line are not low, indicating that the state of the serial bus is idle, executing step 20104.

Step 20102, determine whether the time is longer than a preset time.

If the state of the serial bus is judged to be occupied in the step 20101, whether the time measured by the timer is longer than the preset time or not needs to be judged, if not, the step 20101 is skipped, the state of the serial bus is judged in a continuous loop mode, and if the time is longer than the preset time, the step 20103 is skipped. The exemplary shown preset time is set to 10 milliseconds.

Step 20103, arbitrating the status of the serial bus as occupied.

If the preset time in step 20102 is exceeded and the levels on the BUSY line and the C L K line are not high, the status of the serial bus is judged to be occupied.

In step 20104, BUSY is 0.

When the status of the serial bus is determined to be idle in step 20101, the BUSY pin is controlled to output a low level, i.e., BUSY is equal to 0.

And step 20105, delaying n microseconds randomly, and BUSY is 1.

After the step 20104 controls the BUSY pin to output the low level, the random delay is performed for n microseconds, and the BUSY pin is controlled to output the high level, namely, BUSY is equal to 1. Exemplary n may take on values of 5, 10, 15, 20.

Step 20106, BUSY ═ 0 or C L K ═ 0?

And judging whether at least one of the levels on the BUSY line and the C L K line is low level again, if not, indicating that the state of the serial bus is idle at the moment, skipping to the step 20107, if so, indicating that the state of the serial bus is occupied at the moment, resetting the timer, and skipping to the step 20108.

Step 20107, arbitrating the status of the serial bus to idle.

Step 20108, whether the time is longer than a preset time.

If the serial bus is judged to be occupied in the step 20106, whether the time measured by the timer is longer than the preset time or not needs to be judged, if not, the step 20106 is skipped to, the state of the serial bus is continuously and circularly judged, and if the time is longer than the preset time, the step 20109 is skipped to. The exemplary shown preset time is set to 10 milliseconds.

Step 20109, judge the status of the serial bus as occupied when time out.

Step 202, when the state of the serial bus is idle, the sending end sends byte data byte by byte according to a preset time interval.

In this embodiment, the sending end first generates all byte data to be transmitted, calculates the number of bytes, reduces the number by one after sending one byte data, and continues to send the next data after delaying a preset time interval. Wherein, the arrangement form of all byte data is as follows: the synchronization code (1 byte) + destination device address (1 byte) + source device address (1 byte) + length (1 byte) + xor check (1 byte) + data.

In some optional implementations of this embodiment, the sending end repeatedly performs the following steps until all byte data is sent: and sending one byte of data, judging whether all the byte of data are sent completely, and delaying the time interval if not.

In step 203, the receiving end receives byte data sent by the sending end byte by byte. During the time interval between receiving two bytes of data, other tasks may be processed.

The specific process of respectively sending and receiving byte data by the sending end and the receiving end is as follows:

in step 2021, the transmitting end controls the BUSY pin to output a low level, that is, the BUSY line is set to a low level from a high level, and the DATA pin is controlled to output a high level. Wherein setting BUSY low indicates that the serial bus is engaged.

Step 2031, the receiving end monitors the level on the BUSY line in real time, and when it is detected that the level on the BUSY line changes from high level to low level, the receiving end triggers bus interrupt and suspends processing other tasks.

Step 2032, the receiving end reads the level on the BUSY line, and after confirming that the level is low, controls the DATA pin to output high level as a response. Since the signal line of the serial bus has a higher priority of low level, the DATA line appears high when all terminals on the serial bus control the DATA pin to output high level.

The sender may continuously read the level on the DATA line for a preset time until the read level is high, and if the preset time is exceeded and the level on the DATA line is still low, it is necessary to release the bus, i.e., control the BUSY pin to output a high level, control the C L K pin to output a high level, and control the DATA pin to output a low level.

At step 2023, the sender sends the bit DATA in the byte bit by bit through DATA at the falling edge of C L K, and when sending the next bit DATA, it is ensured that the response signal with high level of C L K returned by the receiver has been received.

In step 2033, the receiving end reads the bit DATA on the DATA one by one when C L K is low, and sets C L K to high level as a response after reading each bit DATA.

In step 2024, when the sender determines that there is any unsent byte DATA, the sender controls the DATA pin to output a high level, the C L K pin to output a low level, and the BUSY pin to output a high level, because the C L K, DATA is high at the same time, it indicates that the serial bus is idle, at this time, the C L K pin is controlled to output a low level, which indicates that the serial bus is still occupied for sending the next byte DATA.

Step 2034, after the receiving end reads one byte of data, it releases the serial bus, and starts the bus interrupt mechanism, and then continues to process the original suspended task or the new task with higher priority.

The specific process of respectively sending and receiving bit data by the sending end and the receiving end is as follows:

the transmitting terminal controls the DATA pin to output bit DATA of 1 or 0 represented by high and low levels, namely, the DATA 1 represented by high level and the DATA 0 represented by low level, and simultaneously controls the C L K pin to output low level of 25 microseconds, namely, the level on the C L K line is set to low level from high level, which represents that the DATA is transmitted on the falling edge of C L K, wherein, the high and low levels on the C L K line can also be understood as clock period signals which are alternately composed of high and low levels of 25 microseconds, of course, the clock period can be changed into other values, and the 25 microseconds is changed into 20 microseconds, 30 microseconds, 50 microseconds and the like as an example.

And the receiving terminal continuously detects whether the level on the C L K line is low level within preset time, if so, the C L K pin is controlled to output low level of 25 microseconds, bit DATA on the DATA line is read at the same time, and after 25 microseconds, the C L K pin is controlled to output high level as response.

The transmitting terminal controls the C L K pin to output high level, if the transmitted bit data is not the last bit of byte data, the C L K pin is kept outputting high level for 25 microseconds, the level on the C L K line is continuously read in the preset time and judged whether to be high level, namely, whether all receiving terminals answer is judged, if the level is high level, whether 8 bit data are completely transmitted is further judged, if unsent bit data exist, the steps are repeatedly executed for transmitting next bit data, if the preset time is exceeded, the level on the C L K line is still low level, part of the receiving terminals do not answer, the bit data are transmitted in error, and the serial bus needs to be released.

The receiving end continuously reads the level on the C L K line within the preset time and judges whether the level is high level, namely judges whether other terminals on the serial bus have responded, if the level is high level, further judges whether the 8-bit data are completely received, if bit data which are not received exist, the steps are repeatedly executed, if the preset time is exceeded, the level on the C L K line is still low level, the error of bit data transmission is indicated, and the serial bus needs to be released.

And step 204, after the sending end judges that all byte data are sent, releasing the serial bus.

Whether the sending terminal or the receiving terminal is used, the releasing serial bus controls the BUSY pin and the C L K pin to output high level and controls the DATA pin to output low level.

In this embodiment, the sending end and the receiving end output high levels or low levels at different times by controlling BUSY and C L K, DATA3 pins, so that the sending end and the receiving end do not distinguish master and slave and intermittent half-duplex synchronous transmission of individual byte data, the receiving end can process other tasks within the interval time for receiving two byte data, and the performance is improved.

With continuing reference to fig. 4, a flow 400 of one embodiment of a serial bus based communication method performed by a transmitting end is shown in accordance with the present application. The communication method based on the serial bus comprises the following steps:

step 401, turning off the bus interrupt mechanism, and determining whether the state of the serial bus is idle according to the read levels on the BUSY line and the C L K line.

In this embodiment, a CPU (Central Processing Unit) is disposed inside both the sender and the receiver to process different tasks such as Processing instructions and data and executing operations. When the receiving end processes other tasks and the transmitting end needs to transmit data to the receiving end, the receiving end can suspend processing other tasks by triggering the bus interrupt of the receiving end, and then receives the data on the serial bus. In order to prevent the task of triggering the bus interrupt of the sender to interrupt sending data when the sender sends data, the sender prepares to receive data, so the sender needs to close the bus interrupt mechanism of the sender before sending data through the serial bus.

In the idle state, the levels on the BUSY line and the C L K line are both high level, and the level on the DATA line is low level.

In some optional implementation manners of this embodiment, the levels on the BUSY line and the C L K line are continuously read within a preset time until the levels on the BUSY line and the C L K line are both high levels, that is, the state of the serial bus is determined to be idle, after the state of the serial bus is determined to be idle, the BUSY pin is controlled to output a low level, a period of time delay is randomly performed, then the BUSY pin is controlled to output a high level, the levels on the BUSY line and the C L K line are continuously read again within the preset time until the levels on the BUSY line and the C L K line are both high levels, the state of the serial bus is finally determined to be idle, otherwise, the state of the serial bus is determined to be occupied, so that the probability that the multiple terminals simultaneously determine that the state of the serial bus is idle, and both occupy the serial bus to cause a transmission error is reduced.

Step 402, when the state of the serial bus is idle, byte DATA is sent byte by byte according to a preset time interval, wherein the process of sending each byte DATA is that the BUSY pin is controlled to output low level, namely BUSY is set from high level to low level, after DATA is determined to be high level, namely all receiving terminals set DATA to high level to respond, bit DATA in the byte is sent byte by DATA bit at the falling edge of C L K, when next bit DATA is sent, a response signal that C L K returned by the receiving terminals is high level is ensured to be received, after sending each byte DATA, the byte DATA which is not sent is judged to exist, the DATA pin is controlled to output high level, the C L K pin is output low level, and the BUSY pin is controlled to output high level.

With continued reference to fig. 5, a flow chart 500 for the sender to send one byte of data is shown, which includes the following steps:

in step 501, BUSY is equal to 0, C L K is equal to 1, and DATA is equal to 1.

The control BUSY pin outputs low level and occupies the idle serial bus, in addition, the level on the BUSY line is changed from high level to low level, the bus interruption of all terminals on the serial bus is triggered, the terminals triggered by the bus interruption become receiving terminals, each receiving terminal reads the level on the BUSY line, after confirming that the level on the BUSY line is low level, the DATA pin is controlled to output high level as a response, C L K is 1, the sending terminal control C L K pin outputs high level, DATA is 1, the sending terminal control DATA pin outputs high level, and the sending terminal starting timer is used for timing.

Step 502, DATA ═ 1?

DATA? The indication receiving end reads the level on the DATA line and judges whether the level is high level, and because the priority that the level on the DATA line is low level is high, the level on the DATA line is high level only after all terminals on the serial bus control the DATA pin to output high level. When all receiving terminals on the serial bus control the DATA pin to output high level as a response, go to step 506; if DATA is not equal to 1, indicating that there are still some receiver side acknowledgements, step 503 is performed.

Step 503, determining whether the time is longer than the preset time by 10 ms.

The sending end sets a preset time of 10ms, wherein ms represents millisecond. Within 10ms, it is continuously determined whether all the receiving terminals have responded. Specifically, the time of the reading timer is used as the elapsed time, if the elapsed time is less than 10ms, the loop jumps to step 502 to determine whether all the receivers have responded, and if the elapsed time exceeds 10ms, the DATA is still at a low level, and step 504 is executed.

Step 504, release the serial bus.

Because part of the receiving ends do not answer, the sending of byte data is terminated, and the serial bus is released.

Step 505, an error flag is returned.

The flag is used to indicate that part of the receiving end has not responded, but terminates the transmission of byte data, releases the serial bus, returns the error flag to the application layer, and determines whether to retransmit or discard by the application layer.

Step 506, controlling the DATA pin to output one bit of DATA which is represented by 1 or 0 by high and low levels, wherein C L K is 0, delaying 25us and representing the low level for controlling the C L K pin to output 25us, wherein, for 8 bit of DATA in one byte of DATA, the high bit is selected to be transmitted first, and then the low bit is transmitted, when the receiving end detects that the level on the C L K line is changed from high level to low level, the receiving end reads the bit of DATA on the DATA line, and at the same time, the C L K pin is controlled to output the low level of 25us first, and then the C L K pin is controlled to output the high level of 25us as a response.

In step 507, C L K is 1, and if not the last 1 bit, the delay is 25 us.

If the transmitted bit data was not the last bit data in the previous step 506, the C L K pin is controlled to output a high level of 25us, after which 25us step 508 is executed.

Step

508, 1?

Reading the level at C L K, determining whether the level is high level, i.e. determining whether all the receiving terminals have received bit data, and controlling the C L K pin to output high level as a response, if all the receiving terminals have responded, executing step 512, otherwise, starting the timer to restart, and executing step 509.

In step 509, it is determined whether the elapsed time is greater than 10 ms.

If the level on the C L K line is not equal to the high level in step 508, the time of the timer indicates the elapsed time, and if the elapsed time is less than 10ms, the method returns to step 508 to continuously determine whether the level on the C L K line is high, i.e., within 10ms, continuously and cyclically poll whether all receivers have acknowledged, and if the level on the C L K line is still low for more than 10ms, step 510 is executed.

At step 510, the serial bus is released.

And terminating the transmission of the byte data and releasing the serial bus because part of the receiving ends do not answer.

Step 511, return the error flag.

The error mark is used for indicating that part of the receiving end does not answer, the transmission of byte data is terminated, the serial bus is released, the error mark is returned to the application layer, and the application layer determines whether to retransmit or abandon.

Step 512, determine whether all 8-bit data of one byte of data are sent.

If it is determined in step 508 that all the receivers have received the bit data, it is determined in this step whether the 8-bit data in the byte data have been completely transmitted, and if not, the step 506 is skipped to continue transmitting the next bit data. If all 8 bits of data in the byte of data have been sent, step 513 is performed.

Step 513 determines whether all the byte data is sent completely.

If there are more bytes of data that have not been sent, step 514 is performed.

And step 514, setting DATA to be 1, setting C L K to be 0, setting BUSY to be 1, and delaying for waiting.

After the sending end finishes sending a byte of DATA, the sending end does not release the serial bus, but controls the pin C L K to output low level, continues to occupy the serial bus, controls the pin BUSY to output high level, prepares for triggering bus interrupt when sending the byte of DATA next time, in addition, controls the pin DATA to output high level, and sends the next byte of DATA after delaying and waiting for a preset time interval, and the receiving end can process other tasks in the time interval.

Step 403, after all byte data are sent, releasing the serial bus and starting a bus interrupt mechanism.

After the sending end successfully sends all byte data, the serial bus is released, so that all terminals on the serial bus can occupy the serial bus in the subsequent process, and meanwhile, a bus interrupt mechanism is started to receive data sent by other terminals.

In this embodiment, the sending terminal outputs a high level or a low level by controlling pins BUSY and C L K, DATA, so that byte data is sent to the receiving terminal at intervals without releasing the serial bus, and the receiving terminal is confirmed to have successfully received each time one bit of data is sent.

With continued reference to fig. 6, a flow chart 600 of one embodiment of a serial bus based communication method for use at a receiving end is shown, the flow chart comprising the steps of:

step 601, monitoring the level on the BUSY line in real time, and when detecting that the level on the BUSY line is changed from high level to low level, triggering the bus to be interrupted and suspending processing other tasks.

If a terminal wants to send DATA, the bus interrupt mechanism of the terminal needs to be closed firstly, then the BUSY pin is controlled to output low level, and other terminals on the corresponding serial bus trigger bus interrupt to suspend processing other tasks and turn to a receiving terminal to prepare for receiving the DATA sent by the sending terminal.

Step 602, after confirming that BUSY is low, setting DATA to high level as response.

In this embodiment, the receiving end reads the level on the BUSY line again, and if the level is confirmed to be low, the DATA pin is controlled to output a high level as a response; if the level is confirmed to be high, the just low level is considered to be noise disturbance, and the serial bus is released, and the bus interrupt mechanism is restarted.

In step 603, when C L K is low, bit DATA on DATA are read one by one, and after reading each bit DATA, C L K is set high as a response.

In this embodiment, the sender sends bit DATA of 1 or 0 indicated by high and low levels through the DATA line at the falling edge of C L K, the corresponding receiver reads the bit DATA on the DATA line when detecting that C L K goes low, and after reading the bit DATA, the sender sets C L K to high level as a response, and after confirming that all receivers have responded, the sender sends the next bit DATA.

Step 604, after receiving a byte of data, releasing the serial bus, starting a bus interrupt mechanism, and continuing to process other tasks.

In this implementation, after the sending end sends one byte of data, it will continue to occupy the serial bus and delay for a while before sending the next byte of data. After receiving one byte of data, the receiving end releases the serial bus, starts the bus interrupt mechanism, quits the receiving task, and continues to process other tasks.

In this embodiment, after the receiving end receives all the byte data intermittently, the receiving end parses out the destination address, compares the destination address with its own address, if the two addresses are consistent, retains all the byte data, and if the two addresses are inconsistent, discards all the received byte data.

In the implementation, the task of receiving byte data is processed only when the bus interrupt of the receiving end is triggered, and the interval time for receiving two byte data is utilized to process other tasks, such as a task suspended due to the reception of the previous byte data or a new task, and the like time division multiplexing is adopted, so that the performance of the receiving end is improved.

With continued reference to FIG. 7, a flow chart 700 of yet another embodiment of a serial bus based communication method is shown, the flow chart comprising the steps of:

step 701, BUSY:1- > 0?

In this embodiment, BUSY:1- > 0? And the real-time reading of the level on the BUSY line is shown, whether the level is changed from a high level to a low level is judged, if not, the monitoring is carried out in real time continuously in a circulating mode until the level on the BUSY line is changed from the high level to the low level, and the bus interruption is triggered.

In step 702, BUSY ═ 0?

In this embodiment, BUSY? The method indicates that the BUSY line is read again and whether the level is low level is confirmed, namely whether the existence terminal really controls the BUSY pin to output low level or not is judged, and the serial bus is occupied. If the level on the BUSY line is high, step 703 is performed, and if it is low, step 704 is performed.

Step 703, release the serial bus and start the bus interrupt mechanism.

In this embodiment, if the level on the BUSY line is still at the high level in step 702, it indicates that no terminal occupies the serial bus, and the detected falling edge is just a disturbance in step 701, and it is necessary to release the serial bus, start the bus interrupt mechanism, and wait for the next bus interrupt triggered.

And step 704, delaying for 10us, and keeping DATA equal to 1.

In this embodiment, if it is confirmed that the BUSY line is at a low level in step 702, the delay is 10 microseconds, and the DATA pin is controlled to output a high level as a response.

Step 705, is C L K?

In this embodiment, C L K is 0, which means that the level at C L K is read, and it is determined whether the level is low, that is, it is determined whether the sender is sending bit data, if not, a timer needs to be started for timing, and it is continuously and cyclically detected whether the sender is sending bit data, that is, step 706 is executed.

In step 706, the time taken is >10 ms?

In this embodiment, the time taken to determine whether the loop detect C L K is low is longer than 10ms, if not, step 705 is continued, loop detection is performed, if timeout occurs, reception is stopped, step 703 is executed, the serial bus is released, and the bus interrupt mechanism is turned on, if the level on the C L K line is low, step 707 is executed.

Step 707, read DATA on the DATA line, C L K equals 0, delayed by 25 us.

In this embodiment, when the level on the C L K line is detected as low in step 705, the DATA on the DATA line is read, and the C L K pin is controlled to output low, after a delay of 25 μ s, step 708 is executed.

In step 708, C L K is 1.

In this embodiment, C L K equals 1, which means that the C L K pin is controlled to output a high level, that is, after the C L K pin is controlled to output a low level for 25 microseconds in step 707, the pin is controlled to output a high level as a response.

Step

709, 1?

In this embodiment, C L K is 1, which means that the level on the C L K line is read, and it is determined whether the level is high, the priority of the low level on the C L K line is high, that is, all terminals connected to the serial bus control the C L K pin to output a high level, the level on the C L K line is high, otherwise, the level is low, it is determined whether the C L K is high, that is, it is determined whether all the receivers have received bit data and responded, and the transmitter controls the C L K pin to output a high level, if the level is not, the timer is reset, and step 710 is executed, that is, the timer continuously and cyclically detects whether the level on the C L K line is high within 10 milliseconds.

Step 710, takes >10 ms?

In this embodiment, the time >10 ms.

In step 711, 8-bit data reception is completed?

In this embodiment, after each byte data is sent by the sending end, the sending end will delay for a period of time and send the next byte data, so the receiving end is interrupted to receive only one byte data each time, after receiving each bit data, it is determined whether all the 8-bit data in the next byte data are received, if not, step 705 is executed, that is, the next bit data is received. If the reception of all 8 bits of data is complete, step 712 is performed.

At step 712, the serial bus is released and the bus interrupt mechanism is turned on.

In this embodiment, since the sending end sends byte data intermittently, the receiving end may release the serial bus and start the bus interrupt mechanism after receiving one byte of data, and then process other tasks until being triggered by the bus interrupt again to receive the next byte of data.

In the implementation, the task of receiving byte data is processed only when the falling edge of BUSY is monitored and bus interruption is triggered, and after each bit of data is received, C L K is set to be high level as a response, namely, a C L K clock signal is synchronized, and the condition of receiving missing is eliminated.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A communication system based on a serial bus comprises a sending end, a receiving end and a serial bus, wherein the serial bus comprises three signal lines including a BUSY line, a DATA line and a C L K line, the three signal lines are all high in priority of low level, and BUSY pins, DATA pins and C L K pins of the sending end and the receiving end are respectively connected to the BUSY line, the DATA line and the C L K line of the serial bus, and the communication system is characterized in that:

the sending end closes a bus interrupt mechanism, judges whether the state of a serial bus is idle according to the level on a read BUSY line and a read C L K line, sends byte DATA byte by byte according to a preset time interval when the state of the serial bus is idle, releases the serial bus and starts the bus interrupt mechanism after all the byte DATA are sent, wherein the flow of sending each byte DATA is that the BUSY pin is controlled to output low level, namely the BUSY is set to low level from high level, when the DATA is determined to be high level, namely all receiving ends send DATA to high level to respond, the DATA in the byte DATA is sent bit by bit at the falling edge of C L K, when the next bit DATA is sent, the C L K returned by the receiving ends is ensured to be high level, and when the unsent byte DATA is judged after sending each byte DATA, the DATA pin is controlled to output high level, the C L K pin outputs low level, and the BUSY pin outputs high level;

the receiving terminal is used for repeatedly executing the following steps of monitoring the level on the BUSY line in real time, triggering bus interruption when the level on the BUSY line is detected to be changed from high level to low level, suspending processing of other tasks, setting DATA to be high level as response after the BUSY line is confirmed to be low level, reading bit DATA on the DATA one by one when C L K is low level, setting C L K to be high level as response after reading each bit DATA, releasing the serial bus after reading one byte of DATA, starting a bus interruption mechanism, and processing other tasks.

2. The serial bus based communication system according to claim 1, wherein the transmitting end arbitrates whether the state of the serial bus is idle according to the read levels on the BUSY line and the C L K line, comprising:

continuously reading the levels on a BUSY line and a C L K line within preset time until the levels on the BUSY line and the C L K line are both high levels, namely judging that the state of the serial bus is idle, and judging that the state of the serial bus is occupied if the preset time is exceeded;

and after the state of the serial bus is judged to be idle in the previous step, controlling the BUSY pin to output a low level, randomly delaying for a period of time, controlling the BUSY pin to output a high level, continuously reading the levels on the BUSY line and the C L K line within the preset time again, and finally judging the state of the serial bus to be idle until the levels on the BUSY line and the C L K line are both high levels, otherwise judging the state of the serial bus to be occupied.

3. The serial bus based communication system according to claim 1, wherein the transmitting end transmits byte data byte by byte at a preset time interval, comprising:

the sending end repeatedly executes the following steps until all byte data are sent completely: and sending one byte of data, judging whether all the byte of data are sent completely, and delaying the time interval if not.

4. The serial bus based communication system according to one of claims 1 to 3, wherein the specific flow of transmitting and receiving one bit of data by the transmitting end and the receiving end respectively is as follows:

the sending terminal controls the DATA pin to output bit DATA of 1 or 0 represented by high and low levels, and controls the C L K pin to output low level of 25 microseconds at the same time, namely, the level on the C L K line is set to low level from high level;

the receiving end continuously detects whether the level on the C L K line is low level within a preset time, if so, the C L K pin is controlled to output 25 microseconds of low level, meanwhile, bit DATA on the DATA line is read, and after 25 microseconds, the C L K pin is controlled to output high level as response;

the transmitting end controls the C L K pin to output a high level, continuously reads the level on the C L K line within a preset time and judges whether the level is the high level, namely judges whether all receiving ends have responded, and further judges whether 8-bit data are completely transmitted if the level is the high level;

and the receiving end continuously reads the level on the C L K line within a preset time and judges whether the level is high level, namely judges whether other terminals on the serial bus answer or not, and further judges whether the 8-bit data are completely received or not if the level is high level.

5. The serial bus based communication system according to claim 4, wherein the transmitting end and/or the receiving end releases the serial bus, comprising:

regardless of the sending terminal or the receiving terminal, the serial bus is released by controlling the BUSY pin to output high level, controlling the C L K pin to output high level and controlling the DATA pin to output low level.

6. A serial bus based communication method, the method comprising:

closing a bus interrupt mechanism, and judging whether the state of the serial bus is idle or not according to the read levels of a BUSY line and a C L K line;

controlling a BUSY pin to output a low level, namely setting BUSY from a high level to a low level, when determining that DATA is at a high level, namely all receiving terminals answer after setting DATA to a high level, transmitting bit DATA in the byte by the DATA bit by bit at a falling edge of C L K, ensuring that a response signal that C L K returned by the receiving terminals is at a high level is received when transmitting next bit DATA, and controlling the DATA pin to output a high level, the C L K pin to output a low level and the BUSY pin to output a high level when judging that unsent byte DATA exist after transmitting each byte DATA;

and after all byte data are sent, releasing the serial bus and starting a bus interrupt mechanism.

7. The serial bus based communication method according to claim 6, wherein said arbitrating whether the state of the serial bus is idle according to the read level on the BUSY line and the C L K line comprises:

8. A serial bus based communication method according to claim 6 or 7, wherein said sending byte data byte by byte at preset time intervals comprises:

the following steps are repeatedly executed until all byte data are sent completely: and sending one byte of data, judging whether all the byte of data are sent completely, and delaying the time interval if not.

9. A serial bus based communication method, the method comprising:

monitoring the level on a BUSY line in real time, and when the level on the BUSY line is detected to be changed from a high level to a low level, triggering the bus to be interrupted, and suspending processing of other tasks;

after determining that BUSY is at a low level, setting DATA to be at a high level as a response;

continuously detecting whether the level on the C L K line is low level within preset time, controlling the C L K pin to output low level of 25 microseconds if the level is low level, simultaneously reading bit DATA on the DATA line, controlling the C L K pin to output high level as a response after 25 microseconds, continuously reading the level on the C L K line within preset time and judging whether the level is high level, namely judging whether other terminals on the serial bus respond, further judging whether the reception of 8-bit DATA is finished if the level is high level, and repeatedly executing the step if the level is not high level until the reception of 8-bit DATA is finished;

after receiving one byte of data, the serial bus is released, the bus interrupt mechanism is started, and the processing of other tasks is continued.