CN109582616A - Communication system and method based on universal serial bus - Google Patents
Communication system and method based on universal serial bus Download PDFInfo
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- CN109582616A CN109582616A CN201811480633.1A CN201811480633A CN109582616A CN 109582616 A CN109582616 A CN 109582616A CN 201811480633 A CN201811480633 A CN 201811480633A CN 109582616 A CN109582616 A CN 109582616A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
This application discloses communication systems and method based on universal serial bus.One specific embodiment of the system includes transmitting terminal, receiving end, universal serial bus, wherein, universal serial bus includes three BUSY line, DATA line, CLK line signal wires, transmitting terminal closes bus interrupt mechanism, when the state of the universal serial bus is idle, occupies the universal serial bus, byte-by-byte transmission byte data according to the preset time interval, after all byte datas are sent completely, universal serial bus is discharged, and open bus interrupt mechanism；Receiving end is triggered bus interruption, and after confirmation bus is occupied, 8 bit datas received in a byte data by turn discharge the universal serial bus later, and open bus interrupt mechanism, then handle other tasks.The embodiment realizes the serial data transmission for not distinguishing master-slave equipment, half-duplex, synchronization, in addition, within the interval time for receiving two byte datas, other tasks are can be performed in receiving end, improves systematic entirety energy.
Description
Technical field
This application involves electronic technology fields, more particularly to communication system and method based on universal serial bus.
Background technique
Existing frequently-used bus mainly has SPI (Serial Peripheral Interface, synchronous peripheral interface) bus
With IIC (Inter-Integrated Circuit, integrated circuit) bus, wherein the communication based on spi bus is limited to principal and subordinate
Operating mode, and increase by one and need to increase a CS signal wire from equipment, extension is limited.Communication based on iic bus is same
It is limited to master-slave mode, from equipment only after receiving the read command that main equipment is sent, is just actively sent toward main equipment
Data.Lack a kind of universal serial bus for not distinguishing principal and subordinate, half-duplex, synchronization.
Summary of the invention
The purpose of the application is to propose a kind of communication system and method based on universal serial bus, to solve background above skill
The technical issues of art part is mentioned.
In a first aspect, the system comprises transmitting terminal, being connect this application provides a kind of communication system based on universal serial bus
Receiving end, universal serial bus, wherein the universal serial bus includes three BUSY line, DATA line, CLK line signal wires, three signals
Line is all that low level priority is high, the BUSY pin of the transmitting terminal and the receiving end, DATA pin, CLK pin difference
It is connected on the BUSY line, DATA line, CLK line of the universal serial bus, it is characterised in that: the transmitting terminal is closed bus and interrupted
Mechanism decides whether the state of universal serial bus is the free time, when described serial total according to the level on the BUSY line of reading, CLK line
When the state of line is idle, byte-by-byte transmission byte data according to the preset time interval, after all byte datas are sent completely,
Universal serial bus is discharged, and opens bus interrupt mechanism, wherein sends the process of each byte data are as follows: control BUSY pin is defeated
BUSY is set to low level by high level by low level out, when determining that DATA is high level, i.e., all receiving ends are all by DATA
It is set to after high level responds, in the failing edge of CLK, sends the position data in byte data by turn by DATA, sending
When next bit data, it is ensured that the CLK that receiving end return has been received is the answer signal of high level, is sending each byte
When judging also not sent byte data after data, control DATA pin exports high level, CLK pin exports low level,
BUSY pin exports high level；The receiving end, for repeating following steps: the level on real-time monitoring BUSY line, when
Detect that the level on BUSY line becomes low level by high level, then Trigger Bus interrupts, and pause handles other tasks, confirmation
After BUSY is low level, DATA is set to high level as response, when CLK is low level, the digit on reading DATA one by one
According to after reading every bit data, CLK is set to high level as response, after having read a byte data, described in release
Universal serial bus, and bus interrupt mechanism is opened, then handle other tasks.
In some embodiments, the transmitting terminal decides universal serial bus according to the level on the BUSY line of reading, CLK line
State whether be idle, comprising: constantly read BUSY line, the level on CLK line within a preset time, until BUSY line and
Level on CLK line is all high level, i.e., the state of determination of serial bus is the free time, if it exceeds the preset time, then cut out
The state of the fixed universal serial bus is to occupy；After the state of previous step universal serial bus is determined as the free time, control BUSY pin is defeated
Low level out, for a period of time, control BUSY pin exports high level to random delay, constantly reads in the preset time again
Level on BUSY line, CLK line, until the level on BUSY line and CLK line is all high level, ability absolute decree universal serial bus
State is the free time, decides the state of the universal serial bus otherwise to occupy.
In some embodiments, the transmitting terminal byte-by-byte transmission byte data according to the preset time interval, comprising: hair
Sending end repeats the following steps, until all byte datas are all sent completely: sending a byte data, judges whether own
Byte data is all sent completely, if the time interval that is delayed without if.
In some embodiments, transmitting terminal and receiving end send and receive the detailed process of a bit data respectively are as follows: hair
Sending end control DATA pin output indicates 10 position data with low and high level, while controlling the low electricity that CLK pin exports 25 microseconds
It is flat, i.e., level on CLK line is set to low level by high level；Within a preset time, constantly detect the level on CLK line in receiving end
Whether it is low level, if it is low level, controls CLK pin and export the low level of 25 microseconds, while reading on DATA line
Position data, after 25 microseconds, control CLK pin output high level is as response；Transmitting terminal, control CLK pin export high level,
The level on CLK line is constantly read in preset time and judges whether it is high level, that is, judges whether that all receiving ends have all been answered
It answers, if it is high level, further judges whether 8 bit datas are all sent completely；It constantly reads within a preset time receiving end
It takes the level on CLK line and judges whether it is high level, that is, judge whether other terminals on universal serial bus have all replied, if
For high level, then further judge whether 8 bit datas all finish receiving.
In some embodiments, the either described transmitting terminal or the receiving end, release universal serial bus are all control
BUSY pin exports high level, control CLK pin output high level, control DATA pin and exports low level.
Second aspect, this application provides a kind of communication means based on universal serial bus, which comprises closes bus
Interrupt mechanism decides whether the state of universal serial bus is idle according to the level on the BUSY line of reading, CLK line；When the string
When the state of row bus is idle, byte-by-byte transmission byte data according to the preset time interval, wherein send each byte number
According to process are as follows: control BUSY pin exports low level, i.e., BUSY is set to low level by high level, when determining DATA for high electricity
Flat, i.e., DATA has all been set to after high level responds by all receiving ends, in the failing edge of CLK, is sent by turn by DATA
Position data in byte, when sending next bit data, it is ensured that the CLK that receiving end return has been received is answering for high level
Signal is answered, in judgement also not sent byte data after sending each byte data, control DATA pin output high level,
CLK pin exports low level, BUSY pin exports high level；After all byte datas are sent completely, universal serial bus is discharged, and open
Open bus interrupt mechanism.
In some embodiments, the BUSY line according to reading, the level on CLK line, decide the state of universal serial bus
It whether is idle, comprising: BUSY line, the level on CLK line are constantly read within a preset time, until on BUSY line and CLK line
Level be all high level, i.e., the state of determination of serial bus be free time, if it exceeds the preset time, then decide the string
The state of row bus is to occupy；After the state of previous step universal serial bus is determined as the free time, control BUSY pin exports low level,
Random delay for a period of time, control BUSY pin export high level, constantly read in the preset time again BUSY line,
Level on CLK line, until the level on BUSY line and CLK line is all high level, the state of ability absolute decree universal serial bus is
Otherwise free time decides the state of the universal serial bus to occupy.
In some embodiments, the transmission byte data byte-by-byte according to the preset time interval, comprising: repeat
The following steps, until all byte datas are all sent completely: sending a byte data, judge whether that all byte datas are all sent out
Completion is sent, if the time interval that is delayed without if.
The third aspect, this application provides a kind of communication means based on universal serial bus, which comprises real-time monitoring
Level on BUSY line, when detecting that the level on BUSY line becomes low level by high level, then Trigger Bus interrupts, at pause
Manage other tasks；BUSY is confirmed for after low level, DATA is set to high level as response；When CLK is low level, read one by one
The position data on DATA are taken, after reading every bit data, CLK is set to high level as response, is receiving a byte
After data, the universal serial bus is discharged, and opens bus interrupt mechanism, then continues with other tasks.
In some embodiments, described when CLK is low level, the position data on DATA are read one by one, it is each reading
After the data of position, CLK is set to high level as response, comprising: within a preset time, whether is the level constantly on detection CLK line
It controls CLK pin if it is low level for low level and exports the low level of 25 microseconds, while reading the digit on DATA line
According to, after 25 microseconds, control CLK pin output high level as response, within a preset time constantly reading CLK line on level simultaneously
Judge whether it is high level, that is, judge whether other terminals on universal serial bus have all replied, if it is high level, further
Judge whether 8 bit datas all finish receiving, if fruit does not have, repeat above-mentioned steps, until 8 bit datas have all received
At.
Communication system and method provided by the present application based on universal serial bus, transmitting terminal and receiving end by control BUSY,
CLK, DATA3 pins export high level or low level in different moments, realize transmitting terminal and receiving end does not distinguish principal and subordinate, half
Duplex, synchronous data transmission, and the byte data of the synchronous transfer of intermittent one by one guarantee that receiving end can receive two
In the interval time of a byte data, goes to handle other tasks, improve the performance of system entirety.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, the application's is other
Feature, objects and advantages will become more apparent upon:
Fig. 1 is that this application can be applied to exemplary system architecture figures therein；
Fig. 2 is the timing diagram according to one embodiment of the communication system based on universal serial bus of the application；
Fig. 3 is that optionally ruling is serial total in one embodiment according to the communication system based on universal serial bus of the application
The state of line is idle flow chart；
Fig. 4 is the flow chart according to one embodiment of the communication means based on universal serial bus of the application；
Fig. 5 is that transmitting terminal sends a word in one embodiment according to the communication means based on universal serial bus of the application
The flow chart of joint number evidence；
Fig. 6 is the flow chart according to one embodiment of the communication means based on universal serial bus of the application；
Fig. 7 is the flow chart according to another embodiment of the communication means based on universal serial bus of the application.
Specific embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related invention, rather than the restriction to the invention.It also should be noted that in order to
Convenient for description, part relevant to related invention is illustrated only in attached drawing.
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
As shown in Figure 1, Fig. 1 shows the implementation that can apply the communication system and method based on universal serial bus of the application
The exemplary system architecture 100 of example.
The communication system based on universal serial bus and method of the application can be applied to the electronics such as robot, toy unmanned plane
In equipment.These electronic equipments generally configure the sensor of multiple and different types.As shown in Figure 1, system architecture 100 may include
Geomagnetic sensor 101, infrared radar 102, laser sensor 103, universal serial bus 104, master control 105.Geomagnetic sensor 101,
Infrared radar 102, laser sensor 103, master control 105 are interconnected amongst one another by universal serial bus 104, and master control 105 is used as robot
Brain, communicated with soft copies such as motor, sensors, to transmit data or instruction.It should be understood that in Fig. 1 the type of terminal and
Number is only schematical.According to needs are realized, the terminal of arbitrary number, type can have.
Universal serial bus based on the application can realize do not distinguish principal and subordinate, half-duplex, synchronization communication, so being connected to serial
Each terminal in bus can both do transmitting terminal, can also do receiving end.When a terminal on universal serial bus is as transmission
End sends data, then other equipment on the universal serial bus all become receiving end, and each receiving end receives the word that transmitting terminal is sent
Joint number according to the step of it is all identical.The application layer of receiving end processes received all byte datas, for example, from received byte
In data, destination address is parsed, is made comparisons with the destination address of itself, judges whether two addresses are consistent, if two ground
Location is inconsistent, then abandons the byte data received, if address is consistent, executes or handle the instruction carried in byte data
Or information.
Universal serial bus includes 3 signal lines, it may be assumed that CLK clock line, DATA line, BUSY condition line.Above-mentioned 3 bars
Line connects pull-up resistor and power supply respectively, wherein pull-up resistor is by uncertain signal clamper in high level.The universal serial bus is idle
When, the level on BUSY line, CLK line is high level, and the level on DATA line is low level.The communication system based on universal serial bus
System is digital display circuit, and the high level on signal wire indicates that number 1, low level indicate number 0, wherein low level priority is high,
I.e. for a certain signal wire, when all terminals being connected on the signal wire all export high level, the signal wire is just showed at this time
It is otherwise low level for high level, is equivalent to and does and calculate to the 01 of the output of all terminals, all terminals all export 1, with fortune
It is just 1 after calculation.
With continued reference to Fig. 2, show one embodiment of the communication system based on universal serial bus according to the application when
Sequence Figure 200.
In the system of the present embodiment, including a transmitting terminal and at least one receiving end, because each receiving end receives word
Joint number according to and the process that is interacted with transmitting terminal it is all identical, so showing a transmitting terminal at this.
As shown in Fig. 2, timing diagram 200 the following steps are included:
Step 201, transmitting terminal closes bus interrupt mechanism, according to the level on the BUSY line of reading, CLK line, ruling string
Whether the state of row bus is idle.
In the present embodiment, the terminal of receiving end is either still used as transmitting terminal, inside all configuration processors
Pass through the different task of processing such as process instruction or data, execution operation.As an example, need master control handle task include but
It is not limited to: receiving the instruction of mobile phone or remote controler transmission, the rotation of each motor of control, the data acquired according to sensor, do
Positioning and avoidance analysis etc..When receiving end is handling other tasks, and transmitting terminal is needed to receiving end transmission data at this time, then
It can be interrupted by triggering the bus of receiving end, so that receiving end pause is handled other tasks, then receive the number on universal serial bus
According to.When to prevent transmitting terminal from sending data, the bus for triggering itself is interrupted, and interrupts this task of data that sends, then is prepared
Data are received, so transmitting terminal needs first to close the bus interrupt mechanism of itself before sending data by universal serial bus.
In the present embodiment, a moment, universal serial bus can only support a transmitting terminal to send data.The shape of universal serial bus
State is divided into idle and occupies, and only in idle state, transmitting terminal could occupy the universal serial bus for sending data.Idle state
When, the level on BUSY line, CLK line is all high level, and the level on DATA line is low level.Transmitting terminal is in the preset time
Interior, on continuous reading BUSY line, CLK line level, until the level on BUSY line, CLK line is all high level, i.e. ruling is gone here and there
The state of row bus is the free time, is not high level more than the level in preset time and BUSY line, CLK line, then ruling is serial
The state of bus is to occupy.
In some optional implementations of the present embodiment, to reduce the shape that multiple terminals determine the universal serial bus simultaneously
State is the free time, and all occupies the probability that the universal serial bus causes error of transmission, shape of the transmitting terminal in first time determination of serial bus
After state is idle, control BUSY pin first exports low level, random delay for a period of time after, the high electricity of control BUSY pin output
It is flat, the state of the universal serial bus is determined again, if the state of the universal serial bus is still the free time, decides the state of universal serial bus
For the free time, specific step is shown in Fig. 3.
Step 20101, BUSY==0 or CLK==0?
BUSY==0 indicates whether the level on BUSY line is low level, and similarly, CLK==0 indicates the electricity on CLK line
Whether flat be low level, and BUSY==0 or CLK==0 indicate BUSY line, whether at least one is low electricity to the level on CLK line
It is flat, if level on BUSY line, CLK line at least one be low level, indicate that the state of universal serial bus to occupy, then opens meter
When device timing, and execute step 20102, if the level on BUSY line, CLK line is not low level, indicate the universal serial bus
State be free time, then follow the steps 20104.
Step 20102, whether the time used is greater than preset time.
If the state of determination of serial bus is to occupy in step 20101, then need first to judge the institute of timer metering
Whether it is greater than preset time with the time, if it is not, then jumping to step 20101, continues cycling through the state for determining the universal serial bus,
If the time used is greater than preset time, step 20103 is jumped to.Preset time shown in illustrative is set as 10 milliseconds.
Step 20103, the state of universal serial bus is decided to occupy.
More than the preset time in step 20102, and the level on BUSY line, CLK line is not high level, then decides string
The state of row bus is to occupy.
Step 20104, BUSY=0.
In step 20101, the state of determination of serial bus is the free time, then controls BUSY pin output low level, i.e.,
BUSY=0.
Step 20105, random delay n microsecond, BUSY=1.
After step 20104 control BUSY pin output low level, random delay n microsecond, control BUSY pin output height
Level, i.e. BUSY=1.Illustrative n can be with value for 5,10,15,20.
Step 20106, BUSY==0 or CLK==0?
Determine whether at least one is low level for BUSY line, the level on CLK line again, if it is not, then indicating to go here and there at this time
The state of row bus is the free time, jumps to step 20107, if it is, indicate that the state of universal serial bus at this time is to occupy, timing
Device reclocking jumps and executes step 20108.
Step 20107, decide the state of universal serial bus for the free time.
Step 20108, whether the time used is greater than preset time.
If the state of determination of serial bus is to occupy in step 20106, then need first to judge the institute of timer metering
Whether it is greater than preset time with the time, if it is not, then jumping to step 20106, continues cycling through the state for determining the universal serial bus,
If the time used is greater than preset time, step 20109 is jumped to.Preset time shown in illustrative is set as 10 milliseconds.
Step 20109, overtime, the state of universal serial bus is decided to occupy.
Step 202, when the state of universal serial bus is idle, transmitting terminal byte-by-byte transmission word according to the preset time interval
Joint number evidence.
In the present embodiment, transmitting terminal first generates all byte datas to be transmitted, and calculates the number of byte, sends one
After a byte data, number subtracts one, is delayed after prefixed time interval, continues to send next data.Wherein, all byte datas
Spread pattern are as follows: synchronous code (1 byte)+mesh device address (1 byte)+source device address (1 byte)+length (1 byte)+
Exclusive or check (1 byte)+data.
In some optional implementations of the present embodiment, transmitting terminal repeats the following steps, until all bytes
Data are all sent completely: being sent a byte data, judged whether that all byte datas are all sent completely, if being delayed without if
Above-mentioned time interval.
Step 203, the byte-by-byte byte data for receiving transmitting terminal and sending in receiving end.It is receiving among two byte datas
In time interval, other tasks can be handled.
Wherein, transmitting terminal and receiving end send and receive the detailed process of byte data respectively are as follows:
Step 2021, transmitting terminal control BUSY pin exports low level, i.e., BUSY line is set to low level by high level, controls
DATA pin processed exports high level.Wherein, BUSY is set to low level, indicates to occupy the universal serial bus.
Step 2031, the level on receiving end real-time monitoring BUSY line, when detecting the level on BUSY line by high level
Become low level, then Trigger Bus interrupts, and pause handles other tasks.
Step 2032, the level on BUSY line is read in receiving end, confirms the level for after low level, control DATA pin is defeated
High level is as response out.Because the low level priority of the signal wire of universal serial bus is high, so when all on the universal serial bus
Terminal all controls DATA pin output high level, and DATA line just shows as high level.
Step 2022, transmitting terminal reads the level on DATA line, determines whether the level is high level, i.e., all receiving ends
DATA is all set to high level and makes response.Transmitting terminal can constantly read the level on DATA line within the preset time,
Until the level of reading is high level, if it exceeds preset time, and the level on DATA line is still low level, then needs to discharge
Bus, i.e. control BUSY pin export high level, and control CLK pin exports high level, and control DATA pin exports low level.Such as
Level on fruit DATA line is high level, i.e., DATA is all set to high level and makes response by all receiving ends.
Step 2023, transmitting terminal sends the position data in byte by DATA, under transmission in the failing edge of CLK by turn
When one bit data, it is ensured that the CLK that receiving end return has been received is the answer signal of high level.
Step 2033, the position data on DATA are read when CLK is low level in receiving end one by one, are reading every units
According to rear, CLK is set to high level as response.
Step 2024, there are also when not sent byte data, control DATA pin exports high level, CLK for transmitting terminal judgement
Pin exports low level, BUSY pin exports high level.Because CLK, DATA are that high level just indicates serial idle simultaneously, at this point,
It controls CLK pin and exports low level, expression still occupies the universal serial bus, for sending next byte data.If sent
End judges that all byte datas have all been sent, then discharges universal serial bus.
Step 2034, receiving end discharges universal serial bus after having read a byte data, and opens off line in bus
System, then continue with former stopped task or the higher task of new priority.
Specific transmitting terminal and receiving end are in the detailed process for sending and receiving a data respectively are as follows:
Transmitting terminal control DATA pin output indicates 10 position data with low and high level, while controlling CLK pin output 25
Level on CLK line is set to low level by high level, indicates the failing edge in CLK, sent out by DATA line by the low level of microsecond
Send data.Wherein, the low and high level on CLK line also is understood as clock cycle signal, by the low and high level alternate group of 25 microseconds
At certainly, the clock cycle can change other numerical value into.As an example, by 25 above-mentioned microseconds be substituted for 20 microseconds, 30 microseconds,
50 microseconds etc..
Within a preset time, whether the level constantly detected on CLK line is low level for receiving end, if it is low level,
It controls CLK pin and exports the low level of 25 microseconds, while reading the position data on DATA line, after 25 microseconds, control CLK pin is defeated
High level is as response out.If it exceeds preset time, the level on CLK line is still high level, then it represents that transmission position data go out
Mistake need to discharge universal serial bus.
Transmitting terminal controls CLK pin and exports high level, if the position data sent are not last positions of byte data,
It keeps CLK pin to export 25 microsecond of high level, constantly read the level on CLK line within a preset time and judges whether it is high electricity
It is flat, that is, judge whether that all receiving ends have all been replied, if it is high level, further judges whether 8 bit datas all send
It completes, if repeating above-mentioned step for sending next bit data there is also not sent position data.If super
Preset time is crossed, the level on CLK line is still low level, then it represents that part receiving end is not replied, and position corrupt data is transmitted, and is needed
Discharge universal serial bus.
Receiving end constantly reads the level on CLK line within a preset time and judges whether it is high level, i.e. judgement is serial
Whether other terminals in bus have all replied, and if it is high level, further judge whether 8 bit datas have all received
At if repeating above-mentioned step there is also not received position data.Electricity if it exceeds preset time, on CLK line
Flat is still low level, then it represents that transmission position corrupt data need to discharge universal serial bus.
Step 204, after transmitting terminal judges that all byte datas are sent completely, universal serial bus is discharged.
Either transmitting terminal or receiving end, release universal serial bus are all control BUSY pin and the high electricity of CLK pin output
Flat, control DATA pin exports low level.
In the present embodiment, transmitting terminal and receiving end are exported by BUSY, CLK, DATA3 pins of control in different moments
High level or low level, realize transmitting terminal and receiving end do not distinguish principal and subordinate, intermittent half-duplex synchronous transfer one by one
Byte data guarantees that receiving end can be gone to handle other tasks within the interval time for receiving two byte datas, similar timesharing
Multiplexing, improves performance.
With continued reference to Fig. 4, the stream of one embodiment of the communication means based on universal serial bus according to the application is shown
Journey 400, this method is executed by transmitting terminal.The communication means based on universal serial bus, comprising the following steps:
Step 401, bus interrupt mechanism is closed, according to the level on the BUSY line of reading, CLK line, decides universal serial bus
State whether be idle.
In the present embodiment, either transmitting terminal or receiving end, inside all configure CPU (central processing unit,
Central Processing Unit) pass through the different task of processing such as process instruction or data, execution operation.Work as receiving end
Other tasks are being handled, and transmitting terminal needs to send data to receiving end at this time, then can pass through the bus of triggering receiving end
It interrupts, so that receiving end pause is handled other tasks, then receive the data on universal serial bus.To prevent transmitting terminal from sending data
When, the bus for triggering itself is interrupted, and interrupts this task of data that sends, then prepares to receive data, so transmitting terminal is logical
It crosses before universal serial bus transmission data, needs first to close the bus interrupt mechanism of itself.
In the present embodiment, a moment, universal serial bus can only support a transmitting terminal to send data.The shape of universal serial bus
State is divided into idle and occupies, and only in idle state, transmitting terminal could occupy the universal serial bus for sending data.Idle state
When, the level on BUSY line, CLK line is all high level, and the level on DATA line is low level.Transmitting terminal is in the preset time
Interior, on continuous reading BUSY line, CLK line level, until the level on BUSY line, CLK line is all high level, i.e. ruling is gone here and there
The state of row bus is the free time, is more than preset time, and the level on BUSY line, CLK line is not high level, then ruling is serial total
The state of line is to occupy.It is 5 milliseconds as the above-mentioned preset time of example.
In some optional implementations of the present embodiment, BUSY line is constantly read within a preset time, on CLK line
Level, until the level on BUSY line and CLK line is all high level, i.e., the state of determination of serial bus is the free time, when judgement is gone here and there
After the state of row bus is idle, first controls BUSY pin and export low level, random delay for a period of time, then controls BUSY pin
High level is exported, BUSY line, the level on CLK line are constantly read within a preset time again, until on BUSY line and CLK line
Level is all high level, and the state of ability absolute decree universal serial bus is the free time, decides the state of the universal serial bus otherwise to occupy.
To reduce multiple terminals while determine that the state of the universal serial bus as the free time, and all occupies the universal serial bus and causes error of transmission
Probability.
Step 402, when the state of universal serial bus is idle, byte-by-byte transmission byte number according to the preset time interval
According to, wherein send the process of each byte data are as follows: control BUSY pin exports low level, i.e., is set to BUSY by high level
Low level, when determining that DATA is high level, i.e., DATA has all been set to after high level responds by all receiving ends, CLK's
Failing edge sends the position data in byte by DATA by turn, when sending next bit data, it is ensured that reception has been received
Holding the CLK returned is the answer signal of high level, and judgement is controlled there are also when not sent byte data after sending each byte data
DATA pin processed exports high level, CLK pin output low level, BUSY pin and exports high level.Some in the present embodiment can
In the implementation of choosing, above-mentioned transmission byte data byte-by-byte according to the preset time interval, comprising: repeat following step
Suddenly, until all byte datas are all sent completely: sending a byte data, judge whether that all byte datas have all been sent
At if the time interval that is delayed without if.
With continued reference to Fig. 5, the flow chart 500 that transmitting terminal sends a byte data is shown, which includes as follows
Step:
Step 501, BUSY=0, CLK=1, DATA=1.
BUSY=0 indicates that control BUSY pin exports low level, occupies the universal serial bus of the free time；In addition, on BUSY line
Level low level is become by high level, can trigger all terminals on the universal serial bus bus interrupt, be triggered in bus
Disconnected terminal becomes receiving end, and level on BUSY line is read in each receiving end, after confirming that the level on the BUSY line is low level,
DATA pin output high level is controlled as response.CLK=1 indicates that transmitting terminal control CLK pin exports high level, DATA=1
Indicate that transmitting terminal control DATA pin exports high level, in addition, transmitting terminal, which opens timer, is used for timing.
Step 502, DATA==1?
DATA==1? it indicates that the level on DATA line is read in receiving end, and judges whether the level is high level, because
Level on DATA line is that low level priority is high, when all terminals on the universal serial bus all control DATA pin output height
After level, the level on DATA line is just high level.When all receiving ends on the universal serial bus all control the output of DATA pin
After high level is as response, then follow the steps 506；If DATA indicates not reply there are also part receiving end not equal to 1,
Execute step 503.
Step 503, judge whether the time used is greater than preset time 10ms.
Transmitting terminal setting one preset time 10ms, ms indicate millisecond.In 10ms, constantly judge whether all receptions
End all has answered that.The specific time for reading timer recycles jump if the time used is less than 10ms as the time used
It goes to step 502 and judges whether that all receiving ends all have answered that, if it exceeds 10ms, DATA are still low level, then execute
Step 504.
Step 504, universal serial bus is discharged.
Because part receiving end is not replied, byte data is sent so terminating, discharges universal serial bus.
Step 505, error identification is returned.
The mark is not replied for expressed portion tap receiving end, and is terminated and sent byte data, universal serial bus is discharged, by this
Error identification returns to application layer, determines it is to retransmit also to be to give up by application layer.
Step 506, control DATA pin output indicates 10 bit data with low and high level, and CLK=0, be delayed 25us,
Indicate the low level of control CLK pin output 25us.Wherein, for 8 bit datas in a byte data, selection is first sent
A high position retransmits low level.Receiving end can read DATA line when detecting that the level on CLK line becomes low level by high level
On position data, while first control CLK pin output 25us low level, then control CLK pin output 25us high level make
For response.
Step 507, CLK=1, if not last 1, then be delayed 25us.
If the position data of transmission are not last bit datas in previous step 506, then the output of CLK pin is controlled
The high level of 25us just executes step 508 after the 25us.If the position data sent are last bit datas, export
The time of high level is unlimited, directly execution step 508.
Step 508, CLK==1?
The level on CLK is read, judges whether the level is high level, that is, judges whether all receiving ends all received bits
Data, and CLK pin output high level is controlled as response.If receiving end has all been replied, 512 are thened follow the steps.Otherwise, it opens
Timer reclocking is opened, step 509 is executed.
Step 509, judge whether the time used is greater than 10ms.
If in step 508, the level on CLK line is not equal to high level, then the time of timer indicates the time used,
If the time used is less than 10ms, return step 508 continues to judge whether level is high level on CLK line.I.e. in 10ms
Interior, whether all receiving ends of continuous cyclic query all have answered that.If it exceeds the level on 10ms, CLK line remain as it is low
Level thens follow the steps 510.
Step 510, universal serial bus is discharged.
Because part receiving end is not replied, then transmission byte data is terminated, discharges universal serial bus.
Step 511, error identification is returned.
Accidentally mark is not replied for expressed portion tap receiving end, and is terminated and sent byte data, universal serial bus is discharged, by this
Error identification returns to application layer, determines it is to retransmit also to be to give up by application layer.
Step 512, judge whether 8 bit datas an of byte data are all sent completely.
If confirming all receiving ends all received bit data in step 508, judge in this step, the byte number
Whether 8 bit datas in have all been sent completely, and jump if not and execute step 506, continue to send next position
Data.If 8 bit datas in the byte data have all been sent completely, 513 are thened follow the steps.
Step 513, judge whether all byte datas are all sent completely.
If thening follow the steps 514 there is also not sent byte data.
Step 514, DATA=1, CLK=0, BUSY=1, delay wait.
Receiving end can discharge universal serial bus after 8 bit datas for judging a byte data have all received, and open total
Line interrupt mechanism waits the transmission of next byte data.And transmitting terminal does not discharge string after having sent a byte data
Row bus, but control CLK pin and export low level, the universal serial bus is held over, control BUSY pin exports high level, is
Trigger Bus interruption is prepared when one next time sent byte data, in addition, control DATA pin exports high level, delay waits pre-
If time interval after, send next byte data, and receiving end can be gone to handle other tasks in this time interval.
Step 403, after all byte datas are sent completely, universal serial bus is discharged, and open bus interrupt mechanism.
Transmitting terminal discharges universal serial bus, after being successfully transmitted all byte datas so as to all ends on the universal serial bus
End can occupy the universal serial bus subsequent, while open bus interrupt mechanism, in case receiving the data that other terminals are sent.
In the present embodiment, transmitting terminal exports high level or low level by control BUSY, CLK, DATA pin, realizes
In the case where not discharging universal serial bus, intermittent sends byte data to receiving end, and confirms after one bit data of every transmission
Receiving end has been properly received.
With continued reference to Fig. 6, the flow chart 600 of one embodiment of the communication means based on universal serial bus, the party are shown
Method is applied to receiving end, as shown, the flow chart includes the following steps:
Step 601, the level on real-time monitoring BUSY line, when detecting that the level on BUSY line becomes low electricity by high level
Flat, then Trigger Bus interrupts, and pause handles other tasks.
In the present embodiment, when the universal serial bus free time, the level on BUSY line is high level, the level on CLK line is
Level on high level, DATA line is low level.All terminals being connected on the free time universal serial bus have been switched in bus
Whether off line system, level on real-time monitoring BUSY line by high level become low level.If there is terminal data to be sent, then need
The bus interrupt mechanism of itself is first closed, BUSY pin is then controlled and exports low level, it is other on corresponding universal serial bus
Terminal detects that the level on BUSY line becomes low level by high level, then Trigger Bus interrupts, and pause handles other tasks, turns
And become receiving end, prepare to receive the data that transmitting terminal is sent.
Step 602, after confirmation BUSY is low level, DATA is set to high level as response.
In the present embodiment, receiving end reads again the level on BUSY line, if it is confirmed that the level is low level, then controls
DATA pin output high level processed is as response；If it is confirmed that the level is high level, then it is assumed that low level just now is noise
Disturbance, and universal serial bus is discharged, reopen bus interrupt mechanism.
Step 603, when CLK is low level, the position data on DATA are read one by one, it, will after reading every bit data
CLK is set to high level as response.
In the present embodiment, failing edge of the transmitting terminal in CLK, 10 digits indicated by DATA line transmission with low and high level
According to, corresponding receiving end detect CLK be lower level when, read the position data on DATA line, after reading this bit of data, general
CLK is set to high level as response, and transmitting terminal can send next bit data after confirming that all receiving ends are all replied.
Step 604, after having received a byte data, universal serial bus is discharged, and open bus interrupt mechanism, then after
The continuous other tasks of processing.
In this embodiment, after transmitting terminal has sent a byte data, will continue to occupy universal serial bus, and be delayed one section when
Between, just send next byte data.And receiving end can discharge universal serial bus after having received a byte data, and open
Bus interrupt mechanism exits reception task, then continues with other tasks.
In the present embodiment, after the complete all byte datas of the reception of receiving end intermittent, destination address can be parsed, and will
The destination address is compared with the address of itself, if two addresses are consistent, retains all byte datas, if different
It causes, then abandons the received all byte datas of institute.
In this embodiment, only when the bus for triggering receiving end is interrupted, just processing receives this task of byte data, and
Using the interval time for receiving two byte datas, go to handle other tasks, for example, suspend because receiving a upper byte data
Task or new task, similar time-sharing multiplex, improve the performance of receiving end.In addition, receiving end is after receiving every bit data, all
CLK is set to high level as response, that is, is synchronized CLK clock signal, and eliminate the case where missing receipts.
With continued reference to Fig. 7, the flow chart 700 of another embodiment of the communication means based on universal serial bus is shown, it should
Flow chart includes the following steps:
Step 701, BUSY:1- > 0?
In the present embodiment, BUSY:1- > 0? indicate in real time read BUSY line on level, and judge the level whether by
High level becomes low level, if NO, then needs to recycle continuous real-time perfoming monitoring, until monitoring the electricity on BUSY line
It is flat to be lower level by high level, and Trigger Bus interrupts.
Step 702, BUSY==0?
In the present embodiment, BUSY==0? expression reads again BUSY line in level, and confirms whether the level is low
Level judges whether really there is terminal control BUSY pin output low level, and occupy universal serial bus.If BUSY line
On level be high level, then follow the steps 703, if it is low level, then follow the steps 704.
Step 703, universal serial bus is discharged, bus interrupt mechanism is opened.
In the present embodiment, if in step 702, the level on BUSY line remains as high level, then it represents that there is no eventually
It holds and occupies universal serial bus, in step 701, the failing edge detected is only disturbed, then needs to discharge universal serial bus, and open
Bus interrupt mechanism waits Trigger Bus next time to interrupt.
Step 704, be delayed 10us, DATA=1.
In the present embodiment, if in a step 702, confirmation BUSY line is low level in level really, then delay 10 is micro-
Second, control DATA pin output high level is as response.Transmitting terminal is determined all by judging that level is high level on DATA line
Receiving end has all been replied, then controls CLK pin output low level, and in the failing edge of CLK, sends position data by DATA line.
Step 705, CLK==0?
In the present embodiment, CLK==0? it indicates to read the level on CLK, and confirms whether the level is low level, i.e.,
Judge whether transmitting terminal is sending position data, when if it is otherwise needing to open timer, and continuous cycle detection is sent
Whether end is sending position data, i.e. execution step 706.
Step 706, time used > 10ms?
In the present embodiment, judge whether cycle detection CLK be the time used in low level more than 10 milliseconds, if do not had
Have, then continue to execute step 705, carry out cycle detection, if it times out, stopping receiving, executes step 703, release is serial total
Line, and open bus interrupt mechanism.If detecting that the level on CLK line is low level, 707 are thened follow the steps.
Step 707, the upper data of DATA line are read, CLK=0, be delayed 25us.
In the present embodiment, in step 705, detect that level is low level on CLK line, then it is upper to read DATA line
Data, while CLK pin output low level is controlled, after 25 microseconds that are delayed, execute step 708.
Step 708, CLK=1.
In the present embodiment, CLK=1 indicates that control CLK pin exports high level, i.e., CLK pin is controlled in step 707
After the low level for exporting 25 microseconds, pin output high level is controlled as response.
Step 709, CLK==1?
In the present embodiment, CLK==1? it indicates to read level on CLK line, and judges whether it is high level.On CLK line
Low level priority is high, and all terminals being attached on the universal serial bus all control CLK pin output high level, CLK line
On level be just high level, be otherwise low level.Judge CLK whether high level, that is, determine whether that all receiving ends have all connect
Position data and response are received, while transmitting terminal control CLK pin exports high level.If NO, then timer reclocking executes
Step 710, i.e., whether level is high level on continuous cycle detection CLK line within 10 milliseconds of time.
Step 710, time used > 10ms?
In the present embodiment, time used > 10ms? indicate cycle detection CLK whether be the time used in high level whether
Greater than 10 milliseconds, if it is not, continuing cycling through detection, if it times out, executing step 703, universal serial bus is discharged, stops connecing
It receives, and opens bus interrupt mechanism.
Do step 711,8 data finish receiving?
After the present embodiment, transmitting terminal one byte data of every transmission, it can be delayed a period of time, retransmit next byte
Data after having received every bit data, all determine the lower word so receiving end is interrupted every time only receives a byte data
Whether 8 bit datas of the joint number in all finish receiving, and jump if not and execute step 705, that is, receive next units
According to.If 8 bit datas all finish receiving, 712 are thened follow the steps.
Step 712, universal serial bus is discharged, bus interrupt mechanism is opened.
In the present embodiment, because of the transmission byte data that transmitting terminal is intermittent, so receiving end is every to have received a word
Joint number can discharge universal serial bus after, open bus interrupt mechanism, then go to handle other tasks, until being triggered again
Bus is interrupted, and next byte data is received.
In this embodiment, the failing edge of BUSY is only monitored, and when Trigger Bus interruption, just processing receives byte data
CLK is all set to high level as response, that is, is synchronized CLK clock signal, again by this task after receiving every bit data
The case where receipts, is missed in elimination.
Above description is only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art
Member is it should be appreciated that invention scope involved in the application, however it is not limited to technology made of the specific combination of above-mentioned technical characteristic
Scheme, while should also cover in the case where not departing from the inventive concept, it is carried out by above-mentioned technical characteristic or its equivalent feature
Any combination and the other technical solutions formed.Such as features described above has similar function with (but being not limited to) disclosed herein
Can technical characteristic replaced mutually and the technical solution that is formed.
Claims (10)
1. a kind of communication system based on universal serial bus, the system comprises transmitting terminal, receiving end, universal serial bus, wherein described
Universal serial bus includes three BUSY line, DATA line, CLK line signal wires, and three signal wires are all that low level priority is high,
The transmitting terminal and the BUSY pin of the receiving end, DATA pin, CLK pin are connected respectively to the BUSY of the universal serial bus
Line, DATA line, on CLK line, it is characterised in that:
The transmitting terminal closes bus interrupt mechanism according to the level on the BUSY line of reading, CLK line and decides universal serial bus
State whether be it is idle, when the state of the universal serial bus is idle, byte-by-byte transmission byte according to the preset time interval
Data after all byte datas are sent completely, discharge universal serial bus, and open bus interrupt mechanism, wherein send each byte
The process of data are as follows: control BUSY pin export low level, i.e., BUSY is set to low level by high level, when determine DATA for height
DATA has all been set to after high level responds, in the failing edge of CLK, has been sent out by turn by DATA by level, i.e., all receiving ends
The position data in byte data are sent, when sending next bit data, it is ensured that the CLK of receiving end return has been received as high electricity
Flat answer signal, in judgement after sending each byte data there are also when not sent byte data, control DATA pin is exported
High level, CLK pin output low level, BUSY pin export high level；
The receiving end, for repeating following steps: the level on real-time monitoring BUSY line, when detecting on BUSY line
Level becomes low level by high level, then Trigger Bus interrupts, and pause handles other tasks, will after confirmation BUSY is low level
DATA is set to high level as response, when CLK is low level, reads the position data on DATA one by one, is reading every units
According to rear, CLK is set to high level as response, after having read a byte data, discharges the universal serial bus, and open total
Line interrupt mechanism, then handle other tasks.
2. the communication system according to claim 1 based on universal serial bus, which is characterized in that the transmitting terminal is according to reading
BUSY line, the level on CLK line, decide whether the state of universal serial bus is idle, comprising:
BUSY line, the level on CLK line are constantly read within a preset time, until the level on BUSY line and CLK line is all high
Level, the i.e. state of determination of serial bus are the free time, if it exceeds the preset time, then decide the state of the universal serial bus
To occupy；
After the state of previous step universal serial bus is determined as the free time, control BUSY pin exports low level, at one section of random delay
Between, control BUSY pin exports high level, constantly reads BUSY line, the level on CLK line in the preset time again, directly
Level on to BUSY line and CLK line is all high level, and the state of ability absolute decree universal serial bus is the free time, otherwise described in ruling
The state of universal serial bus is to occupy.
3. the communication system according to claim 1 based on universal serial bus, which is characterized in that the transmitting terminal is according to default
The byte-by-byte transmission byte data of time interval, comprising:
Transmitting terminal repeats the following steps, until all byte datas are all sent completely: sending a byte data, judgement is
No all byte datas are all sent completely, if the time interval that is delayed without if.
4. according to claim 1 based on the communication system of universal serial bus described in one of -3, which is characterized in that transmitting terminal and reception
End sends and receives the detailed process of a bit data respectively are as follows:
Transmitting terminal, control DATA pin output indicate 10 position data with low and high level, while controlling CLK pin and exporting 25 microseconds
Low level, i.e., level on CLK line is set to low level by high level；
Receiving end, within a preset time, whether the level constantly detected on CLK line is low level, if it is low level, is controlled
CLK pin exports the low level of 25 microseconds, while reading the position data on DATA line, and after 25 microseconds, control CLK pin output is high
Level is as response；
Transmitting terminal, control CLK pin export high level, constantly read the level on CLK line within a preset time and judge whether
For high level, that is, judge whether that all receiving ends have all been replied, if it is high level, further whether judges 8 bit datas
All it is sent completely；
Receiving end constantly reads the level on CLK line within a preset time and judges whether it is high level, that is, judges universal serial bus
On other terminals whether all replied, if it is high level, further judge whether 8 bit datas all finish receiving.
5. the communication system according to claim 4 based on universal serial bus, which is characterized in that the transmitting terminal and/or connect
Receiving end discharges universal serial bus, comprising:
The either described transmitting terminal or the receiving end, release universal serial bus are all control BUSY pin output high level, control
CLK pin processed exports high level, control DATA pin exports low level.
6. a kind of communication means based on universal serial bus, which is characterized in that the described method includes:
Close bus interrupt mechanism, according to the level on the BUSY line of reading, CLK line, decide universal serial bus state whether be
It is idle；
When the state of the universal serial bus is idle, byte-by-byte transmission byte data according to the preset time interval, wherein hair
Send the process of each byte data are as follows: control BUSY pin exports low level, i.e., BUSY is set to low level by high level, when true
Determining DATA is high level, i.e., DATA has all been set to after high level responds by all receiving ends, in the failing edge of CLK, is passed through
DATA sends the position data in byte by turn, when sending next bit data, it is ensured that the CLK of receiving end return has been received
For the answer signal of high level, in judgement after sending each byte data there are also when not sent byte data, control DATA is managed
Foot exports high level, CLK pin output low level, BUSY pin and exports high level；
After all byte datas are sent completely, universal serial bus is discharged, and open bus interrupt mechanism.
7. a kind of communication means based on universal serial bus according to claim 6, which is characterized in that described according to reading
Level on BUSY line, CLK line decides whether the state of universal serial bus is idle, comprising:
BUSY line, the level on CLK line are constantly read within a preset time, until the level on BUSY line and CLK line is all high
Level, the i.e. state of determination of serial bus are the free time, if it exceeds the preset time, then decide the state of the universal serial bus
To occupy；
After the state of previous step universal serial bus is determined as the free time, control BUSY pin exports low level, at one section of random delay
Between, control BUSY pin exports high level, constantly reads BUSY line, the level on CLK line in the preset time again, directly
Level on to BUSY line and CLK line is all high level, and the state of ability absolute decree universal serial bus is the free time, otherwise described in ruling
The state of universal serial bus is to occupy.
8. a kind of communication means based on universal serial bus according to claim 6 or 7, which is characterized in that described according to pre-
If the byte-by-byte transmission byte data of time interval, comprising:
The following steps are repeated, until all byte datas are all sent completely: sending a byte data, judge whether own
Byte data is all sent completely, if the time interval that is delayed without if.
9. a kind of communication means based on universal serial bus, which is characterized in that the described method includes:
Level on real-time monitoring BUSY line, when detecting that the level on BUSY line becomes low level by high level, then triggering is total
Line interrupts, and pause handles other tasks；
BUSY is confirmed for after low level, DATA is set to high level as response；
When CLK is low level, CLK is set to high level after reading every bit data by the position data read on DATA one by one
As response,
After having received a byte data, the universal serial bus is discharged, and opens bus interrupt mechanism, then continues with it
Its task.
10. a kind of communication means based on universal serial bus according to claim 9, which is characterized in that it is described CLK be it is low
When level, the position data on DATA are read one by one, and after reading every bit data, CLK is set to high level as response, packet
It includes:
Within a preset time, whether the level constantly on detection CLK line is low level, if it is low level, controls CLK pin
The low level of 25 microseconds is exported, while reading the position data on DATA line, after 25 microseconds, control CLK pin output high level is made
For response, the level on CLK line is constantly read within a preset time and judges whether it is high level, that is, is judged on universal serial bus
Whether other terminals have all replied, and if it is high level, further judge whether 8 bit datas all finish receiving, if fruit does not have
Have, then repeat above-mentioned steps, until 8 bit datas all finish receiving.
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