CN102929830A - Software simulation rapid communication protocol - Google Patents
Software simulation rapid communication protocol Download PDFInfo
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- CN102929830A CN102929830A CN2012104445912A CN201210444591A CN102929830A CN 102929830 A CN102929830 A CN 102929830A CN 2012104445912 A CN2012104445912 A CN 2012104445912A CN 201210444591 A CN201210444591 A CN 201210444591A CN 102929830 A CN102929830 A CN 102929830A
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Abstract
A software simulation rapid communication protocol comprises a host end for sending data and a slave end for receiving data, wherein a clock line for transmitting a clock signal and a data line for transmitting data are arranged between the host end and the slave end; a handshake line is arranged between the host end and the slave end, the slave end processes the clock signal from the host end to form a response signal, and the response signal is fed back to the host end through the handshake line; the host end transmits data to the slave end after receiving the response signal; the synchronous communication between the host end and the slave end through the handshake line comprises an initial stage; a data transmission stage; and (5) finishing the stage. The invention has the advantages of determining the preparation state of the data receiving end and improving the communication speed.
Description
Technical field
The present invention relates to the communication protocol between a kind of chip.
Background technology
Communication protocol (communications protocol) refers to that both sides' entity finishes the mandatory rule of communication or service institute and agreement.Protocol definition the form that uses of data cell, the information that message unit should comprise and implication, connected mode, the sequential of information sending and receiving, thus guarantee that data successfully are sent to definite place in the network.At present, the communication protocol that is usually used in chip comprises I2C, SPI, UART etc.
The I2C bus is a kind of for the bidirectional two-line that connects between IC device bus processed, and so-called I2C bus can be hung a plurality of devices above it, and logical two lines connect, very little of taking up room, and maximum transfer speed can reach 300Kbit/s.
The I2C bus has two signal wires, and one is the SDA(data line), one is the CLK(clock line).Whenever clock signal all is to be produced by the master control device.
The I2C bus mainly contains three kinds of control signals: start signal, end signal in the process that transmits data.Start signal: when CLK is high level, when SDA transfers low level to by high level, begin to transmit data.End signal: when CLK was high level, when SDA transferred high level to by low level, end data transmitted.
SPI communication protocol adds 1 CS chip select line by 3 signals and realizes full-duplex communication, can obtain 2 times of communication speeds that I2C communicates by letter when two biographies are the same with the downloading data amount.
SPI, UART both can realize half-duplex operation, also can realize full-duplex communication.
The shortcoming of these communication protocols is: because communication speed is controlled to be open loop control, when the slave end does not have the hardware communications port support and communicates by letter with software simulation, can't whether carry out the reception preparation by the specified data receiving end, therefore must reserve the time enough surplus when designing and guarantee that communication correctly carries out, thereby cause the degradation of communication speed.
Summary of the invention
Can't whether carry out the reception preparation by the specified data receiving end in order to overcome the existing software simulation communication technology, the shortcoming that communication speed is slow, the invention provides a kind of standby condition that can the specified data receiving end, can improve the software simulation fast communication protocols of communication speed.
A kind of software simulation fast communication protocols comprises the host side that sends data and the slave end of receive data, is provided with the clock line of transmission clock signal between host side and the slave end and transmits the data line of data;
It is characterized in that: be provided with handshaking line between host side and the slave end, the slave end will be processed from the clock signal of host side and form answer signal, and answer signal feeds back to host side through handshaking line; Host side receives the backward slave end of answer signal and carries out data transmission;
Host side and slave end comprise with the next stage by the handshaking line synchronous communication:
1), initial period: the clock signal that host side is sent becomes low level by high level, the slave termination is received this clock signal, the slave end is set to low level with initial high level, this high level is to the answer signal of low level variable signal as initial period, the answer signal of initial period is inputted host side through handshaking line, host side is set to low level with data line after receiving this answer signal, and handshaking line is set to high level;
2), data transfer phase: host side is sent the clock signal of rule, the clock signal that slave end monitoring host side is sent, when the level of clock signal changes, the slave end sends the transmit stage answer signal opposite with clock signal, and the transmit stage answer signal inputted host side by handshaking line; Then carry out next data transmission if host side receives the transmit stage answer signal, then do not think data transmission exception if host side receives the transmit stage answer signal;
3), ending phase:
As shown above, host side CLK line is in high level, the slave end detects the rear generation handshake opposite with CLK, host side detects after the state of slave end, DATA line level is produced a level saltus step from low to high, the slave end after detecting this signal is drawn high handshaking line, and this moment is just the same with host side clock line level, has so just finished a complete STOP signal.
Further, step 2) in, when the level saltus step from low to high of clock signal, the slave end sends the level signal by on earth saltus step of height; When the level of clock signal from high to low during saltus step, the slave end sends the level signal of saltus step from low to high; The skip signal that the slave end sends is as the transmit stage answer signal.
Technical conceive of the present invention is: by setting up a handshaking line between host side and slave end, the slave termination is received in time to make to host side after the clock signal that host side sends and is replied, makes host side can grasp in real time the standby condition of slave end.The required call duration time of normal corresponding signal is very short because slave is rectified, and response time is set aside some time much smaller than open loop control mode, therefore can improve in a large number communication speed.
The present invention have can the specified data receiving end standby condition, can improve the advantage of communication speed.
Description of drawings
Synoptic diagram when Fig. 1 is half-duplex operation of the present invention.
Synoptic diagram when Fig. 2 is full-duplex communication of the present invention.
Fig. 3 is the oscillogram that the present invention exports.
Embodiment
With reference to accompanying drawing, further specify the present invention:
A kind of software simulation fast communication protocols comprises the host side MCU1 that sends data and the slave end MCU2 of receive data, is provided with the clock line CLK of transmission clock signal between host side MCU1 and the slave end MCU2 and transmits the data line SDA of data;
Be provided with handshaking line between host side MCU1 and the slave end MCU2
Slave end MCU2 will process from the clock signal of host side MCU1 and form answer signal, and answer signal feeds back to host side MCU1 through handshaking line CLK; Host side MCU1 receives the backward slave end of answer signal MCU2 and carries out data transmission;
Host side MCU1 and slave end MCU2 pass through handshaking line
Synchronous communication comprises with the next stage, as shown in Figure 3:
1), the clock signal sent of initial period Start: host side MCU1 becomes low level by high level, slave end MCU2 receives this clock signal, slave end MCU2 is set to low level with initial high level, this high level is to the answer signal of low level variable signal as initial period, the answer signal of initial period is through handshaking line CLK input host side MCU1, host side MCU1 is set to low level with data line SDA after receiving this answer signal, and with handshaking line
Be set to high level;
2), data transfer phase Data: host side MCU1 sends the clock signal of rule, the clock signal that slave end MCU2 monitoring host side MCU1 sends, when the level of clock signal changes, slave end MCU2 sends the transmit stage answer signal opposite with clock signal, and the transmit stage answer signal passed through handshaking line
Input host side MCU1; Then carry out next data transmission if host side MCU1 receives the transmit stage answer signal, then do not think data transmission exception if host side MCU1 receives the transmit stage answer signal;
3), ending phase Stop: when the clock signal saltus step from low to high of data line SDA during at high level, host side MCU1, with this skip signal as end signal; Slave end MCU2 receives handshaking line behind the end signal
Continue high level, no longer send answer signal;
Step 2) in, when the level saltus step from low to high of clock signal, slave end MCU2 sends the level signal by on earth saltus step of height; When the level of clock signal from high to low during saltus step, slave end MCU2 sends the level signal of saltus step from low to high; The skip signal that slave end MCU2 sends is as the transmit stage answer signal.
The present invention can arrange 3 signal wires and realize half-duplex operation, as shown in Figure 1.4 signal wires also can be set realize full-duplex communication, as shown in Figure 2.
Technical conceive of the present invention is: by set up a handshaking line between host side MCU1 and slave end MCU2
Slave end MCU2 in time passes through handshaking line after receiving the clock signal that host side MCU1 sends
Make to host side MCU1 and to reply, make host side MCU1 can grasp in real time the standby condition of slave end MCU2.Owing to the call duration time that slave end MCU2 normal phase induction signal is required is very short, response time is set aside some time much smaller than open loop control mode, therefore can improve in a large number communication speed.
Step 2) compares with traditional I2C agreement, because traditional I2C agreement is the open loop control protocol, so in order to confirm that whether data are rectified really reception by slave, need to produce an ack signal and are used for replying; And the present invention need not to produce ack signal, get final product so only need transmit 8bit when transmitting the data of 8bit, and traditional I2C agreement need to be transmitted 8bit+ACK(1bit).The data volume of the present invention's transmission also is starkly lower than traditional open loop control protocol.
The present invention have can the specified data receiving end standby condition, can improve the advantage of communication speed.
The described content of this instructions embodiment only is enumerating the way of realization of inventive concept; protection scope of the present invention should not be regarded as only limiting to the concrete form that embodiment states, protection scope of the present invention also reaches in those skilled in the art conceives the equivalent technologies means that can expect according to the present invention.
Claims (2)
1. software simulation fast communication protocols comprises the host side that sends data and the slave end of receive data, is provided with the clock line of transmission clock signal between host side and the slave end and transmits the data line of data;
It is characterized in that: be provided with handshaking line between host side and the slave end, the slave end will be processed from the clock signal of host side and form answer signal, and answer signal feeds back to host side through handshaking line; Host side receives the backward slave end of answer signal and carries out data transmission;
Host side and slave end comprise with the next stage by the handshaking line synchronous communication:
1), initial period: the clock signal that host side is sent becomes low level by high level, the slave termination is received this clock signal, the slave end is set to low level with initial high level, this high level is to the answer signal of low level variable signal as initial period, the answer signal of initial period is inputted host side through handshaking line, host side is set to low level with data line after receiving this answer signal, and handshaking line is set to high level;
2), data transfer phase: host side is sent the clock signal of rule, the clock signal that slave end monitoring host side is sent, when the level of clock signal changes, the slave end sends the transmit stage answer signal opposite with clock signal, and the transmit stage answer signal inputted host side by handshaking line; Then carry out next data transmission if host side receives the transmit stage answer signal, then do not think data transmission exception if host side receives the transmit stage answer signal;
3), ending phase: when the clock signal saltus step from low to high of data line during at high level, host side, with this skip signal as end signal; Handshaking line continued high level after the slave termination was received end signal, no longer sent answer signal.
2. software simulation fast communication protocols as claimed in claim 1 is characterized in that: step 2) in, when the level saltus step from low to high of clock signal, the slave end sends the level signal by on earth saltus step of height; When the level of clock signal from high to low during saltus step, the slave end sends the level signal of saltus step from low to high; The skip signal that the slave end sends is as the transmit stage answer signal.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838700A (en) * | 2014-02-20 | 2014-06-04 | 江苏理工学院 | Level multiplexing control serial communication device and method |
| CN108804372A (en) * | 2018-06-21 | 2018-11-13 | 青岛海信电器股份有限公司 | Control method, device and the display device of the V-by-One interfaces of display device |
| CN109582616A (en) * | 2018-12-05 | 2019-04-05 | 张洋 | Communication system and method based on universal serial bus |
| CN109960672A (en) * | 2017-12-22 | 2019-07-02 | 苏州迈瑞微电子有限公司 | A kind of digital communication method based on GPIO interface |
| CN112286854A (en) * | 2020-10-12 | 2021-01-29 | 杭州德旺信息技术有限公司 | Multiplexing system, method and storage medium for UART interface and SPI interface |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
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| JPH06243052A (en) * | 1993-02-18 | 1994-09-02 | Fuji Photo Film Co Ltd | Serial communication error processing method |
| JP2003163653A (en) * | 2001-11-28 | 2003-06-06 | Yokogawa Electric Corp | Serial data communication method |
| CN1902580A (en) * | 2004-01-13 | 2007-01-24 | 皇家飞利浦电子股份有限公司 | Electronic circuit with a FIFO pipeline |
| CN101803269A (en) * | 2007-09-18 | 2010-08-11 | 兴和株式会社 | Serial data communication system and serial data communication method |
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2012
- 2012-11-08 CN CN2012104445912A patent/CN102929830A/en active Pending
Patent Citations (4)
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| JPH06243052A (en) * | 1993-02-18 | 1994-09-02 | Fuji Photo Film Co Ltd | Serial communication error processing method |
| JP2003163653A (en) * | 2001-11-28 | 2003-06-06 | Yokogawa Electric Corp | Serial data communication method |
| CN1902580A (en) * | 2004-01-13 | 2007-01-24 | 皇家飞利浦电子股份有限公司 | Electronic circuit with a FIFO pipeline |
| CN101803269A (en) * | 2007-09-18 | 2010-08-11 | 兴和株式会社 | Serial data communication system and serial data communication method |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838700A (en) * | 2014-02-20 | 2014-06-04 | 江苏理工学院 | Level multiplexing control serial communication device and method |
| CN109960672A (en) * | 2017-12-22 | 2019-07-02 | 苏州迈瑞微电子有限公司 | A kind of digital communication method based on GPIO interface |
| CN109960672B (en) * | 2017-12-22 | 2022-12-30 | 苏州迈瑞微电子有限公司 | Digital communication method based on GPIO interface |
| CN108804372A (en) * | 2018-06-21 | 2018-11-13 | 青岛海信电器股份有限公司 | Control method, device and the display device of the V-by-One interfaces of display device |
| CN108804372B (en) * | 2018-06-21 | 2020-05-05 | 海信视像科技股份有限公司 | Control method and device for V-by-One interface of display device and display device |
| CN109582616A (en) * | 2018-12-05 | 2019-04-05 | 张洋 | Communication system and method based on universal serial bus |
| CN109582616B (en) * | 2018-12-05 | 2020-07-17 | 北京爱其科技有限公司 | Communication system and method based on serial bus |
| CN112286854A (en) * | 2020-10-12 | 2021-01-29 | 杭州德旺信息技术有限公司 | Multiplexing system, method and storage medium for UART interface and SPI interface |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
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