CN109960672B - Digital communication method based on GPIO interface - Google Patents

Digital communication method based on GPIO interface Download PDF

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Publication number
CN109960672B
CN109960672B CN201711409298.1A CN201711409298A CN109960672B CN 109960672 B CN109960672 B CN 109960672B CN 201711409298 A CN201711409298 A CN 201711409298A CN 109960672 B CN109960672 B CN 109960672B
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module
signal
gpio interface
bit
level
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CN109960672A (en
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李扬渊
卞维军
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Microarray Microelectronics Corp ltd
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Microarray Microelectronics Corp ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link

Abstract

The embodiment of the invention provides a GPIO interface-based digital communication method, wherein a first GPIO interface of a first module is connected with a second GPIO interface of a second module to realize communication between the first module and the second module; the transmission signals include handshake signals and data signals, the handshake signals are larger than one Bit time of the data signals to distinguish between the bits and the handshake signals, one Bit is composed of a first level and a second level, and the Bit values are distinguished by the proportion of the first level to the one Bit time.

Description

Digital communication method based on GPIO interface
Technical Field
The invention relates to the field of GPIO interface communication.
Background
UART and I are commonly used for communication between modules of communication system 2 C, etc. interface, and adopting UART or I 2 C protocol communication, it may appear that one of the master or slave does not have UART or I 2 C interface, therefore the master or slave needs to emulate UART or I 2 C, and it is often difficult to program a UART or I from the slave side 2 C。
Disclosure of Invention
The invention discloses a digital communication method based on GPIO interfaces, wherein a first GPIO interface of a first module is connected with a second GPIO interface of a second module to realize the communication between the first module and the second module;
when the data is in an idle state, the first module continuously outputs a first level to the second GPIO interface;
when the data transmission state is established, the signals output by the first module comprise handshake signals and data signals, and each Bit time of the data signals is t 0 ；
The data transmission comprises the following steps:
1) Handshake signaling: the first module outputs a handshake signal to the second module, wherein the handshake signal comprises a second level of a preset time t, and t is greater than t 0 ；
2) Data signal transmission: the first block outputs a data signal to the second block, each Bit of the data signal is composed of a first level and a second level, each Bit is sandwiched between two adjacent rising edges or each Bit is sandwiched between two adjacent falling edges, the first level time t1 and the time t in one Bit 0 A, a predetermined value a 0 A is greater than a 0 Or a is less than a 0 And determining a Bit value according to the comparison result.
The GPIO interface is used for communication among the modules of the electronic system, is relatively abundant, solves the problem of insufficient interface and meets the requirement of low-speed communication. The invention also provides a corresponding communication method, wherein the GPIO is utilized to transmit digital signals, and handshake signals and data signals are transmitted through the GPIO interface without an additional external programming device.
Drawings
Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of communication signals according to a first embodiment of the invention.
Fig. 3 is a schematic diagram of communication signals according to a second embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As shown in fig. 1, the communication system of the present invention includes a first module and a second module, where the first module and the second module may be mcu, and may be in a master-slave relationship, for example, the first module is a master, the second module is a slave, or may not be in a master-slave relationship. And the first GPIO interface of the first module is connected with the second GPIO interface of the second module to realize communication between the first module and the second module. The communication signal is realized by level change, and the level comprises a first level and a second level. The first module and the second module can adopt single-wire transmission or double-wire transmission.
Example one
As shown in fig. 2, in the idle state of data, the first module continuously outputs the first level to the second GPIO interface, where the first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level. The second module is always in a state of online reception of receivable data or in a state of triggerable interrupt.
When the data is in a transmission state, the signals output by the first module comprise handshake signalsA signal and a data signal, said data signal having a time t per Bit 0 ；
The data transmission comprises the following steps:
1) Handshake signaling: the first module outputs a handshake signal to the second module, the handshake signal includes a second level for a predetermined time t, t is greater than t 0 Since the handshake signal time is longer than the time of one Bit, it is advantageous to distinguish between the handshake signal and the Bit of the data signal. When the second module is in the state of receiving on-line all the time in the scheme, directly entering step 2), when the second module is in the state of being capable of triggering interruption in the scheme, the second module receives the jump of the handshake signals from the first level to the second level, and then enters step 2) to be switched to the state of receiving on-line.
2) Data signal transmission: the first block outputs a data signal to the second block, each Bit of the data signal being composed of a first level and a second level, each Bit being sandwiched between two adjacent rising edges or each Bit being sandwiched between two adjacent falling edges, the first level time t in one Bit being 1 And time t 0 A, a predetermined value a 0 A is greater than a 0 Or a is less than a 0 And determining a Bit value according to the comparison result. A is the 0 Preferably 50%, it will be understood that the skilled person will a 0 Adjusted to other values, e.g., 40%,60%, etc., and in one arrangement, bit1 is such that a is greater than a 0 Bit0 is a is less than a 0 Bit of (2); in another scheme, bit1 is that a is less than a 0 Bit0 is a is larger than a 0 Bit of (1).
Example two
The second embodiment is different from the first embodiment in that the second module is not always in the online receiving state or can trigger the interrupt state, for example, the second module is in the sleep state or the busy state, and cannot receive the data signal sent by the first module temporarily, so after the first module starts sending the handshake signal, it is necessary to wait for the second module to confirm that the signal can be received, and the first module can send the data signal after receiving the signal to be received sent by the second module.
The method comprises the following specific steps:
as shown in fig. 3, in the idle state of data, the first module continuously outputs the first level to the second GPIO interface, and the second module continuously outputs the first level to the first GPIO interface.
In a data transmission state, signals output by the first module comprise handshake signals and data signals, and each Bit time of the data signals is t 0 ；
The data transmission comprises the following steps:
1) Handshake signaling: the first module outputs a handshake signal to the second module, wherein the handshake signal comprises a second level of a preset time t, and t is greater than t 0 (ii) a When the second level of the handshake signal lasts for t ', if the second module is in a state of being capable of receiving the data signal, the second module outputs a signal to be received, wherein t' is greater than or equal to t 0 And if the signal to be received is a jump from the first level to the second level, or the signal to be received is the second level of the preset time, the first module receives the signal to be received, and the step 2) is carried out after the output of the handshake signal is finished. If the second module is in a state of being incapable of receiving the data signal, the signal to be received is not sent to the second module, and the first module can send a handshake signal to the second module periodically to request to send the data signal.
2) Data signal transmission: the first block outputs a data signal to the second block, each Bit of the data signal is composed of a first level and a second level, each Bit is sandwiched between two adjacent rising edges or each Bit is sandwiched between two adjacent falling edges, the first level time t1 and the time t in one Bit 0 A, a predetermined value a is set 0 A is greater than a 0 Or a is less than a 0 And determining a Bit value according to the comparison result. A is the 0 Preferably 50%, it will be understood by those skilled in the art that 0 Adjusted to other values, e.g., 40%,60%, etc., in one embodiment, bit1 is a Bit with a greater than a0, and Bit0 is a Bit with a less than a 0 Bit of (2); in another scheme, bit1 is that a is less than a 0 Bit0 is a is larger than a 0 Bit of (1).
EXAMPLE III
This embodiment is a specific application of the first embodiment and the second embodiment.
The embodiment of the invention is particularly suitable for electronic equipment with an identity authentication module, such as a U disk, a U shield, an electronic lock and the like, wherein the identity authentication module can be a fingerprint authentication module, an iris authentication module, a face recognition module and the like, and the communication method of the electronic system is specifically described below by using the U disk with the fingerprint authentication module.
The fingerprint authentication module can include fingerprint authentication mcu and fingerprint sensor, and fingerprint authentication mcu connects fingerprint sensor, and fingerprint authentication mcu can control fingerprint sensor, for example can control fingerprint sensor's mode, and fingerprint authentication mcu can also handle the finger information that fingerprint sensor detected to handle this information with authentication fingerprint etc. fingerprint sensor can be any type of fingerprint sensor, such as capacitanc, optical type, ultrasonic wave formula fingerprint sensor. The U disk comprises a U disk mcu, and the U disk mcu can control reading and storing of the U disk and unlocking of the U disk. Preferably, the usb disk mcu is connected to and communicates with a fingerprint authentication mcu, where the fingerprint authentication mcu corresponds to the second module, hereinafter referred to as a slave, and the usb disk mcu corresponds to the first module, hereinafter referred to as a master.
The host computer and the slave computer are connected through respective GPIO interfaces to realize communication.
After receiving the trigger event, the host or the slave sends a data signal to the opposite side by adopting the mode of the first embodiment or the second embodiment, for example, when the host receives a registration fingerprint or a fingerprint authentication instruction of a user, the host sends the data signal to the slave for fingerprint registration; when the slave computer receives a signal of the finger touching the fingerprint sensor or the fingerprint information is successfully matched, the slave computer sends a data signal to the host computer, the triggering events are not limited to the above types, and the triggering events can be set according to requirements.
For embodiments one, two, and three, the data signal includes, for example, a four bit header bit segment, a four bit command bit segment, a four bit data bit segment, and a four bit check bit segment. Taking the case that the master sends data to the slave, the head bit field indicates that the sending direction is from the master to the slave, and the command bit field can indicate command instructions for setting a fingerprint working mode, reading a fingerprint ID index table, fingerprint registration and the like; the data bit field indicates the parameters of the command, such as what fingerprint working mode is set; the check bits are used to check the correctness of the data, and only if the data is checked to be correct is a correct data, preferably, the first three bit segments are subjected to the exclusive-or check sequentially by using BCC (exclusive-or check).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (7)

1. A digital communication method based on GPIO interface is characterized in that a first GPIO interface of a first module is connected with a second GPIO interface of a second module to realize the communication between the first module and the second module; when the data is in an idle state, the first module continuously outputs a first level to the second GPIO interface;
when the data transmission state is established, the signals output by the first module comprise handshake signals and data signals, and each Bit time of the data signals is t 0 ；
The data transmission comprises the following steps:
1) Handshake signaling: the first module outputs a handshake signal to the second module, the handshake signal includes a second level for a predetermined time t, t is greater than t 0 ；
2) Data signal transmission: the first block outputs a data signal to the second block, each Bit of the data signal consisting of a first level and a second level, each Bit being sandwiched between two adjacent rising edges or each Bit being sandwiched between two adjacent falling edges, one Bit at the first levelTime t 1 And time t 0 A, a predetermined value a 0 A is greater than a 0 Or a is less than a 0 And determining a Bit value according to the comparison result.
2. The GPIO interface-based digital communication method of claim 1, wherein a is 0 Is 50%.
3. The GPIO interface-based digital communication method as claimed in claim 1 or 2, wherein the second module is always in a receive on-line state or in a triggerable interrupt state.
4. The GPIO interface-based digital communication method of claim 1 or 2, wherein in step 1), if the second level of the handshake signal lasts for t ', and the second module is in a state of being able to receive the data signal, the second module outputs a signal to be received, and t' is greater than or equal to t 0 When the first module receives the signal to be received and the output of the handshake signal is finished, step 2) is carried out.
5. The GPIO interface-based digital communication method of claim 4, wherein in step 1), if the second module is in a state of not being able to receive the data signal, the second module does not send the signal to be received to the second module, and the first module periodically sends a handshake signal to the second module to request the data signal to be sent.
6. The GPIO interface-based digital communication method of any one of claims 1-2,5, wherein the second module is a mcu of a fingerprint authentication module.
7. The GPIO interface-based digital communication method of any one of claims 1-2,5, wherein the first module is a USB flash drive, an electric vehicle or a mcu of an electronic lock.
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Publication number Priority date Publication date Assignee Title
CN112363962A (en) * 2020-10-30 2021-02-12 深圳市汇顶科技股份有限公司 Data communication method, system, electronic device and computer storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727370A (en) * 1985-12-17 1988-02-23 Ampex Corporation Method and system for synchronous handshake generation
CN102929830A (en) * 2012-11-08 2013-02-13 浙江绍兴苏泊尔生活电器有限公司 Software simulation rapid communication protocol
WO2017050234A1 (en) * 2015-09-21 2017-03-30 天地融科技股份有限公司 Data transmission method and data processing device
CN107220198A (en) * 2017-06-22 2017-09-29 深圳天珑无线科技有限公司 Communication terminal and mongline two-way communication system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727370A (en) * 1985-12-17 1988-02-23 Ampex Corporation Method and system for synchronous handshake generation
CN102929830A (en) * 2012-11-08 2013-02-13 浙江绍兴苏泊尔生活电器有限公司 Software simulation rapid communication protocol
WO2017050234A1 (en) * 2015-09-21 2017-03-30 天地融科技股份有限公司 Data transmission method and data processing device
CN107220198A (en) * 2017-06-22 2017-09-29 深圳天珑无线科技有限公司 Communication terminal and mongline two-way communication system

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