CN113242168B - Single bus communication method - Google Patents

Single bus communication method Download PDF

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Publication number
CN113242168B
CN113242168B CN202110425344.7A CN202110425344A CN113242168B CN 113242168 B CN113242168 B CN 113242168B CN 202110425344 A CN202110425344 A CN 202110425344A CN 113242168 B CN113242168 B CN 113242168B
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bus
dsl
signal
communication
master device
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CN113242168A (en
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许利凯
罗军
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Hebei Stability Control Technology Co ltd
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Hebei Stability Control Technology Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/4013Management of data rate on the bus

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a single bus communication method, which comprises the following steps: connecting a plurality of devices to a DSL bus through a single data line, and setting all the devices to adopt open-drain output; optionally selecting one piece of equipment as master equipment, using the other pieces of equipment as slave equipment, sending a communication starting signal to a DSL bus by using the master equipment, and establishing communication connection with the expected slave equipment; the master device outputs various signals for controlling the DSL bus, and combines the various signals for controlling the DSL bus to form various operation states, and the master device and the slave device carry out data interaction according to a set operation mode; the invention uses a single communication line, dynamically synchronizes the communication speed, can reduce the core number of the communication cable during remote communication, ensures the self-adaptation of signal time sequence to the cable parameter, effectively reduces the material cost, increases the communication distance and dynamically synchronizes the communication speed.

Description

Single bus communication method
Technical Field
The invention relates to the technical field of data communication, in particular to a single bus communication method.
Background
The most commonly used serial buses include UART, SPI, I2C, CAN, USB, etc., and the 1Wire bus is also a single communication line interface protocol, and has been widely used, but this bus has the disadvantages of fixed communication rate and high time slot requirement in signal timing sequence, and cannot implement near field communication, while the serial communication protocols such as UART and USB have the problems of rate non-allocation, high error rate and even code confusion caused by the difference of respective clocks of both communication parties.
Disclosure of Invention
The invention aims to provide a single bus communication method to solve the technical problems of no rate configuration, high error rate and even messy codes in the prior art.
In order to solve the technical problems, the invention specifically provides the following technical scheme:
a single bus communication method comprises the following steps:
step 100, connecting a plurality of devices to a DSL bus through a single data line, and setting all the devices to adopt open-drain output;
200, selecting one piece of equipment as a master equipment and the rest as slave equipment, sending a communication starting signal to the DSL bus by using the master equipment, and establishing communication connection with the expected slave equipment;
step 300, the master device outputs various signals for controlling the DSL bus, and combines the various signals for controlling the DSL bus operation state to form various operation states, and the master device and the slave device perform data interaction according to a set operation mode.
As a preferred scheme of the present invention, in step 100, all devices connected to the DSL bus are respectively provided with a unique ID code, and all devices are divided into a master device or a slave device, where the master device is responsible for initiating a communication start signal and controlling the whole communication process, and the slave device is configured to monitor and detect the communication start signal on the DSL bus;
the master device and the slave device can receive and send data in the communication process, the master device which is sending data is called a sender, and the slave device which is receiving data is called a receiver;
when the DSL bus is free of communication signals, all the devices connected to the DSL bus are slave devices, and any one slave device can be converted into a master device to initiate a communication process.
As a preferable scheme of the present invention, in step 100, an and gate relationship exists between the output level signals of the master device and the slave device and the total level signal of the DSL bus, and when any one device outputs a low level signal, the DSL bus is pulled down, and only if all devices output high level signals, the DSL bus outputs a high level signal correspondingly.
As a preferable aspect of the present invention, each of the master device and the slave device has an open-drain output detection function and an open-drain input detection function, the master device and the slave device are switched to an output state to control an operation state of the DSL bus, and the slave device and the master device are switched to an input state to detect a level state of the DSL bus.
As a preferred aspect of the present invention, in step 200, the DSL bus takes a time period T for transmitting one byte of dataBASECalled bit duration, and TBASEThe minimum signal time sequence of the communication protocol of the DSL bus is the signal time sequence of the combination of a single low-level signal and a single high-level signal, and the holding time length of the high-level signal is always less than or equal to the holding time length of the low-level signal in the data communication process;
the minimum unit of the transmission data of the DSL bus is a byte, and when the DSL bus transmits data, the high bit is transmitted first and then the low bit is transmitted.
As a preferred aspect of the present invention, in step 300, the master device outputs a plurality of signals for controlling the DSL bus operation state, including an idle signal, a reset signal, an acknowledgement signal, and a non-acknowledgement signal;
the main device sends an idle signal to the DSL bus, where the low-level signal holding duration is less than that of an adjacent high-level signal, and the high-level signal holding duration is greater than 3 times the low-level signal holding duration, and the DSL bus is in an idle state, that is, communication of the DSL bus is terminated, and when the DSL bus communicates again, the DSL bus must start with a reset signal.
The master device sends a time sequence signal to the DSL bus, wherein the duration of the low level signal is less than the duration of the adjacent high level signal, the duration of the high level signal is 1.5-2 times of the duration of the low level signal, the DSL bus is in a reset state, and the slave device updates the self communication bit duration T after detecting the reset signalBASEContinuing to receive subsequent data according to the updated bit duration;
the receiver controls the DSL bus to output a response signal after receiving one byte of data, and the low level of the response signal keeps TBASEThereafter, high holding TBASE
The receiver controls the DSL bus to output a non-response signal after receiving one byte of data, and the low level of the response signal keeps TBASE2, high level hold T thereafterBASE
As a preferred aspect of the present invention, when the DSL bus is in the idle state, all devices connected to the DSL bus wait for a reset signal, and all devices do not respond to any signal other than the reset signal;
the slave device detects a reset signal on the DSL bus and completes TBASEUpdating, and the slave device waits for the master device to send a slave device ID for authentication communication;
the master device and the slave device corresponding to the ID code establish a communication relationship, the slave device detects a continuous starting signal on the DSL bus and the ID of the slave device is consistent with the ID of the slave device, the master device sends a completion starting signal and a target ID and receives a response signal of the corresponding slave device, and the master device and the slave device corresponding to the ID code are in a matching state until the communication is finished or the communication is overtime.
As a preferred scheme of the present invention, after the DSL bus is reset, the master device must send a slave device ID for communication, and a last byte for regulating read and write operations of the master device is carried in the slave device ID, and when the last byte is 0, the master device sends byte data to the slave device, and when the last byte is 1, the master device is configured to read the byte data sent by the slave device.
As a preferred scheme of the present invention, when a last byte is 0, the master device continuously writes transmission byte data to the slave device, and the specific implementation steps are as follows:
the master device sends a communication starting signal to the DSL bus;
the master device sends a target ID to the DSL bus, and the last byte is 0, releases the DSL bus and waits for a response signal of the slave device;
the main equipment takes over the DSL bus again after receiving the response signal until the main equipment finishes the communication when receiving the non-response signal;
the master device sends byte data to the slave device and waits for a response signal returned by the slave device after sending one byte.
And after the master device finishes sending the last byte and receives a response signal sent by the slave device, the master device sends an idle signal for finishing communication to the DSL bus.
As a preferred scheme of the present invention, when a last byte is 1, the master device continuously reads byte data sent by the slave device, and the specific implementation steps are as follows:
the master device sends a communication starting signal to the DSL bus;
the master device sends a target ID to the DSL bus, the last byte of the target ID is 1, the DSL bus is released, and a response signal of the slave device is waited;
the master device continues to receive the byte data sent by the slave device after receiving the response signal, and takes over the DSL bus after receiving one byte data each time;
the master device sends an acknowledgement signal to the DSL bus and releases the bus.
And after receiving one byte, the main equipment sends a non-response signal to the bus and does not receive byte data any more, and the communication is finished.
Compared with the prior art, the invention has the following beneficial effects:
the DSL bus interface protocol provided by the invention uses a single communication line, dynamically synchronizes the communication speed, can reduce the core number of the communication cable while performing remote communication, ensures the self-adaption of signal time sequence to cable parameters, effectively reduces the material cost, increases the communication distance and dynamically synchronizes the communication speed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
Fig. 1 is a flowchart illustrating a single bus communication method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides a single bus communication method, which specifically includes the following steps:
step 100, connecting a plurality of devices to a DSL bus through a single data line, and setting all the devices to adopt open-drain output.
In step 100, all devices connected to the DSL bus are respectively provided with a unique ID code, and all devices are divided into a master device or a slave device, where the master device is responsible for initiating a communication start signal and controlling the whole communication process, and the slave device is configured to monitor and detect the communication start signal on the DSL bus.
The master device and the slave device can both receive and transmit data during communication, the master device which is transmitting data is called a transmitter, and the slave device which is receiving data is called a receiver.
When the DSL bus is free of communication signals, all the devices connected to the DSL bus are slave devices, and any one slave device can be converted into a master device to initiate a communication process.
In particular, the controlling party of the DSL bus (i.e. the master) has to actively pull down the DSL bus (i.e. output a low signal) after sending a signal and keep at least 0.2TBASETime length, if the identities of the master equipment and the slave equipment need to be switched, the 0.2TBASEThe time gap is used to switch the identities of the master and slave devices, and the DSL bus is taken over by the new master device, so the party taking over the DSL bus must first output a low signal.
And an AND gate relationship exists between the output level signals of the master device and the slave device and the total level signal of the DSL bus, when any one device outputs a low level signal, the DSL bus is pulled down, and only if all the devices output high level signals, the DSL bus correspondingly outputs the high level signals.
The master device and the slave device both have an open-drain output detection function and an open-drain input detection function, the master device and the slave device are switched to an output state to control an operation state of the DSL bus, and the slave device and the master device are switched to an input state to detect a level state of the DSL bus.
And 200, selecting one optional device as a master device, using the other devices as slave devices, sending a communication starting signal to the DSL bus by using the master device, and establishing communication connection with the expected slave devices.
The time length T used by the DSL bus for transmitting one byte of dataBASECalled bit duration, and TBASEThe DSL bus communication protocol minimum signal time sequence is a signal time sequence formed by combining a single low level signal and a single high level signal, and the holding time length of the high level signal is always less than or equal to the holding time length of the low level signal in the data communication process.
The minimum unit of the transmission data of the DSL bus is a byte, and when the DSL bus transmits data, a high level signal is transmitted first, and then a low level signal is transmitted.
Step 300, the master device outputs various signals for controlling the DSL bus, and combines the various signals for controlling the DSL bus operation state to form various operation states, and the master device and the slave device perform data interaction of a dynamic synchronous communication rate according to a set operation mode.
The master device outputs various signals for controlling the operation state of the DSL bus, including an idle signal, a reset signal, an answer signal and a non-answer signal.
The main device sends an idle signal to the DSL bus, where the low-level signal holding duration is less than that of an adjacent high-level signal, and the high-level signal holding duration is greater than 3 times the low-level signal holding duration, and the DSL bus is in an idle state, that is, communication of the DSL bus is terminated, and when the DSL bus communicates again, the DSL bus must start with a reset signal.
The master device sends a time sequence signal to the DSL bus, wherein the duration of the low level signal is less than the duration of the adjacent high level signal, the duration of the high level signal is 1.5-2 times of the duration of the low level signal, the DSL bus is in a reset state, and the slave device updates the self communication bit duration T after detecting the reset signalBASEAnd continues to receive subsequent data with the updated bit duration.
The receiver controls the DSL bus to output a response signal after receiving one byte of data, and the low level of the response signal keeps TBASEThereafter, high holding TBASE
The receiver controls the DSL bus to output a non-response signal after receiving one byte of data, and the low level of the response signal keeps TBASE2, high level hold T thereafterBASE
Preferably, when the DSL bus is in the idle state, all devices connected to the DSL bus are waiting for a reset signal, and all devices do not respond to any signal other than the reset signal.
The slave device detects a reset signal on the DSL bus and completes TBASEAnd updating, and the slave equipment waits for the master equipment to send the slave equipment ID for authentication communication.
The master device and the slave device corresponding to the ID code establish a communication relationship, the slave device detects a continuous starting signal on the DSL bus and the ID of the slave device is consistent with the ID of the slave device, the master device sends a completion starting signal and a target ID and receives a response signal of the corresponding slave device, and the master device and the slave device corresponding to the ID code are in a matching state until the communication is finished or the communication is overtime.
After the DSL bus is reset, the master device must send a slave device ID for communication, and a last byte for regulating and controlling read-write operation of the master device is carried in the slave device ID, and when the last byte is 0, the master device sends byte data to the slave device, and when the last byte is 1, the master device is configured to read the byte data sent by the slave device.
When the last byte is 0, the master device continuously writes the sending byte data into the slave device, and the specific implementation steps are as follows: (1) the master device sends a communication start signal to the DSL bus.
(2) And the master device sends a target ID to the DSL bus, and the last byte is 0, releases the DSL bus and waits for a response signal of the slave device.
(3) And the main equipment takes over the DSL bus again after receiving the response signal until the main equipment finishes the communication when receiving the non-response signal.
(4) The master device sends byte data to the slave device and waits for a response signal returned by the slave device after sending one byte.
(5) And after the master device finishes sending the last byte and receives a response signal sent by the slave device, the master device sends an idle signal for finishing communication to the DSL bus.
When the last byte is 1, the master device continuously reads the byte data sent by the slave device, and the specific implementation steps are as follows: the main equipment sends a communication starting signal to the DSL bus;
the master device sends a target ID to the DSL bus, the last byte is 1, the DSL bus is released, and a response signal of the slave device is waited;
after receiving the response signal, the master device continues to receive the byte data sent by the slave device, and takes over the DSL bus after receiving one byte data;
fourthly, the main equipment sends a response signal to the DSL bus and releases the bus;
after receiving a byte, the master device sends non-response signal to the bus and does not receive byte data any more, and finishes the communication.
The DSL bus interface protocol provided by the embodiment uses a single communication line, dynamically synchronizes the communication speed, can reduce the core number of the communication cable during remote communication, can ensure the self-adaption of signal time sequence to cable parameters, effectively reduces the material cost, increases the communication distance, dynamically synchronizes the communication speed, and solves the problems of rate non-configuration, high error rate and even code disorder caused by the difference of respective clocks of two communication parties in serial communication protocols such as UART, USB and the like.
The above embodiments are only exemplary embodiments of the present application, and are not intended to limit the present application, and the protection scope of the present application is defined by the claims. Various modifications and equivalents may be made by those skilled in the art within the spirit and scope of the present application and such modifications and equivalents should also be considered to be within the scope of the present application.

Claims (7)

1. A single bus communication method, comprising: the method comprises the following steps:
step 100, connecting a plurality of devices to a DSL bus through a single data line, and setting all the devices to adopt open-drain output;
200, selecting one piece of equipment as a master equipment and the rest as slave equipment, sending a communication starting signal to the DSL bus by using the master equipment, and establishing communication connection with the expected slave equipment;
step 300, the master device outputs various signals for controlling the DSL bus, combines the various signals for controlling the DSL bus operating state to form various operating states, and performs data interaction of a dynamic synchronous communication rate according to a set operating mode;
in step 300, the master device outputs a plurality of signals for controlling the DSL bus operation state, including an idle signal, a reset signal, an acknowledgement signal, and a non-acknowledgement signal;
the main device sends an idle signal to the DSL bus, wherein the low-level signal holding duration of the idle signal is less than that of an adjacent high-level signal, the high-level signal holding duration of the idle signal is more than 3 times of the low-level signal holding duration, the DSL bus is in an idle state, namely, the communication of the DSL bus is terminated, and the DSL bus must start with a reset signal when communicating again;
the master device sends a time sequence signal to the DSL bus, wherein the duration of the low level signal is less than the duration of the adjacent high level signal, the duration of the high level signal is 1.5-2 times of the duration of the low level signal, the DSL bus is in a reset state, and the slave device updates the self communication bit duration T after detecting the reset signalBASEContinuing to receive subsequent data according to the updated bit duration;
the receiver controls the DSL bus to output a response signal after receiving one byte of data, and the low level of the response signal keeps TBASEThereafter, high holding TBASE
The receiver controls the DSL bus to output a non-response signal after receiving one byte of data, and the low level of the response signal keeps TBASE2, high level hold T thereafterBASE
When the DSL bus is in an idle state, all devices connected with the DSL bus wait for a reset signal, and all devices do not respond to any signal except the reset signal;
the slave device detects a reset signal on the DSL bus and completes TBASEUpdating, and the slave device waits for the master device to send a slave device ID for authentication communication;
the master device and the slave device corresponding to the ID code establish a communication relationship, the slave device detects a continuous starting signal on the DSL bus and conforms to the ID of the slave device and the ID of the slave device, the master device sends a completion starting signal and a target ID and receives a response signal of the corresponding slave device, and the master device and the slave device corresponding to the ID code are in a matching state until the communication is finished or the communication is overtime;
after the DSL bus is reset, the master device must send a slave device ID for communication, and a last byte for regulating and controlling read-write operation of the master device is carried in the slave device ID, and when the last byte is 0, the master device sends byte data to the slave device, and when the last byte is 1, the master device is configured to read the byte data sent by the slave device.
2. The single-bus communication method as claimed in claim 1, wherein: in step 100, all devices connected to the DSL bus are respectively provided with a unique ID code, and all devices are divided into a master device or a slave device, where the master device is responsible for initiating a communication start signal and controlling the whole communication process, and the slave device is configured to monitor and detect a communication start signal on the DSL bus;
the master device and the slave device can receive and send data in the communication process, the master device which is sending data is called a sender, and the slave device which is receiving data is called a receiver;
when the DSL bus is free of communication signals, all the devices connected to the DSL bus are slave devices, and any one slave device can be converted into a master device to initiate a communication process.
3. The single-bus communication method according to claim 2, wherein: in step 100, an and-gate relationship exists between the output level signals of the master device and the slave device and the total level signal of the DSL bus, and when any one device outputs a low level signal, the DSL bus is pulled low, and only if all devices output high level signals, the DSL bus outputs a high level signal correspondingly.
4. The single-bus communication method as claimed in claim 3, wherein: the master device and the slave device both have an open-drain output detection function and an open-drain input detection function, the master device and the slave device are switched to an output state to control an operation state of the DSL bus, and the slave device and the master device are switched to an input state to detect a level state of the DSL bus.
5. The single-bus communication method according to claim 2, wherein: in step 200, the DSL bus takes a time period T for each byte of data to be transmittedBASECalled bit duration, and TBASEThe minimum signal time sequence of the communication protocol of the DSL bus is the signal time sequence of the combination of a single low-level signal and a single high-level signal, and the holding time length of the high-level signal is always less than or equal to the holding time length of the low-level signal in the data communication process;
the minimum unit of the transmission data of the DSL bus is a byte, and when the DSL bus transmits data, the high bit is transmitted first and then the low bit is transmitted.
6. The single-bus communication method as claimed in claim 1, wherein: when the last byte is 0, the master device continuously writes the sending byte data into the slave device, and the specific implementation steps are as follows:
the master device sends a communication starting signal to the DSL bus;
the master device sends a target ID to the DSL bus, and the last byte is 0, releases the DSL bus and waits for a response signal of the slave device;
the main equipment takes over the DSL bus again after receiving the response signal until the main equipment finishes the communication when receiving the non-response signal;
the master device sends byte data to the slave device, and waits for a response signal returned by the slave device after sending one byte;
and after the master device finishes sending the last byte and receives a response signal sent by the slave device, the master device sends an idle signal for finishing communication to the DSL bus.
7. The single-bus communication method as claimed in claim 1, wherein: when the last byte is 1, the master device continuously reads the byte data sent by the slave device, and the specific implementation steps are as follows:
the master device sends a communication starting signal to the DSL bus;
the master device sends a target ID to the DSL bus, the last byte of the target ID is 1, the DSL bus is released, and a response signal of the slave device is waited;
the master device continues to receive the byte data sent by the slave device after receiving the response signal, and takes over the DSL bus after receiving one byte data each time;
the master device sends a response signal to the DSL bus and releases the bus;
and after receiving one byte, the main equipment sends a non-response signal to the bus and does not receive byte data any more, and the communication is finished.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6671748B1 (en) * 2001-07-11 2003-12-30 Advanced Micro Devices, Inc. Method and apparatus for passing device configuration information to a shared controller
US7606955B1 (en) * 2003-09-15 2009-10-20 National Semiconductor Corporation Single wire bus for connecting devices and methods of operating the same
CN104811273A (en) * 2015-04-02 2015-07-29 福州大学 Implement method for high speed single bus communication
CN207473599U (en) * 2017-12-04 2018-06-08 山东高云半导体科技有限公司 A kind of I2C bus control interfaces circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10135634B2 (en) * 2016-11-03 2018-11-20 Infineon Technologies Ag Bus interface with bi-directional, one-wire communication and individual select lines
JP6880663B2 (en) * 2016-11-14 2021-06-02 セイコーエプソン株式会社 Data communication systems and semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6671748B1 (en) * 2001-07-11 2003-12-30 Advanced Micro Devices, Inc. Method and apparatus for passing device configuration information to a shared controller
US7606955B1 (en) * 2003-09-15 2009-10-20 National Semiconductor Corporation Single wire bus for connecting devices and methods of operating the same
CN104811273A (en) * 2015-04-02 2015-07-29 福州大学 Implement method for high speed single bus communication
CN207473599U (en) * 2017-12-04 2018-06-08 山东高云半导体科技有限公司 A kind of I2C bus control interfaces circuit

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