JPH06243052A - Serial communication error processing method - Google Patents

Abstract

PURPOSE:To prevent a system from becoming hang-up in serial communication. CONSTITUTION:A micro computer 1 transmits an address and transmits/receives data in serial communication with IC 2. In the micro computer 1, an ACK signal recognizes an H level and sets an STB signal to an L level. When IC 2 sets the ACK signal to the L level immediately after it, the address for eight bits or data is transmitted/received as an input/output signal. At that time, an SCK signal transmits a clock pulse. When transmission/reception normally terminates, the ACK signal becomes the H level and the micro computer 1 sets the STB signal to the H level. When the ACK signal does not become the H level even a prescribed time has passed, the micro computer 1 judges that a communication error occurs, compulsorily sets the STB signal to the H level and abnormally terminates communication. When communication abnormally terminates, IC 2 does not latch the address or data in the middle of input. The micro computer sets the STB signal to the L level after abnormal communication terminates, and resumes communication from the address or data where the communication error occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication error processing method.

[0002]

2. Description of the Related Art When data is communicated between a microcomputer and an IC or between microcomputers, serial communication is often used when the amount of data is small. This serial communication does not require the number of data transmission lines according to the number of bits of data to be transmitted, and the number of data transmission lines may be two or one. Therefore, there are restrictions on the number of data transmission lines and the number of connection pins. Very convenient in case.

In serial communication, in addition to data, timing signals and control signals for notifying the other party of transmission / reception states are used, and these signals are input / output using respective signal lines. When both sides communicate, data transmission / reception possible state, transmission / reception standby state, request,
The status such as transmission start and reception completion is determined.

[0004]

However, in the above method, a communication error occurs for some reason, one of the communication partners waits for data input, and the other waits for a data reception completion signal. May occur. In this state, both parties continue to wait for the signal from the other party, and the procedure goes to the next step, resulting in a hangup. If you hang up once, you have to input a communication reset signal from the outside or turn off the power of the device and then turn it on again to initialize it.
Even if it recovers in this way, it is very inconvenient because the valid data that was normally communicated is deleted.

The present invention has been made to solve the above problems, and provides an error processing method for serial communication in which a communication error is reliably determined and communication is restarted without hang-up. With the goal.

[0006]

In order to achieve the above object, the present invention provides a first method for transmitting a transmission request signal from a transmission side to a reception side in communication for serially transmitting data from the transmission side to the reception side. A communication line and a second communication line for transmitting a reception request signal from the reception side to the transmission side are provided, and the transmission side starts the generation of the transmission request signal during data communication and confirms that the generation of the reception request signal has stopped. After that, the generation of the transmission request signal is stopped, and the receiving side generates the reception request signal from immediately after receiving the transmission request signal until the end of data reception, and a fixed time has elapsed from the generation start point of the transmission request signal. When the reception request signal is still generated, the transmission side judges that a communication error has occurred, stops the generation of the transmission request signal, and then transmits it to retransmit the data in which the communication error occurred. request The generated items, the other receiving side discards the data being received it is determined that a communication error when the occurrence of the transmission request signal during generation of the received request signal is stopped occurs.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a block diagram of a microcomputer and an IC for communicating using the present invention. The microcomputer 1 and the IC 2 in the same set are connected by a plurality of signal lines, and STB signal and ACK are connected to these signal lines.
There are signals, input / output signals, SCK signals, ALD signals, and WLR signals. The IC 2 holds an address designated by the microcomputer 1 and has a function of writing data sent by the microcomputer 1 to the address and a function of reading data at the address and sending the data to the microcomputer 1.

The STB signal is a transmission request signal from the microcomputer 1. The ACK signal is a reception request signal from IC2. The input / output signal includes an address and data, which are composed of 8 bits and are exchanged bit by bit between the microcomputer 1 and the IC 2.
In order to indicate the division of this 8-bit input / output signal, SK
Microcomputer 1 with C signal as clock pulse
Sent to IC2. The ALD signal is a signal for selecting an address and data, and the microcomputer 1 sets the ALD signal to L level when sending an address and sets it to H level when inputting / outputting data. The STB signal, the ALD signal, and the SCK signal are the microcomputer 1
Is input to IC2. The ACK signal is input from the IC 2 to the microcomputer 1. When the ACK signal is at the H level even after the ACK signal has been longer than one cycle of the clock pulse,
It is detected that the K signal has become H level. Further, when the ACK signal is at the L level for a certain time or longer, the microcomputer 1 determines that a communication error has occurred and forcibly sets the STB signal to the H level.

The WLR signal is sent to the address specified by the microcomputer from the microcomputer 1 to I.
It is selected whether to write data to C2 or read the data of IC2 to the microcomputer 1. When the microcomputer 1 selects the reading of data, the IC 2 sends the data at the designated address as an input / output signal in synchronization with the SCK signal. Further, when the writing is set, the data from the microcomputer 1 can be received.

FIG. 1 is a logic circuit diagram of the main part of IC2. The STB signal from the microcomputer 1 is an OR gate 25a, an inverter 29a, a fall detection circuit 2
1 and the rising edge detection circuit 22. The fall detection circuit 21 generates one short pulse (H level) at the fall of the STB signal (changes from H level to L level), and outputs the pulse to the K terminal of the JK-FF 23, the AND gate 24a, and the OR gate 25b. Output to. The rising edge detection circuit 22 generates one short pulse (H level) at the rising edge of the STB signal (changes from L level to H level), and outputs its output from the AND gates 23b, 23c, 26,
To 27.

JK-FF23 and JK-FF2 described later
Reference numeral 5 is a JK type flip-flop circuit, in which the J terminal is at L level, the K terminal is at L level, the output of the Q terminal does not change, the J terminal is at H level, the K terminal is at L level, and the output Q is at H level.
When the J terminal is at the L level, the K terminal is at the H level, the output Q is at the L level, the J terminal is at the H level, the K terminal is at the H level, and the output of the Q terminal is inverted. The output of the Q terminal is J
It changes with a delay within half a clock cycle after the change of the terminal and the K terminal occurs.

S sent from the microcomputer 1
The CK signal is input to the AND gate 29. The output of the inverter 29a is input to the AND gate 29, and the clock pulse of the SCK signal is input to the counter 24 and the AND gate 25c only when the STB signal is at the L level. The counter 24 counts at the falling edge of the clock pulse of the SCK signal, and the count number is a binary number from the lowest digit to the QA terminal, QB terminal, QC terminal, QD terminal, CO
Output in the order of terminals. When the pulse (H level) is sent from the counter 24a, the counter 24 sets its value to "0" (QA
The outputs from the terminals to the QD terminal and the CO terminal are all at the L level). The outputs of the QA terminal, QB terminal and QC terminal are input to the NOR gate 25d, and the output of the QD terminal is input to the NOR gate 25d via the inverter 25e.

The OR gate 27a has a NOR gate 25d.
And the output of the CO terminal of the counter 24 are input. The counter sequentially counts the clock pulses of the SCK signal from 1 and the outputs from the QD terminal to the QA terminal become "H, L, L, L" at the eighth position, so that the output becomes the H level. When the counter 24 counts the 16th clock pulse, the output of the CO terminal is "H".

The output of the OR gate 27a is input to the one-shot circuit 27. The output of the CO terminal of the counter 24 is also input to the one-shot circuit 28. The one-shot circuits 27 and 28 output one short pulse at the rising edge of the input signal. The pulse from the one-shot circuit 27 is input to the OR gate 25a. The pulse of the one-shot circuit 28 is input to the OR gate 23a. A
The LD signal is input to the AND gate 27, and the ALD signal is passed through the inverter 26a to the AND gates 23b and 2b.
It has been entered in 6.

The output from the OR gate 25a is JK-FF.
It is input to the J terminal of 25. The output of the OR gate 25b is input to the K terminal of the JK-FF25. OR
The output of the AND gate 25c is input to the input of the gate 25b. The Q output of the JK-FF 25 is output as an ACK signal, and the AND gates 25c, 26, 2
It is entered in 7. The INV-Q terminal outputs an inverted version of the output from the Q terminal. INV-Q terminal output is A
It is input to the ND gate 23c.

The output of the AND gate 23b is the OR gate 2
It is input to 3a. The output of the AND gate 23c is O
It is input to the R gate 23a. The output of 23a is JK
-It is input to the J terminal of FF23. JK-FF23
The output of the Q terminal of is input to the AND gates 24a and 27.

AND gate 26 outputs the ADWTE signal. The IC output by the pulse output from the AND gate 26
2 latches the address sent by the microcomputer 1. Also, the AND gate 27 outputs the DWTE signal. The data output from the microcomputer 1 is latched by the pulse output from the AND gate 27.

Next, the operation of the circuit shown in FIG. 2 will be described with reference to FIG.
From now on, referring to FIG. As the initial state when the power is turned on, the STB signal, the Q terminal of the JK-FF 23, and the ALD signal are set to the H level. In normal communication, it operates as follows. First, when the microcomputer 1 detects the H level of the ACK signal, it sets the ALD signal, the WLR signal and the STB signal to the L level. At this time, the ALD signal, the WLR signal, and the STB signal may be set to the L level at the same time, or the STB signal may be slightly delayed.

When a pulse is output from the fall detection circuit 21 due to the fall of the STB signal, JK-F
Since the Q terminal of F23 is at H level, a pulse is output from the AND gate 24a and the counter 24 is cleared. Further, since the H level is also input to the K terminal of the JK-FF 23, Q becomes the L level with a slight delay. Furthermore, J
Since the J terminal of the K-FF 25 becomes L level and the H terminal is inputted at H level, the ACK signal output from the Q terminal of the JK-FF 25 becomes L level with a little delay.

In the microcomputer 1, the ACK signal is L
When it is confirmed that the level is reached, eight clock pulses are sent by the SCK signal and 8-bit address data is sent as an input / output signal. When the counter 24 counts the eighth clock pulse, the H level is input to the J terminal of the JK-FF 25, and the ACK signal goes to the H level.
When the microcomputer 1 detects that the ACK signal has become H level, it sets the STB signal to H level.

When the STB signal rises, the rising edge detection circuit 22 sends out a pulse. As a result, the signal obtained by inverting the ALD signal by the inverter 26a and the JK-FF
Since the Q terminal of 25 is at H level, the AND gate 26 outputs a pulse of the ADWTE signal. This AD
The address data sent from the microcomputer 1 is latched in the IC 2 by the WTE signal. Also, J
Since the H level is input to the J terminal of K-FF23,
The Q terminal becomes H level. After that, the H level of the STB signal is input to the Q terminal of the JK-FF 25, but Q does not change from the H level state.

In the microcomputer 1, the ACK signal is H
After confirming the level, the ALD signal is set to the H level, the WLR signal is set to write or read data, and the STB signal is set to the L level. When the STB signal falls, a pulse is output from the fall detection circuit 21 and the counter 24 is cleared. Furthermore JK-FF
At 23, the H level is input to the K terminal, and the Q terminal becomes the L level after a delay. Further, in the JK-FF 25, the J terminal is at the L level and the K terminal is at the H level, so that the Q terminal, that is, the ACK signal is at the L level with a delay.

When the microcomputer 1 confirms the L level of the ACK signal, the upper 8 bits of data are transmitted / received by the input / output signal together with the transmission of the clock pulse. When the counter 24 counts eight pulses, the H level is input to the J terminal of the JK-FF 25 and the ACK signal goes to the H level. After detecting the H level of the ACK signal, the microcomputer 1 sets the STB signal to the H level. At this time, the J terminal of the JK-FF 23 does not go to the H level, so the Q terminal remains at the L level. At this point DWTE
Since the signal is not pulsed, it does not latch the data.

The microcomputer 1 sets the STB signal to L level after a fixed time. At this time, even if a pulse is output from the fall detection circuit 21, the counter is not cleared because the Q terminal of the JK-FF 23 is at L level. Since the H level is input to the K terminal in the JK-FF25, the ACK signal goes to the L level with a slight delay. After confirming the L level of the ACK signal, the microcomputer 1 sends out eight clocks and transmits / receives the lower 8 bits of data. When this transmission / reception ends, the counter 2
The count number of 4 becomes 16, so J of JK-FF23
The H level is input to the terminal and the J terminal of the JK-FF 25, whereby the Q terminal of the JK-FF 23 and the ACK signal become the H level.

When the microcomputer 1 detects that the ACK signal has become H level, it sets the STB signal to H level. Since the ALD signal and the Q terminals of the JK-FFs 23 and 25 are at the H level, the rise detection circuit 2
With the pulse from 2, the AND gate 27 sends out a pulse of the DWTE signal. When data writing is set, 16-bit data is latched in IC2. When the data is sent to the microcomputer 1, it may be held in a register, for example. ST
Since the B signal is at the H level, the J terminal of the JK-FF 25 goes to the H level and returns to the initial state. This operation is repeated until transmission / reception of necessary data is completed.

Next, the operation when a communication error occurs will be described. As described above with reference to the timing of FIG. 3, after the microcomputer 1 sets the STB signal to the L level and the communication is normally completed, the STB signal is set to the H level before the ACK signal. However, if the communication does not end normally for some reason, the microcomputer 1 cannot detect the H level even after the ACK signal has passed for a certain period of time as shown in FIG. Then, the STB signal is set to H level. Here, since the ACK signal is delayed and becomes H level, S
The TB signal goes to H level before the ACK signal and ends abnormally. STB signal goes to H level and SCK between
No signal is sent out from AND gate 29 first.

Rising detection circuit 2 upon abnormal termination
Even if the pulse is transmitted from 2, the Q terminal of the JK-FF 25 is still at the L level. As a result, the IC 2 recognizes a communication error and discards the input address or data without latching them. INV-Q terminal of JK-FF25 is H
Since it is at the level, when a pulse is sent from the rising edge detection circuit 22, the AND gate 23c outputs JK-
H level is input to the J terminal of FF23 and JK-FF23
Q terminal of H level. After that, the microcomputer 1 sets the STB signal to the L level in order to retransmit the address or the data when the error occurs.

For example, if the count of the counter 24 does not reach 8 or 16 for a certain period of time for some reason, such as when the number of clocks is small or the clock count of the counter 24 is missed, it is determined that a communication error has occurred. Then, the microcomputer 1 forcibly sets the STB signal to the H level. Then, as described above, retransmission is performed from the input / output signal in which the communication error has occurred.

FIG. 5 shows the timing when there are many clocks. For example, if the counter counts 8 or 16 before the original 8th or 16th pulse due to noise on the SCK signal (in FIG. 5, the change of only the 16th pulse is a broken line). ,), JK
-The Q terminal of the FF 25, that is, the ACK signal becomes H level. However, the clock of the SCK signal is input to the IC2 even after the counter has counted the 8th or 16th counter. In the AND gate 25c, the input from the JK-FF 25 is already at H level. Apparently 9 or 1
When the H level of the 7th clock is input, OR
The H level is input to the K terminal of the JK-FF 25 via the gate 25b. At this time, the output from the one-shot circuit 27 is already at L level, and the counter 24 C
Since there is no change in the O terminal, the one-shot circuit 27 is again used.
No pulse is output from JK-
The J terminal of the FF 25 is at the L level.

Since the H level is input to the K terminal of the JK-FF 25, the ACK signal is at the L level during the maximum time within one cycle of the clock pulse after the ACK signal is at the H level. Here, the microcomputer 1 is AC
K signal is not detected. The original 8th or 16th clock pulse is sent out, and the L-level state of the ACK signal does not change during or after counting by the counter 24. After a certain period of time, the microcomputer 1 determines that there is a communication error and sets the STB signal to H level. Retransmission is started as described above.

Further, since there is a possibility that the relationship between the address and the data is broken in the communication after the communication is interrupted, the IC2 always uses the address when the ALD signal is at the L level as described above. . As shown in FIG. 6A, it is assumed that the IC 2 receives the address even if the ALD signal is at the L level. Further, as shown in FIG. 6B, the IC2 receives the address 2 even if the ALD signal changes from the H level to the L level after the transmission and reception of the upper 8 bits of data. At this time, the upper 8 bits of data 1 corresponding to address 1 are not latched.

As described above, even if a communication error occurs, the IC 2 and the microcomputer 1 do not continue to wait for the end of communication, and communication is resumed without hangup.

In the above embodiment, the description has been made between the microcomputer and the IC, but a similar protocol may be used between the microcomputers. Further, not only communication within the same set but also communication between sets is possible. Although the ALD signal line is used for identifying the address and the data, this signal line may be omitted. Although the WLR signal line is used for reading and writing data, this signal line is not necessary.

[0034]

As described above, according to the communication error processing method of the present invention, the communication line for transmitting the transmission request signal and the communication line for transmitting the reception request signal are provided between the transmitting side and the receiving side. If the data transmission does not end within a certain time after the start of communication, it is determined that a communication error has occurred, and the data with the communication error is retransmitted. Can be prevented.
Further, since the communication error is controlled from the state of this signal, it is reliable and simple.

[Brief description of drawings]

FIG. 1 is a logic diagram of the main parts of an IC implementing the method of the present invention.

FIG. 2 is a block diagram showing serial communication between a microcomputer and an IC.

FIG. 3 is a timing chart showing normal communication of the logic circuit of the embodiment.

FIG. 4 is a timing chart when a communication error occurs.

FIG. 5 is a timing chart when another communication error occurs.

FIG. 6 is an operation explanatory diagram according to an ALD signal.

[Explanation of symbols]

 1 Microcomputer 2 IC 23,25 JK-FF 24 counter

Claims (1)

[Claims] 1. In serial communication for transmitting data serially from a transmitting side to a receiving side, a first communication line for transmitting a transmission request signal from the transmitting side to the receiving side, and a receiving request signal from the receiving side to the transmitting side. And a second communication line for transmitting the data, the transmitting side starts generation of the transmission request signal during data communication, confirms that the reception request signal is not generated, and then stops generation of the transmission request signal. Generates a reception request signal immediately after receiving the transmission request signal until the end of data reception, and when the reception request signal continues to be generated when a certain time has elapsed from the time when the generation of the transmission request signal started. , The transmitting side determines that a communication error has occurred, stops the generation of the transmission request signal, and then generates the transmission request signal to retransmit the data with the communication error, while the receiving side receives the reception request signal. A method for processing serial communication error, characterized in that it is judged that a communication error has occurred when the generation of the transmission request signal is stopped while the data is being generated, and the data being received is discarded.