JP3296905B2 - Pattern detection circuit and facsimile machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern detection circuit and a facsimile apparatus, and more particularly to a pattern detection circuit of a communication apparatus having a built-in modem having a parallel interface and a serial interface, and a facsimile apparatus having the same.

[0002]

2. Description of the Related Art In a communication apparatus such as a facsimile apparatus, for example, as disclosed in Japanese Patent Application Laid-Open No. 4-267563,
When a modem (modulator / demodulator) receives data from an external device (transmitter), it converts the received data into a parallel interface to correct the bit shift of the received data caused by the difference in the operation timing of data transmission / reception with the transmitter. Is transferred to a pattern detection circuit by CPU transfer or DMA transfer via the CPU to perform pattern detection.

[0003]

However, in the above-described modem, it is necessary to convert the parallel data into serial data once and then detect whether or not the pattern matches. And a cost increase.

Also, modems themselves have become sophisticated, and most modems today have a built-in HDLC (high-level data link control procedure) function. There is also a drawback that the flag pattern cannot be counted because the is deleted by the modem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and therefore, a cost reduction can be achieved by eliminating the need for a conversion circuit for converting parallel data into serial data, and the flag pattern can be counted even when the HDLC function is used. The purpose is to be.

[0006]

According to the present invention, there is provided an output / stop unit connected to a serial interface of a modem for outputting / stopping a serial clock input of the modem in accordance with a condition. Parallel output means for latching an input at the rising edge of the serial clock to perform a parallel output, pattern setting means for setting a pattern to be compared with the parallel output output from the means, and a parallel output output from the parallel output means Is compared with the pattern set by the pattern setting means, and a pattern matching detecting means for outputting a corresponding signal when detecting that the parallel output matches the pattern, and controlling when the signal is output from the means. Notification means for notifying the control unit, and an address output from the control unit. The decoding to provide a pattern detection circuit provided with a control signal generating means for generating a signal for controlling the above means.

The output / stop means, the parallel output means, the pattern setting means, and the pattern coincidence detecting means described above, the number of latches counting the number of latches by the parallel output means, the means and the pattern coincidence detecting means Predetermined signal output means for outputting a predetermined signal in accordance with the output of the output means, output number counting means for counting the number of outputs by the means, and notification to notify the control unit when the output number counted by the means reaches a specified value. There is also provided a pattern detection circuit provided with means and means for decoding an address output from the control unit and generating a signal for controlling each of the above means.

Further, the output / stop means, the parallel output means, the pattern setting means, the pattern coincidence detecting means, the number of latch times counting means, the predetermined signal outputting means, and the output number counting means, and the continuous number for setting the number of continuous detections Detecting number means, notifying means for notifying the control unit when the number of outputs counted by the output number counting means reaches the value set by the continuous detection number setting means, and decoding the address output from the control unit. There is also provided a pattern detection circuit provided with means for generating a signal for controlling each of the above means.

Further, the present invention provides a facsimile apparatus having any one of the above-described pattern detection circuits.

[0010]

The pattern detecting circuit according to the first aspect of the present invention is connected to a serial interface of a modem, and a control signal generating means in the pattern detecting circuit decodes an address output from the control unit and controls the following means. Output / stop means for outputting / stopping the serial clock input of the modem according to the conditions.

The parallel output means latches the serial data input of the modem at the rising edge of the serial clock to perform parallel output, and the pattern coincidence detecting means compares the parallel output with the pattern set by the pattern setting means. When it is detected that the parallel output matches the pattern, a corresponding signal is output, and the notifying unit notifies the control unit at the time of the output. Therefore, a conversion circuit from parallel data to serial data is not required, and the flag pattern can be counted even when the HDLC function of the modem is used.

The pattern detecting circuit according to the second aspect of the present invention is also connected to the serial interface of the modem, and the control signal generating means in the pattern detecting circuit decodes an address output from the control unit and controls the following means. And the output / stop unit, the parallel output unit, the pattern setting unit, and the pattern coincidence detection unit perform the same operations as described above.

The latch number counting means counts the number of latches by the parallel output means, the predetermined signal output means outputs a predetermined signal in accordance with the outputs of the latch number counting means and the pattern matching detection means, and the output number counting means outputs the predetermined signal. The number of outputs is counted, and the notifying unit notifies the control unit when the number of outputs reaches a specified value. Therefore, the same effect as described above can be obtained, and the probability of erroneous detection due to data application is reduced.

The pattern detecting circuit according to the third aspect of the present invention is also connected to the serial interface of the modem, and the control signal generating means in the pattern detecting circuit decodes an address output from the control unit and controls the following means. And the output / stop means, the parallel output means, the pattern setting means, the pattern coincidence detection means, the latch count counting means, the predetermined signal output means, and the output number counting means perform the same operations as described above. Since the notification means notifies the control unit when the number of outputs counted by the output number counting means reaches the value set by the continuous detection number setting means, the same effect as described above can be obtained.

According to the facsimile apparatus of the present invention, since any one of the above-described pattern detection circuits is provided, a communication failure due to the inability to count the number of flag patterns in the HDLC mode is eliminated.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of a facsimile apparatus according to one embodiment of the present invention.

The facsimile apparatus includes a system control unit 1 including a CPU (central processing unit) for controlling the entire system, a system memory unit 2 for storing information necessary for system control, and an image for storing image information. Memory part 3
An encoding / decoding unit 4 for encoding and decoding image information; a recording unit 5 for recording image information on paper; a reading unit 6 for reading an original; an LCD display, a numeric keypad, and a line A handshake is performed between the operation unit 7 having a selection button and the like and the system control unit 1 so that the modem unit 9 and the N
A communication control unit 8 for controlling a communication unit such as the CU unit 10;

Also, the protocol signal and the image information are transmitted to 21
And V. A modem unit 9 for modulating and demodulating according to a standard such as 17;
An NCU unit 10 which is an interface with a line, and a serial interface of the modem unit 9 (hereinafter, "interface" is referred to as "I / F").
Pattern detection unit (pattern detection circuit) for detecting OL (line end code) / RTC (control return code) pattern
11 is provided.

FIG. 1 is a block diagram showing an example of the configuration of the pattern detecting section 11. The command decoding section 12, the clock gate section 13, the shift register section 14, the pattern coincidence detecting section 15, the control register section 19, and the interrupt generating section. 20 and a three-state buffer unit 21.

The command decoding unit 12 includes a communication control unit 8
And decodes the address output to generate a CPU command (signal) such as a set signal to the control register section 19 and a pattern detection start / stop signal. The clock gate unit 13 starts the modem unit 9 when the pattern detection starts.
Is output to the shift register unit 14, and when the detection of each pattern is completed, the output of the serial clock (DCLK) of the modem unit 9 to the shift register unit 14 is stopped.

The shift register unit 14 converts a serial data input (RXD) of the modem unit 9 into a serial clock (DC).
LK) is latched at the rising edge to perform parallel output. The pattern match detection section 15 compares the parallel output of the shift register section 14 with the pattern selected and set by the pattern selection signal from the control register section 19, and when it detects that the parallel output matches the pattern, the corresponding pattern is detected. Flag detection signal or EOL signal
Outputs (activates) the detection signal.

The control register section 19 sets a detection mode via a data bus in accordance with a set signal from the command decode section 12, and outputs a corresponding pattern selection signal. When a flag detection signal is input from the pattern matching detection unit 15, the interrupt generation unit 20 generates a flag detection interrupt signal.
When an EOL detection signal is input, an EOL detection interrupt signal is output. The three-state buffer unit 21 normally outputs data to the data bus only when reading the status in the high impedance state.

FIG. 3 is a block diagram showing another example of the configuration of the pattern detecting section 11, and portions corresponding to FIG. 1 are denoted by the same reference numerals. The pattern detection unit 11 includes a command decoding unit 12, a clock gate unit 13, a shift register unit 14, a pattern match detection unit 15, a shift counter unit 16, a detection timing control unit 17, a pattern counter unit 18, a control register unit 19, And a three-state buffer unit 21.

The clock gate unit 13 outputs the serial clock input (DCLK) of the modem unit 9 to the shift register unit 14 and the shift counter unit 16 at the start of pattern detection, and when the detection of each pattern is completed, the serial clock of the modem unit 9 The output of (DCLK) to the shift register unit 14 and the shift counter unit 16 is stopped.

The pattern match detecting section 15 compares the parallel output of the shift register section 14 with a pattern selected and set by a pattern selection signal from the control register section 19 or a TAG (additional bit), and the parallel output matches the pattern. Flag detection signal, EOL detection signal, or EOL + TAG, which is a signal corresponding to the detection of
Outputs a detection signal.

The shift counter 16 counts the number of bits (the number of latches) shifted by the shift register 14, and is reset each time a pattern is detected. The detection timing control unit 17 resets the shift counter unit 16 based on the respective setting conditions, the outputs of the shift counter unit 16, the pattern counter unit 18, and the pattern match detection unit 15, and increments the pattern counter unit 18 (+
1) and generates and outputs reset and EOL detection signal generation timings.

The pattern counter 18 counts the number of outputs of the detection timing controller 17 corresponding to the number of detected patterns. The control register unit 19 sets a detection mode or a detection pattern via a data bus in response to a reset signal from the command decode unit 12, and outputs a corresponding pattern selection signal or TAG.

The interrupt generation unit 20 includes the pattern counter unit 1
When the count value of 8 (the number of consecutive detections of each pattern) reaches a specified value, a flag detection interrupt signal, an EOL detection interrupt signal, or an RTC detection interrupt signal is output.

FIG. 4 is a block diagram showing still another example of the configuration of the pattern detecting section 11. As in FIG. 3, a command decoding section 12, a clock gate section 13, a shift register section 14, a pattern matching detecting section 15, a shift Counter part 1
6, detection timing control unit 17, pattern counter unit 1
8, a control register section 19, an interrupt generation section 20, and a 3-state buffer section 21.

The control register unit 19 sets a detection mode, a detection pattern, or the number of continuous detections of a pattern through a data bus in response to a reset signal from the command decoding unit 12, and sets a corresponding pattern selection signal, TAG, or continuous detection number signal. Is output. When the count value of the pattern counter section 18 (the number of consecutive detections of each pattern) reaches a set value, the interrupt generation section 20 outputs a flag detection interrupt signal, EOL.
It outputs a detection interrupt signal or an RTC detection interrupt signal.

Next, the operation of the facsimile apparatus having the pattern detector 11 shown in FIG. 1 according to the first aspect of the present invention will be described. Now, when an address, a chip select signal, data, and a write pulse are output by the communication control unit 8 of FIG. 2, the command decode unit 12 inputs the address, the chip select signal, and the write pulse.

When the CPU command is generated by decoding the address, the CPU command is a set signal to the control register unit 19, the control register unit 19 inputs the set signal and outputs the set signal to the data bus. Set the detection mode that is data. The detection mode is set by setting ON / O of the corresponding bit of the control register unit 19.
It can be selected by FF.

The detection modes include an HDLC mode and a NON_HDLC mode.
1 is a flag pattern (011) in the HDLC mode.
11110) is notified to the communication control unit 8 as flag detection as a flag detection.
When the L pattern (0000000000001) is detected, the communication control unit 8 is notified as EOL detection.

Next, when a pattern detection start signal is issued from the command decoding unit 12, the clock gate unit 13 receives the signal and inputs it to the serial clock (DCLK) and serial data (DCLK) of the modem unit 9 to the shift register unit 14. RXD), and the shift register unit 14 outputs the serial data input (RXD) to the serial clock (D
CLK) is latched at the rising edge to perform parallel output.

Then, the pattern coincidence detecting section 15 compares the parallel output of the shift register section 14 with the pattern selected and set by the pattern selection signal (detection mode) from the control register section 19, and when it is detected that both coincide with each other. Output the corresponding signal. That is, if the detection mode is HD
In the LC mode, the flag detection signal is set to NON_HDL
In the C mode, an EOL detection signal is output (activated).

The interrupt generation unit 20 includes the pattern match detection unit 1
5 when a flag detection signal from the communication control unit 8 and a flag detection status bit signal to the three-state buffer unit 21
When the OL detection signal is output, the EO to the communication control unit 8 is output.
L detection interrupt signal and EO to the 3-state buffer unit 21
The L detection status bit signals are activated.

The interrupt signal is reset when the data is shifted by the input of the next serial clock (DCLK) to the shift register section 14 and the pattern does not match, but the status bit signal is held.
After the status bit signal is output from the three-state buffer unit 21 onto the data bus by the status read signal issued from the command decode unit 12, the reset is performed.

The pattern detection operation is continuously performed until a pattern detection stop signal is issued. When a pattern detection stop signal is issued from the command decode unit 12, the clock gate unit 13 stops outputting the serial clock (DCLK) and serial data (RXD), whereby the interrupt signal and the status bit signal are also reset. .

According to the facsimile apparatus having the pattern detecting section 11, since the pattern detecting section 11 is connected to the serial I / F of the modem section 9, a conversion circuit for converting parallel data into serial data is not required. Cost reduction can be realized by reducing the amount of hardware. Further, even when the HDLC function of the modem unit 9 is used, the flag pattern can be detected. Further, EO is performed by the communication control unit 8.
There is no need to detect the L pattern, and the load on the communication control unit 8 is reduced. Furthermore, there is no communication failure due to the inability to count the number of flag patterns in the HDLC mode.

Next, the operation of the facsimile apparatus having the pattern detecting section 11 shown in FIG. 3 according to the second aspect of the present invention will be described. Now, when an address, a chip select signal, data, and a write pulse are output by the communication control unit 8 in FIG. 2, the command decode unit 12 inputs the address, the chip select signal, and the write pulse as described above.

The CPU command is generated by decoding the address. If the CPU command is a set signal to the control register section 19, the control register section 19 inputs the set signal and outputs the set signal to the data bus. The detection mode and the detection pattern which are data are set.
The setting of the detection mode and the detection pattern can be selected by ON / OFF of the corresponding bit of the control register unit 19.

The detection modes include an HDLC mode and a NON_HDLC mode.
1 is a flag pattern (011) in the HDLC mode.
11110) is notified to the communication control unit 8 as a flag detection when it is detected a specified number of times in succession. In the case of the NON_HDLC mode, the EOL pattern (000000000000)
When 1) is detected, it is notified to the communication control unit 8 as EOL detection, and the EOL pattern (0000000000001) or the EOL pattern + TAG pattern (00000000) is detected.
0010011) is notified as RTC detection when it is detected a specified number of times in a row. The detection pattern (EOL / EOL + TAG) in the RTC detection can be selected.

Next, when a pattern detection start signal is issued from the command decode unit 12, the clock gate unit 13 receives the signal and inputs the same to the shift register unit 1 as described above.
The output of the serial clock (DCLK) and serial data (RXD) of the modem unit 9 to the modem 4 and the output of the serial clock (DCLK) to the shift counter 16 are started.

Then, the shift counter section 16 counts the serial clock (DCLK) from the clock gate section 13 and performs a reset when a reset signal is input from the detection timing control section 17.
4 latches the serial data input (RXD) from the clock gate unit 13 at the rising edge of the serial clock (DCLK) and performs parallel output.

Then, the pattern coincidence detecting section 15 compares the parallel output of the shift register section 14 with the pattern selected and set by the pattern selection signal (detection mode) from the control register section 19 and the TAG (detection pattern). When it detects that the output matches the pattern, it activates the corresponding signal and outputs it to the detection timing control unit 17.

The following is a description of each of the set detection modes. (1) In case of HDLC mode After issuing the pattern detection start signal, the detection timing control section 17 sets the count value of the shift counter section 16 to “1”.
When the flag detection signal from the pattern coincidence detection section 15 becomes active after exceeding "3", a corresponding signal is output, and the corresponding signal is output to the pattern counter section 18 as an increment signal and to the shift counter section 16 as a reset signal. Enter each.

As a result, the pattern counter 18 increments (counts up) in synchronization with the input of the increment signal from the detection timing controller 17, and the shift counter 16 sets the count value to "0" by the input of the reset signal. Reset to.

Further, the shift of the data by the shift register 14 proceeds, the count is incremented by the shift counter 16, the flag detection signal from the pattern match detector 15 becomes active again, and the shift counter 16
Is "7" or "8",
As described above, the detection timing control unit 17 outputs an increment signal to the pattern counter unit 18 and outputs a reset signal to the shift counter unit 16.

The interrupt generation unit 20 includes the pattern counter unit 1
6 is compared with the specified value, and when the count value reaches the specified value, the flag detection interrupt signal and the flag detection status bit signal are activated, and the flag to the clock gate unit 13 is set. / RTC detection signal is reset, and serial clock (DCLK) and serial data (RXD) by clock gate unit 13 are reset.
Is stopped and flag detection is stopped.

At this time, the flag detection interrupt signal and the flag detection status bit signal are kept held, and the resetting of each signal is performed by issuing a pattern detection stop signal from the command decoding unit 12. When the pattern detection stop signal is issued, the clock gate unit 1
3, the output of the serial clock (DCLK) and the serial data (RXD) is stopped, and the flag detection interrupt signal and the flag detection status bit signal are also reset.

When the counter value of the pattern counter section 18 is not "0", a flag detection signal is output from the pattern match detection section 15 (activated), and the counter value of the shift counter section 16 becomes "7" or "8". Otherwise, the detection timing control unit 17 outputs a reset signal to the pattern counter unit 18, and the pattern counter unit 18 resets the counter value to “0” by the input of the signal, and then outputs the next increment signal ( The count-up is performed by the input of the flag detection signal).

At this time, the count value of the shift counter 16 is not referred to, and the count-up and the reset of the shift counter 16 are performed. Thereafter, the above operation is repeated until the flag detection condition is reached or the pattern detection stop signal is issued from the command decoding unit 12.

(2) In the case of the NON_HDLC mode After the issuance of the pattern detection start signal, the detection timing control unit 17 sets the counter value of the shift counter unit 16 to “1”.
It becomes effective when the detection signal from the pattern matching detection section 15 becomes active after exceeding "3". If the activated detection signal is an EOL detection signal, the detection timing control unit 17 outputs the detection signal to the interrupt signal generation unit 2
0 to make the EOL detection interrupt signal and the EOL detection status bit signal active.

The EOL detection interrupt signal is reset when the data is shifted by the next serial clock (DCLK) input to the shift register section 14 and the pattern does not match, but the EOL detection status bit signal is retained. Is done. The EOL status bit signal is reset after the status bit data signal is output from the three-state buffer unit 21 onto the data bus by the status read signal issued from the command decode unit 12.

When the activated detection signal is an RTC detection signal, the detection timing control section 17 outputs a signal corresponding to the signal, and outputs the signal to the pattern counter section 1.
8 is used as an increment signal as the shift count unit 1
6 is input as a reset signal. Thereby, the pattern counter section 18 counts up in synchronization with the input of the increment signal, and the shift counter section 16 resets the counter value to “0” by the input of the reset signal.

Here, EOL is used as the RTC detection pattern.
If the pattern has been selected, the shift of the data by the shift register section 14 further proceeds, the count is performed by the shift counter section 16, the EOL detection signal from the pattern matching detection section 15 becomes active again, and the shift counter When the counter value of the unit 16 is “12”, the detection timing control unit 17
Thus, the output of the increment signal to the pattern counter section 18 and the output of the reset signal to the shift counter section 16 are performed.

When the EOL pattern + TAG pattern is selected as the RTC detection pattern, the EOL + TAG detection signal from the pattern coincidence detection section 15 becomes active again, and the counter value of the shift counter section 16 is "13". In this case, the detection timing control unit 17 outputs an increment signal to the pattern counter unit 18 and a reset signal to the shift counter unit 16 as described above. At this time, if the count value of the pattern counter unit 18 is not “0”, the active output of the EOL detection interrupt signal is masked.

The interrupt generation unit 20 includes the pattern counter unit 1
8 (count value) and a specified value, and when the count value reaches the specified value, activates the RTC detection interrupt signal and the RTC detection status bit signal and resets the flag / RTC detection signal. And the serial clock (DCLK) by the clock gate unit 13,
The output of the serial data (RXD) is stopped, and the flag detection is stopped.

At this time, the RTC detection interrupt signal and the RTC
The detection status bit signal remains held, and each signal is reset by issuing a command of the pattern detection stop signal from the command decoding unit 12. When the pattern detection stop signal is issued, the output of the serial clock (DCLK) and the serial data (RXD) by the clock gate unit 13 is stopped, and the RTC detection interrupt signal and the RTC detection status bit signal are also reset.

When the counter value of the pattern counter unit 18 is not "0", the pattern match detection unit 15
When the detection signal or the EOL pattern + TAG detection signal is output (becomes active) and the counter value of the shift counter unit 16 is not the above value (12/13), the detection timing control unit 17 sets the pattern counter unit 1
8, the pattern counter 18 resets the counter value to “0” by the input of the signal, and then counts up by the input of the next increment signal (EOL detection signal or EOL pattern + TAG detection signal). Do.

At this time, the count value of the shift counter 16 is not referred to, and the count-up and the reset of the shift counter 16 are performed. Thereafter, the above operation is performed at RT
This is repeated until the C detection condition is reached or a pattern detection stop signal is issued from the command decoding unit 12.

According to the facsimile apparatus having the pattern detecting section 11, the same effects as those of the above-described facsimile apparatus can be obtained. Further, when the pattern detection unit 11 detects the flag / EOL (+ TAG) pattern for the specified number of consecutive times, the flag / RTC detection is notified, so that the probability of erroneous detection due to data application or the like is reduced. Furthermore, since the EOL detection and the RTC detection are notified separately,
The end of the line and the end of one page can be clearly known. Furthermore, EOL / RTC
There is no need to perform detection, and the load on the communication control unit 8 is reduced, so that high-speed operation can be supported. Also, the flag / R
Communication problems due to erroneous TC detection are eliminated.

Next, the operation of the facsimile apparatus having the pattern detector 11 shown in FIG. 4 according to the third aspect of the present invention will be described. Now, when an address, a chip select signal, data, and a write pulse are output by the communication control unit 8 in FIG. 2, the command decode unit 12 inputs the address, the chip select signal, and the write pulse as described above.

The CPU command is generated by decoding the address. If the CPU command is a set signal to the control register unit 19, the control register unit 19 inputs the set signal and outputs the set signal to the data bus. The detection mode, the detection pattern, and the number of continuous detections (the number of continuous detections) that are data are set. The detection mode,
The setting of the detection pattern and the number of continuous detections can be selected by ON / OFF of the corresponding bit of the control register unit 19.

Here, the detection modes include an HDLC mode and a NON_HDLC mode.
1 is a flag pattern (011) in the HDLC mode.
11110) is notified to the communication control unit 8 as a flag detection when it is detected continuously for the set number of times. In the case of the NON_HDLC mode, the EOL pattern (000000000000)
When 1) is detected, it is notified to the communication control unit 8 as EOL detection, and the EOL pattern (0000000000001) or the EOL pattern + TAG pattern (00000000) is detected.
0010011) is notified as RTC detection when it is detected for the set number of times in a row. The detection pattern (EOL / EOL + TAG) in the RTC detection can be selected.

Next, when a pattern detection start signal is issued from the command decode unit 12, the clock gate unit 13 receives the signal and inputs the same to the shift register unit 1 as described above.
The output of the serial clock (DCLK) and serial data (RXD) of the modem unit 9 to the modem 4 and the output of the serial clock (DCLK) to the shift counter 16 are started.

Then, the shift counter section 16 counts the serial clock (DCLK) from the clock gate section 13 and performs a reset when a reset signal is input from the detection timing control section 17.
4 latches the serial data input (RXD) from the clock gate unit 13 at the rising edge of the serial clock (DCLK) and performs parallel output.

Then, the pattern coincidence detecting section 15 compares the parallel output of the shift register section 14 with the pattern selected and set by the pattern selection signal (detection mode) from the control register section 19 and the TAG (detection pattern). When it detects that the output matches the pattern, it activates the corresponding signal and outputs it to the detection timing control unit 17.

A description will be given below for each set detection mode. (1) In case of HDLC mode After issuing the pattern detection start signal, the detection timing control section 17 sets the count value of the shift counter section 16 to “1”.
When the flag detection signal from the pattern coincidence detection section 15 becomes active after exceeding "3", a corresponding signal is output, and the corresponding signal is output to the pattern counter section 18 as an increment signal and to the shift counter section 16 as a reset signal. Enter each.

As a result, the pattern counter section 18 increments (counts up) in synchronization with the input of the increment signal from the detection timing control section 17, and the shift counter section 16 sets the count value to "0" by the input of the reset signal. Reset to.

Further, the shift of the data by the shift register 14 proceeds, and the shift counter 16 counts up. The flag detection signal from the pattern match detector 15 becomes active again, and the shift counter 16
Is "7" or "8",
As described above, the detection timing control unit 17 outputs an increment signal to the pattern counter unit 18 and outputs a reset signal to the shift counter unit 16.

The interrupt generation unit 20 includes the pattern counter unit 1
6 (the count value) and the output of the control register unit 19 (the number of consecutive detections), and when the count value reaches the number of consecutive detections, a flag detection interrupt signal and a flag detection status bit signal are output. At the same time, the flag / RTC detection signal to the clock gate unit 13 is reset and the serial clock (DCLK) and serial data (RXD) by the clock gate unit 13 are reset.
Is stopped and flag detection is stopped.

At this time, the flag detection interrupt signal and the flag detection status bit signal are kept held, and the resetting of each signal is performed by issuing a pattern detection stop signal from the command decoding unit 12. When the pattern detection stop signal is issued, the clock gate unit 1
3, the output of the serial clock (DCLK) and the serial data (RXD) is stopped, and the flag detection interrupt signal and the flag detection status bit signal are also reset.

When the counter value of the pattern counter section 18 is not "0", a flag detection signal is output from the pattern match detection section 15 (activated), and the counter value of the shift counter section 16 becomes "7" or "8". If not, the detection timing control unit 17 outputs a reset signal to the pattern counter unit 18, and the pattern counter unit 18 sets the counter value to “0” by the input of the signal.
After the reset, the count is incremented by the input of the next increment signal (flag detection signal).

At this time, the count value of the shift counter unit 16 is not referred to, and the count up and the reset of the shift counter unit 16 are performed. Thereafter, the above operation is repeated until the flag detection condition is reached or the pattern detection stop signal is issued from the command decoding unit 12.

(2) In the case of the NON_HDLC mode After the issuance of the pattern detection start signal, the detection timing control section 17 sets the counter value of the shift counter section 16 to “1”.
It becomes effective when the detection signal from the pattern matching detection section 15 becomes active after exceeding "3". If the activated detection signal is an EOL detection signal, the detection timing control unit 17 outputs the detection signal to the interrupt signal generation unit 2
0 to make the EOL detection interrupt signal and the EOL detection status bit signal active.

The EOL detection interrupt signal is reset when the data is shifted by the next serial clock (DCLK) input to the shift register unit 14 and the pattern does not match, but the EOL detection status bit signal is retained. Is done. The EOL status bit signal is reset after the status bit data signal is output from the three-state buffer unit 21 onto the data bus by the status read signal issued from the command decode unit 12.

If the activated detection signal is an RTC detection signal, the detection timing control section 17 outputs a signal corresponding to the signal, and outputs the signal to the pattern counter section 1.
8 is used as an increment signal as the shift count unit 1
6 is input as a reset signal. Thereby, the pattern counter section 18 counts up in synchronization with the input of the increment signal, and the shift counter section 16 resets the counter value to “0” by the input of the reset signal.

Here, EOL is used as the RTC detection pattern.
If the pattern has been selected, the shift of the data by the shift register section 14 further proceeds, the count is performed by the shift counter section 16, the EOL detection signal from the pattern matching detection section 15 becomes active again, and the shift counter When the counter value of the unit 16 is “12”, the detection timing control unit 17
Thus, the output of the increment signal to the pattern counter section 18 and the output of the reset signal to the shift counter section 16 are performed.

When the EOL pattern + TAG pattern is selected as the RTC detection pattern, the EOL + TAG detection signal from the pattern coincidence detection section 15 becomes active again, and the counter value of the shift counter section 16 is "13". In this case, the detection timing control unit 17 outputs an increment signal to the pattern counter unit 18 and a reset signal to the shift counter unit 16 as described above. At this time, if the count value of the pattern counter unit 18 is not “0”, the active output of the EOL detection interrupt signal is masked.

The interrupt generation unit 20 includes the pattern counter unit 1
8 (count value) and the output of the control register unit 19 (the number of continuous detections), and when the count value reaches the set number of continuous detections, the RTC detection interrupt signal and the RTC detection status bit signal are output. Activate and reset the flag / RTC detection signal to reset the serial clock (DCLK),
The output of the serial data (RXD) is stopped, and the flag detection is stopped.

At this time, the RTC detection interrupt signal and the RTC
The detection status bit signal remains held, and each signal is reset by issuing a command of the pattern detection stop signal from the command decoding unit 12. When the pattern detection stop signal is issued, the output of the serial clock (DCLK) and the serial data (RXD) by the clock gate unit 13 is stopped, and the RTC detection interrupt signal and the RTC detection status bit signal are also reset.

When the counter value of the pattern counter 18 is not "0", the pattern match detector 15
If the detection signal or the EOL pattern + TAG detection signal is output (becomes active) and the count value of the shift counter unit 16 is not the above value (12/13), the detection timing control unit 17 sets the pattern counter unit 1
8, the pattern counter 18 resets the counter value to “0” by the input of the signal, and then counts up by the input of the next increment signal (EOL detection signal or EOL pattern + TAG detection signal). Do.

At this time, the count value of the shift counter 16 is not referred to, and the count-up and the reset of the shift counter 16 are performed. Thereafter, the above operation is performed at RT
This is repeated until the C detection condition is reached or a pattern detection stop signal is issued from the command decoding unit 12.

According to the facsimile apparatus having the pattern detecting section 11, the same effects as those of the facsimile apparatus having the pattern detecting section 11 shown in FIG. 1 can be obtained. Further, the pattern detection unit 11 sets the flag / EOL (+ TAG)
Flag is detected when the pattern is detected continuously for the set number of times.
Since the C detection is notified, the communication control unit 8 reduces the probability of erroneous detection due to data application and preferentially performs flag / RTC detection (over erroneous detection).
(User) can be selected.

Further, similarly to the facsimile machine described above, the pattern detecting section 11 of the embodiment separately notifies the EOL detection and the RTC detection, so that the end of the line and the end of one page can be clearly known. Furthermore, the communication control unit 8
Eliminates the need to perform EOL / RTC detection,
Since the load on the communication control unit 8 is reduced, it is possible to cope with high speed. In addition, communication failure due to erroneous detection of the flag / RTC is eliminated. Therefore, it is possible to design a facsimile apparatus that utilizes the design concept of the user.

When the reception state of the modem unit 9 is good, the set value may be reduced to increase the probability of pattern detection. Further, in the case of the protocol, it is preferable to set the pattern detection to be performed at least twice with emphasis on certainty. The embodiment in which the present invention is applied to a facsimile apparatus has been described above. However, the present invention is not limited to this, and can be applied to various electronic apparatuses equipped with a communication device such as a digital copying machine.

[0088]

As described above, according to the present invention, a conversion circuit for converting parallel data into serial data is not required, and the cost can be reduced. Also,
Even when the HDLC function is used, the flag pattern can be counted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a pattern detection unit 11 of FIG.

FIG. 2 is a block diagram illustrating a configuration example of a facsimile apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating another configuration example of the pattern detection unit 11 of FIG. 2;

FIG. 4 is a block diagram showing still another configuration example of the pattern detection unit 11;

[Explanation of symbols]

 1: System control unit 2: System memory unit 3: Image memory unit 4: Encoding / decoding unit 5: Recording unit 6: Reading unit 7: Operation unit 8: Communication control unit 9: Modem unit 10: NCU unit 11: Pattern detection unit 12: Command decoding unit 13: Clock gate unit 14: Shift register unit 15: Pattern match detection unit 16: Shift counter unit 17: Detection timing control unit 18: Pattern counter unit 19: Control register unit 20 Interrupt generation unit 21: 3 state buffer section

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 29/10 H04L 7/08 H04N 1/32 H04N 1/36

Claims (4)

(57) [Claims] An output / stop means connected to a serial interface of a modem for outputting / stopping a serial clock input of the modem according to a condition; and a serial data input of the modem latched at a rising edge of the serial clock to be parallelized. Parallel output means for outputting, pattern setting means for setting a pattern to be compared with the parallel output output from the means, and comparison of the parallel output output from the parallel output means with the pattern set by the pattern setting means Pattern matching detecting means for outputting a corresponding signal when the parallel output matches the pattern, notifying means for notifying a control unit when the signal is output from the means, Decodes the address output from and controls each of the above means And a control signal generating means for generating a signal for generating a pattern. 2. An output / stop means connected to a serial interface of a modem for outputting / stopping a serial clock input of the modem in accordance with a condition, and latching a serial data input of the modem at a rising edge of the serial clock for parallel operation. Parallel output means for outputting, pattern setting means for setting a pattern to be compared with the parallel output output from the means, and comparison of the parallel output output from the parallel output means with the pattern set by the pattern setting means Pattern matching detecting means for outputting a signal corresponding to the detection that the parallel output matches the pattern; latch number counting means for counting the number of latches by the parallel output means; According to the output of the detection means A predetermined signal output unit that outputs a predetermined signal, an output number counting unit that counts the number of outputs by the unit, a notification unit that notifies a control unit when the output number counted by the unit reaches a specified value, And a control signal generating means for decoding an address output from said control section and generating a signal for controlling each of said means. 3. An output / stop means connected to a serial interface of a modem for outputting / stopping a serial clock input of the modem in accordance with a condition, and latching a serial data input of the modem at a rising edge of the serial clock for parallel processing. Parallel output means for outputting, pattern setting means for setting a pattern to be compared with the parallel output output from the means, and comparison of the parallel output output from the parallel output means with the pattern set by the pattern setting means Pattern matching detecting means for outputting a signal corresponding to the detection that the parallel output matches the pattern; latch number counting means for counting the number of latches by the parallel output means; According to the output of the detection means Predetermined signal output means for outputting a predetermined signal; output number counting means for counting the number of outputs by the means; continuous detection number means for setting a continuous detection number; and the number of outputs counted by the output number counting means. Notification means for notifying the control unit when the value set by the continuous detection number setting means is reached, and a control signal for decoding an address output from the control unit and generating a signal for controlling the respective means A pattern detection circuit comprising a generation unit. 4. A facsimile apparatus comprising the pattern detection circuit according to claim 1.