JP3019740B2 - Serial interface and serial data transfer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface circuit and a serial interface system, and more particularly to a synchronous serial interface and a serial interface system for serially transferring data in synchronization with a transfer clock.

[0002]

2. Description of the Related Art Since a synchronous serial interface transfers data serially in synchronization with a transfer clock, a circuit for generating a transfer clock is not required in a receiving system. Therefore, the circuit scale can be made smaller than that of the non-homogeneous serial interface, and it is widely used as a data transfer means between one-chip computers or a one-chip microcomputer and a peripheral I / O which is restricted in chip area.

[0003] The serial interface in the receiving system takes in serial data transferred from the transmitting system in synchronization with the transfer. Specifically, the serial interface works on the data by using the level inversion edge of the clock. Therefore, when the level of the transmission line connecting the transmitting side and the receiving side system changes due to noise, the receiving side system:
The level change due to the noise is regarded as the level change of the transfer clock, and as a result, the data at that time is used. That is, the same data is worked on a plurality of times. Since the receiving system operates based on such data, it naturally causes a malfunction.

Therefore, noise is required to detect a change in level of a transmission line. A means for this purpose is disclosed in Japanese Patent Application Laid-Open No. 2-81246.

In this method, a third signal path is provided in addition to a serial clock transfer line and a serial data transfer line for connecting clock terminals and terminals between a transmission system and a reception system, respectively. Is fed back to the transmission system via the third signal path, while the transmission system creates a reference timing signal based on the transfer timing of the serial clock and compares these. According to such a configuration, when a level change occurs in the serial clock transfer line due to noise, a difference occurs between the timing signal in the receiving system and the reference timing in the transmitting system, and as a result, the noise can be detected.

[0006]

However, in such a configuration, the clock timing signal is fed back via the third signal transfer line, so that the level of the third signal transfer line changes due to noise. is there. Such a level change is regarded as a clock timing signal in the receiving system in the transmitting system, and is processed as noise mixed into the clock transfer line. As a result, data transfer is restarted from the beginning, and there is a problem that data transfer efficiency is deteriorated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a serial interface and a serial data transfer system provided with a means for detecting noise mixing in a serial clock transfer line without deteriorating data transfer efficiency.

[0008]

A serial interface according to the present invention is connected to a serial clock terminal and generates a timer signal after a lapse of a predetermined time from the start of serial data transfer. A counter for counting, and means for detecting a count state of the counter in response to the timer signal and generating an error signal when the count state is not a predetermined count state.

[0009]

That is, the present invention focuses on the fact that the number of bits of data transmitted in one transfer is determined to be, for example, 8 bits, and sets the period of the timer signal generated by the timer means to 8 bits of data. It is slightly shorter than the time required for receiving. Therefore, when noise is not mixed into the clock terminal, the count value of the counter at the time when the timer signal is generated is 7 in the above example. However, when noise is mixed, the counter value depends on the number and the width of the noise. 7
Takes a value other than. Therefore, it can be determined whether or not there has been an error communication based on the count state. Moreover,
Unlike the conventional example, since the clock transfer timing on the transmission side is not compared with the clock reception timing on the reception side, no malfunction occurs.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 is a diagram showing an embodiment of the present invention. The synchronous serial interface according to the present embodiment has a transmission system 1 and a reception system 2.

The transmission system 1 includes an internal bus 11, an 8-bit shift register 12, an inverter 13, a counter 14 capable of setting its count value in a programmable manner, a clock generated by a clock generator divider circuit 16, a counter 14, and a shift register. A gate circuit 15 for controlling transmission to the transmission system 12 and the like; a data processing device 17 for performing data processing of the transmission side system 1;
2. It has a serial data output terminal 24 and a serial clock output terminal 25. These output terminals 24, 25
Are connected to the receiving system 2 via a serial data line 44 and a serial clock line 45, respectively.

On the other hand, the receiving system 2 includes an internal bus 31,
Shift register 32 of an 8-bit shift register, serial data input terminal 41, serial clock input terminal 42, input buffers 38 and 39, clock input terminal 42
And a data processing device 37 for counting the level change of the data. According to the present invention, the receiving system 2 further includes a D flip-flop 34, a timer 35 capable of setting the output time in a programmable manner, and a D flip-flop 36 latching the output of the counter 33 by the output of the timer 35. The output of the flip-flop 36 is supplied to the error output terminal 43 via the output buffer 40. This terminal 43 is connected to the error input terminal 26 of the transmission system 1 via the error transfer line 46. The transmission system 1 further has an error signal detection circuit 27, which has an input buffer 23, a delay circuit 20, an AND gate 19, and an SR flip-flop 18. Next, the operation of the present system will be described. In the transmission system 1, the data processing device 17
Has overall control. When the data processing device 17 receives a serial data transfer request to the receiving system 2 by executing a program or the like, the data processing device 17 transfers 8-bit data to be transferred to the shift register 12. Further, the data processing device 17 outputs a START signal to the counter 14, the gate circuit 15, and the RS flip-flop 18. The counter 14 and the RS flip-flop 18 are reset by the START signal, and the gate circuit 15 is opened to output the transfer clock from the clock generator frequency dividing circuit 16. The transfer clock is input to the shift register 12 via the inverter 13 as a shift clock.

The shift register 12 shifts the data stored therein in order from the most significant bit MSD in synchronization with the rising edge of the shift clock, that is, the falling edge of the transfer clock. The buffer 21 is connected to the serial data output terminal 2 based on the output data.
4, which drives the serial data transfer line 44 high or low.

The transfer clock is further supplied to the output buffer 22. As a result, the serial clock line 45 is driven to a high level and a low level via the clock terminal 25, and the serial transfer clock SCK is output on the line. Before the start of the transfer, the output buffer 22 keeps the clock terminal 25 (clock line 45) at a high level.

The transfer clock is further supplied to a counter 14. The counter 14 increments the count value at every rise of the transfer clock, and when the coefficient value becomes 8, generates a transmission completion signal 14-1. The signal 14-1 is supplied to the data processing device 17 and is also input to the gate circuit 15 to close the gate circuit 15.

Thus, the 8-bit data to be transferred is transferred to the receiving system 2 bit by bit in synchronization with the serial clock SCK.

In the receiving system 2, as shown in the timing chart of FIG. 2, the D flip-flop 36 and the counter 33 are reset by the set signal SET generated from the data processing device 37 based on the end of the previous serial data transfer. And the D flip-flop 34 is set. The timer 35 is reset upon receiving the set Q output of the D flip-flop 34. That is, as an initial state, the output of the counter 33 is low, the output of the D flip-flop 34 is high, the output of the D flip-flop 36 is low, and the output of the timer 35 is low.

In this state, when the data transfer from the transmission system 1 is disclosed as described above, the clock input terminal 42 receives a level change as shown in FIG. 2 by the serial clock SCK on the serial clock line 45, The change is shaped by the input buffer 39 and supplied to the shift register 32 as a shift clock.
The data transferred on the data line 44 is transferred to the data input terminal 41, shaped by the input buffer 38, and transmitted to the input of the shift register 32. The shift register 32 sequentially takes in and transmits data transmitted after input in synchronization with the rising edge of the shift clock. The shift lock is also supplied to the counter 33, and the counter 33 increments its count value at the rise of the clock. When the count value reaches 8, the counter 33 changes its output to a high level and supplies it to the data processing device 37 as a transfer end signal.

The shift clock is further supplied to a flip-flop 34 as a clock input. Therefore, at the first falling edge of the mift clock, that is, at the start of serial transfer, the output of flip-flop 34 goes low. The reset of the timer 35 is released by the low-level signal, and the timer operation is started. Although the timer 35 is output after a predetermined time has elapsed to a high level, in this embodiment, as shown in FIG. 2, the timer set time t ₂ timer output from the serial transfer start becomes high level, one data Time t ₁ required for transfer
The time is set to be shorter by the clock of the serial clock SCK. Therefore, as shown in FIG. 2, when there is no noise in the serial clock line 45, the output of the counter 33 at the time when the output of the timer 35 becomes high level remains at low level. This low level is sampled by the flip-flop 36, held as a low level output, and supplied to the data processing device 37. Note that the timer 35 can be configured by a counter that counts a reference clock or a multivibrator.

The data processing device 37 receives the transfer end signal from the counter 33 as an interrupt request, temporarily suspends the process currently being executed, and activates the interrupt process. In such interrupt processing, the data processing device 37 first checks the output level of the flip-flop 36. Since the output of the D flip-flop 36 shown in FIG. 2 is at a low level, the data processing device 37 determines that serial data reception has been completed normally, accesses the shift register 32, and transfers the transferred 8-bit data. Capture via internal bus. Then, a SET signal is generated to set the above-mentioned initial state. Thereafter, the interrupted processing is resumed. Alternatively, processing on data taken in from the shift register 32 may be performed.

However, as shown in FIG. 3, when noise is mixed in the serial clock line 45 during data reception and a level change based on the noise occurs at the clock input terminal 42, the shift register causes the same bit to be changed by the level change. Data will be acquired twice. That is, a data reception error has occurred due to noise. Such an error is detected as follows.

That is, the counter 33 advances its count value by one according to the level change of the clock input terminal 42 based on the noise, so that the counter 33 increases by the arrival of the seventh rising edge by the normal serial clock SCK.
Has a count value of 8, and sets its output to a high level. On the other hand, the timer 35 since the timer time t ₂ to its output to a high level is constant, the timer output after the output of counter 33 becomes high level to the high level. Therefore, the D flip-flop 36 is connected to the counter 3
3 is sampled at the rise of the output of the timer 35, and the output is set to the high level.
This high level output is supplied to the data processing device 37 as a communication error signal.

As described above, the data processing device 37 checks the output of the flip-flop 36 by the interrupt process based on the high-level output from the counter 33.
Since the output is at the high level, it is determined that a communication error has occurred. Therefore, the data fetched into the shift register 32 is discarded, the SET signal is output, the counter 33 and the D flip-flop 36 are reset, and the D flip-flop 34 is set to prepare for re-transfer. The communication error signal is further supplied to the output buffer 40. The output buffer 40 thereby drives the error transfer line 43 to a high level, and notifies the receiving side system 1 of the error.
This signal is supplied to the error input terminal 26 of the supply system 1 and the buffer 23, the delay circuit 20, the AND gate 1
9, the flip-flop 18 is set. In the transmission system 4, as described above, when the 8-bit data transfer is completed, the counter 14 generates the transmission end signal 14-1. Based on this signal, the data processing device 17 checks the output level of the flip-flop 18. Since the output level is high, it is determined that a communication error has occurred, and data retransmission is started. Note that the delay circuit 20 and the AND gate 19 constitute a noise removing circuit for preventing the flip-flop 18 from being set even when the error transfer line 46 temporarily becomes high level due to noise.

Thus, in this embodiment, the communication error is detected by the communication system itself, and the problem as shown in the conventional example does not occur. Also, the communication error is fed back to the communication system 1 via the error transfer line 46, but the operation is static, and therefore, the above-described noise elimination circuit can be provided, and the erroneous communication error can be provided. Is not determined by the transmission system 1.

FIG. 4 is a diagram showing another embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, an OR circuit 51 is further provided, the output of which is connected to the reset terminal of the counter 33, and the two inputs of which are connected to the D flip-flop 36 and the output of the data processing device 37, respectively. I have. With this configuration, when the D flip-flop 36 detects a transfer error signal, the counter 33 can be quickly reset.

As described above, in the embodiment shown in FIGS. 1 and 4, the counter 33 is set to the high level when the count value reaches 8, and the counter 33 at the time when the timer output occurs is utilized. By sampling the output, the count state at the time when the timer output of the counter 33 occurs is detected, and it is determined whether or not a communication error has occurred.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the present invention is not limited to the above-described configuration. For example, both the transmission system and the reception system may be provided with circuits for both data reception and transmission, and a mode flag may be provided, and the mode may be switched between the transmission mode and the reception mode. Instead of supplying the output of the flip-flop 36 to the output buffer 40, the data processing device 37 can generate an error signal. Further, data transfer of a bit number other than 8 bits can be similarly performed. Needless to say, each of the gate circuits and flip-flops shown in FIGS. 1 and 4 can be realized by another gate circuit or the like having a similar function. Furthermore, a case has been described where the number of noise occurrences is shorter than the timer set time due to noise. However, if the contents of the counter 33 are decoded by the timer output, the noise generated in the transfer clock is large and completely high level. The error can be detected according to the present invention even in the case where the signal disappears. That is, in the case of the transfer without error, the counter 33 when the timer output is generated is 7 in the above embodiment. Therefore, as shown in FIG. 5 as still another embodiment of the present invention, the counter 33
The decoder 50 is provided for decoding the count value of, and the decoder 50 is activated by a high-level timer output from the timer 35. That is, the decode 50 decodes the count value at the time when the timer output is generated, and detects whether the count value is 7. At 7, the output remains at the low level, but at other than 7, the output is set to the high level and the RS flip flip 51 is set. Thus, a communication error is detected irrespective of the number and width of the noise mixed. OR gate 5
2, the transfer completion is notified to the device 37.

In each of the above embodiments, error detection may be performed using a counter provided separately from the counter that generates the reception end signal.

[0031]

As described above, according to the present invention, a serial transfer error signal can be output only on the receiving side. In addition, by instructing the transmission side system to retransmit by the transmission error signal, an error detection circuit can be provided in the transmission side system, and there is no influence of noise mixed into the error transmission line. Therefore, retransmission of serial data due to noise on the error transfer line is eliminated, so that transfer efficiency is improved and highly reliable serial data communication can be realized.

In addition, according to the present invention, an existing system can be used as it is without adding a special circuit to the transmitting side, and the receiving side system has one timer and two flip-flops in comparison with the conventional circuit. With few additional circuits. Further, if a general-purpose timer built in a one-chip microcomputer is used for the timer unit, the number of circuits to be used can be further reduced, and a one-chip computer having a chip size restriction can be easily realized.

According to the configuration of the second embodiment, when a communication error occurs, the counter can be reset without the intervention of the data processing device, which has the effect of reducing the load on the data processing device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an operation timing chart of the receiving system shown in FIG. 2 when there is no noise.

FIG. 3 is a timing chart of the receiving system shown in FIG. 1 when noise is mixed.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing still another embodiment of the present invention.

[Explanation of symbols]

 1 Transmission system 2, 3 Receiving system 11, 31, 70, 90 Internal bus 12, 31, 72, 92 Shift register 13, 99, 100, 101, 105 Inverter 14, 33, 73, 93 Counter 24 Data transfer line output terminal 25 Serial clock output terminal 26 Error transfer line input terminal 27 Error transfer line input terminal 34, 36, 95, 96 D flip-flop 35 Timer 41 Data transfer line input terminal 42 Serial clock line input terminal 43 Error transfer line output terminal 44 Data transfer Line 45 Serial clock line 46 Error transfer line

Claims (3)

(57) [Claims] 1. A serial data transfer system comprising: a transmission unit that outputs serial data in synchronization with a transfer clock; and a reception unit that receives the serial data in synchronization with the transfer clock sent from the transmission unit. Wherein the receiving unit counts the transfer clock for a predetermined time from the start of the serial data reception and outputs a count state, and detects the count state output by the count means after the predetermined time, and sets the count state to a predetermined value. Cow count does not exceed the value <br/> time is given to generate an error signal of the first logic level
Detecting means for generating an error signal of a second logical level when the error signal exceeds the logical value, and for detecting the serial data transferred from the transmitting unit when the error signal is at the first logical level. A serial data transfer system, wherein the serial data is retransmitted to the receiving unit when the error signal sent from the receiving unit is at a second logical level. . 2. The method according to claim 1, wherein the counting means includes a counter for the transfer clock.
The number of level changes required for one serial data reception
When the number of occurrences occurs, the count state is changed to the first logic level.
To the second logic level, and the detecting means
After a predetermined time, the logic level of the count state is sampled.
Based on the sampled logic level
2. The serial data transfer according to claim 1, wherein the error signal is generated.
system. 3. A transmission unit having a clock output terminal and a data output terminal, a reception unit having a clock input terminal and a data input terminal, and the clock output terminal and the data output terminal of the transmission unit and the reception unit having the data output terminal. A clock line and a data line for connecting the clock input terminal and the data input terminal, respectively, wherein the transmission unit transfers the serial clock onto the clock line via the clock output terminal while transmitting the serial clock via the data output terminal. In a serial data transfer system for transferring serial data to the data line, wherein the receiving unit receives data of the data input terminal in response to a level change appearing at the clock input terminal and stores the data in a register, , Siri Means for generating a timer signal after a predetermined time from the start of receiving the data, counter means for counting a level change appearing at the clock input terminal, and detecting the count value of the counting means in response to the timer signal. When the count value is a predetermined value, a reception error signal of a first logic level is generated. When the count value is less than the predetermined value or exceeds the predetermined value, a reception error signal of a second logic level is generated. And an error output terminal for outputting the reception error signal. When the reception error signal is at the first logic level, the contents of the register are taken into a data processing circuit, and A transmission unit includes an error input terminal connected to the error output terminal of the reception unit, and an error input terminal connected to the error input terminal. Serial data transfer system when the signal error signal is detected that is supplied, characterized by further comprising a means for re-transmitting the serial data.