JP7057990B2 - Clock synchronous serial data receiving circuit - Google Patents

Description

The present invention has at least three signal inputs of a serial data signal, a serial clock signal, and a select signal, and while the select signal is active, the serial data signal is taken in at the change timing of the serial clock signal. The present invention relates to a clock-synchronized serial data receiving circuit that shifts each time one bit of data is received and converts it into parallel data having a reference number of bits, and a bus system that actively connects a plurality of the clock-synchronized serial data receiving circuits.

A clock-synchronized serial data transfer method is widely used for data transfer between parts in various computer systems, mechanical devices such as game machines, or between boards. In this clock-synchronized serial data transfer method, data is received bit by bit from the serial data transmitted on the data signal line in accordance with the clock of the clock signal (for example, rising timing).

In the clock-synchronized serial data transfer method, the handling of data transmission errors that occur accidentally due to the influence of noise or the like is determined by the design policy of the entire system. Generally, when a transmission error occurs, a process of notifying the other party of the occurrence of the transmission error and requesting re-transmission is performed. However, in the case of a mechanical device that operates in a poor noise environment such as a gaming machine, communication errors occur not a little, so if a retransmission request is made each time, it causes a decrease in throughput and is rapid. It is not preferable because it may hinder the progress of the game.

In addition, when data is transferred periodically at short intervals, even if there is an error in some received data, the request for retransmission is not made, and the error data is simply ignored and not received. You may get the same effect as retransmitting just by waiting for the data in. For example, in the gaming machine described in Patent Document 1, drawing data is transmitted from the effect control board to the lamp connection board in a short cycle of about 2 mS in order to repeatedly drive N × M lamps at high speed. If the drawing data has garbled bits, the drawing data is discarded and the lamp is not driven. In this way, even if the lamp drive due to abnormal drawing data is discarded, there is no problem as a whole due to the relationship between human vision and the lamp lighting cycle.

Japanese Unexamined Patent Publication No. 2009-279252

However, in the invention described in Patent Document 1, it is normal that the basis for detecting an abnormality in the received data by the abnormality detection circuit is only one bit of the content of the received data (common data COM1 to COM4). Other than that, it depends on abnormalities), and it is difficult to apply it to a general-purpose clock-synchronized serial data transfer circuit. That is, unless the abnormality can be detected by such a simple determination condition, it is difficult to properly discard the drawing data that is periodically transmitted in a short period of time.

Further, in general, the fact that bit garbled is caused by the influence of noise means that noise is added to the serial data signal at the rising edge or falling edge (hereinafter referred to as "edge") of the clock signal, and it is originally recognized as H level. It should be mistakenly recognized as L level (or vice versa), but noise is generally a voltage change over a very short period of time, so there is noise in the serial data signal just at the edge timing of the clock signal. Riding is rare.

On the other hand, when noise is added to the clock signal, even if the voltage changes for a short time, it is recognized as an edge by the electronic circuit, so that a data abnormality occurs in which the bit position of the serial data shifts. .. Moreover, no matter which part of the clock signal the noise gets on, a data abnormality will occur, so the frequency of occurrence here is higher.

When the bit position shifts due to such noise, it cannot be detected by the abnormality detection circuit in the invention described in Patent Document 1, and the lamp effect is executed with the bit position shifted from the original position, which is not possible. There is a risk of performing a natural lamp effect.

The present invention has been made in view of the above circumstances, and a clock synchronous serial data receiving circuit that easily detects a transmission error and ignores the data when a clock signal is erroneously recognized due to the influence of noise, and this It is an object of the present invention to provide a bus system for actively connecting a plurality of clock-synchronized serial data receiving circuits.

In order to solve the above problems, the invention according to claim 1 has at least three signal input terminals of a serial data signal, a serial clock signal, and a select signal, while the select signal is active. In a clock-synchronized serial data receiving circuit having a modular structure, the serial data signal is taken in at the change timing of the serial clock signal, shifted every time one bit of data is received, and converted into parallel data having a reference number of bits. The number of the serial clock signals detected while the select signal is active is counted, and when the counted value becomes a natural number multiple of the reference bit number, an acquisition timing determination signal is output and the counted value is calculated. When the number of natural bits becomes +1 by the natural number of the reference bits, the capture timing determination means for stopping the capture timing determination signal and the capture timing determination means during the period when the capture timing determination signal is output by the capture timing determination means. It is characterized by comprising a received data determination means for determining the parallel data as received data only when the select signal becomes inactive.

Further, the invention according to claim 2 makes it possible to output the serial data signal for the next stage in which the serial data signal is shifted by the reference bit number in the clock synchronous serial data receiving circuit according to claim 1. It is characterized by that.

Further, in the invention according to claim 3, at least the serial data signal, the serial clock signal, and the select signal of the reference bit number × M (M is a natural number of 2 or more) are supplied from the master side device, and the said The clock-synchronized serial data receiving circuit according to claim 2 is provided in a slave-side device connected in an M -stage cascade , and from the received data determined by the clock-synchronized serial data receiving circuit of the M-stage. A bus system that actively connects the clock-synchronized serial data receiving circuit of the M stage so that parallel data of "reference bit number x M" can be obtained, and the serial data signal is a predetermined first stage. A serial data signal line supplied only to the serial data signal input terminal in the clock synchronous serial data receiving circuit, and a serial clock supplying the serial clock signal to all serial clock signal input terminals in the clock synchronous serial data receiving circuit. The signal line, the select signal line that supplies the select signal to the select signal input terminals in all the clock-synchronized serial data receiving circuits, and the clock-synchronized serial data receiving circuit of the nth stage (1 ≦ n <M). It is characterized by including a serial data signal output terminal for the next stage in the above, and a serial data signal line for the next stage connecting the serial data signal input terminal in the clock synchronous serial data receiving circuit of the n + 1th stage.

According to the clock synchronous serial data receiving circuit according to the present invention, when a clock signal is erroneously recognized due to the influence of noise, the transmission error can be easily detected and the data can be ignored. Further, according to the bus system according to the present invention, it is possible to realize a clock-synchronized serial data receiving function corresponding to M times the number of reference bits by cascade-connecting M clock-synchronized serial data receiving circuits. ..

It is a schematic block diagram of the gaming machine provided with the clock synchronization type serial data receiving circuit which concerns on this invention. It is a circuit block diagram which shows the embodiment of the clock synchronous type serial data receiving circuit which concerns on this invention. It is a timing chart when normal communication data is received by the clock synchronization type serial data reception circuit of this embodiment. It is a timing chart when abnormal communication data is received by the clock synchronization type serial data reception circuit of this embodiment. It is a schematic block diagram of the slave side device provided with the bus structure which can cascade-connect four clock-synchronous serial data receiving circuits.

Hereinafter, embodiments of the clock-synchronized serial data receiving circuit according to the present invention will be described in detail with reference to the accompanying drawings.

The gaming machine 100 exemplified in FIG. 1 is a pachinko-type gaming machine capable of playing a ball game using a gaming ball. The main control board 200, which is responsible for controlling the main game progress in the game machine 100, controls various game function devices. The sub-control board 300, which mainly performs effect control by a liquid crystal display device, a decorative lamp, or the like provided at a suitable position in the gaming machine 100, transmits a command signal for driving a lamp to, for example, a lamp connection board 400, and receives the command signal. Drive signals are output from the connection board 400 to the various lamps 110, and the lamp effect is executed.

Here, the sub-control board 300 is a master-side device that transmits clock-synchronized serial data, and the lamp connection board 400 is a slave-side device that receives clock-synchronized serial data. The lamp connection board 400 is provided with a clock-synchronized serial data receiving circuit 1 that converts the received clock-synchronized serial data into parallel data and outputs the data. This clock-synchronized serial data receiving circuit 1 is not limited to the pachinko-type gaming machine, and even if it is a spinning-type gaming machine, when the clock-synchronized serial data is transmitted from the master-side device to the slave-side device, the slave It can be used for the side device.

FIG. 2 is a circuit configuration diagram showing an embodiment of the clock-synchronized serial data receiving circuit 1 described above. The clock synchronous serial data receiving circuit 1 has a shift register 11, a latch 12, and a counter 13 as main configurations, and also uses an AND circuit 14, a negative logic or circuit 15a, and a knot circuit 15b. The input signals to the clock-synchronized serial data receiving circuit 1 are a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR.

The clear signal CLR is an H-level negative logic signal at normal times, and is input to the CLR terminal of the latch 12 and the CLR terminal of the shift register 11 and the counter 13 via the or circuit 15a, respectively. Therefore, when the clear signal CLR reaches the L level, the shift register 11, the latch 12, and the counter 13 are initialized.

The select signal SEL is an H-level negative logic signal at normal times, and is input to the CLR terminals of the shift register 11 and the counter 13 via the knot circuit 15b and the or circuit 15a, respectively. When the select signal SEL is at the H level, the shift register 11 and the counter 13 are stopped in the initial state. On the other hand, when the select signal SEL reaches the L level, the CLR terminals of the shift register 11 and the counter 13 become the H level, and the operation is possible.

Further, the output of the AND circuit 14 to which the select signal SEL is given to one of the input terminals remains at the L level until the Q3 output of the counter 13 described later is inverted to the H level and the select signal SEL becomes the H level. Does not fluctuate. Therefore, the output of the latch 12 (for example, 8 bits) holds the previously latched output until the output of the AND circuit 14 changes to the H level and is input to the CK terminal of the latch 12.

The shift register 11 outputs the signal level of the serial data signal SD input to the D terminal to the QA terminal at the rising timing of the serial clock signal SCK input to the CK terminal. At the same timing, the signal level output to the QA terminal is output to the QB terminal. Similarly, the signal of the adjacent terminal is shifted to the QH terminal.

The reception timing of the serial clock signal by the shift register 11 will be described with reference to FIGS. 3 and 4. First, a case where a serial data signal is normally received will be described with reference to FIG.

Since the shift register 11 becomes operable while the select signal SEL is at the L level, the serial data signal is at the timing of the rising edge of each clock pulse in the serial clock signal SCK (including eight clock pulse signals from T1 to T8). It takes in SD data and shifts from QA to QH. Specifically, the data "1" of the first bit is registered in the QA from the serial data signal SD at the rising edge of the first clock pulse T1. Subsequently, at the rising edge of the second clock pulse T2, the second bit data "1" is registered in the QA from the serial data SD, and the first bit data "1" already registered in the QA is shifted to the QB. .. Similarly, the data "0", "0", "1", "0", "1", and "0" of the third to eighth bits are received from the third clock pulse T3 to the eighth clock pulse T8, and by QA to QH. Stores 8 bits of data.

The bit data stored in each of the QA to QH of the shift register 11 is given to the data input terminals D0 to D7 of the latch 12, but the output signal of the AND circuit 14 (detailed later) is sent to the CK terminal of the latch 12. Until it is input, it is not latched by the output terminals Q0 to Q7 of the latch 12. Further, the QH of the shift register 11 can be taken out to the outside of the clock synchronous serial data receiving circuit 1. The signal obtained from this QH is a serial data signal obtained by shifting the serial data signal SD by 8 bits, and can be used as a serial data signal for the next stage (detailed later).

On the other hand, when the select signal SEL reaches the L level and the counter 13 starts operating, it is in the initial state, so the outputs of the Q0 to Q3 terminals remain at the L level. The count value is incremented at the rising edge of the serial clock signal SCK input thereafter, and the result is output in binary from Q0 to Q3. In this counter 13, the output signal TP1 of the Q3 terminal corresponding to the bit 3 becomes H level at the rising timing of the eighth pulse (eighth clock pulse T8) of the serial clock signal SCK.

Further, the output signal TP1 of the Q3 terminal in the counter 13 is input to its own LD terminal. The input signals from D0 to D3 are output from Q0 to Q3 at the rising timing of the CK terminal input when the LD terminal is at H level. In the counter 13 of this configuration example, D0 is connected to the H level and D1 to D3 are all connected to the L level, so that the count values of the Q0 to Q3 outputs return to "1" again. That is, the output signal TP1 of the Q3 terminal changes from the L level to the H level at the 8nth rising edge of the CK terminal after the CLR terminal reaches the H level (n is an arbitrary natural number), and at the 8n + 1st. It will be L level again.

Therefore, the counter 13 "counts the number of serial clock signals detected while the select signal is active, and when the counted value becomes a natural number multiple of the reference bit number (for example, 8), it is captured. It functions as a "capture timing determination means" that outputs a timing determination signal. In the clock synchronous serial data receiving circuit 1 of the present embodiment, since the reference bit number to be output as parallel data is set to 8, the timing (serial clock signal SCK) in which the number of bits of the data to be transferred is considered to be 8. The output signal TP1 of the Q3 terminal, which is the output of the counter 13, is set to H level at the timing when up to 8 clock pulses are counted. However, even when the reference bit number is 16 or 32, the serial clock signal SCK is similarly used. The output signal TP1 of the Q3 terminal may be configured to be H level at the timing when the clock pulse is counted up to 16 or 32.

The Q3 output TP1 of the counter 13 described above is ANDed with the select signal SEL by the AND circuit 14, and is input to the CK terminal of the latch 12. Therefore, only when the select signal SEL reaches the H level after the clock pulse of the serial clock signal SCK input to the clock synchronous serial data receiving circuit 1 becomes 8n and before it becomes 8n + 1. The output signal TP2 of the circuit 14 becomes H level and is input to the CK terminal of the latch 12. When the rising signal (rising edge of the output signal TP2 of the AND circuit 14) is input to the CK terminal, the latch 12 latches the input signals from D0 to D7 and outputs them from Q0 to the Q7 terminal. That is, the first bit (lowest bit LSB) transmitted first is the Q7 terminal, the second bit is the Q6 terminal, the third bit is the Q5 terminal, the fourth bit is the Q4 terminal, and the fifth bit is Q3. The 6th bit is latched to the Q2 terminal, the 7th bit is latched to the Q1 terminal, and the 8th bit (highest bit MSB) transmitted last is latched to the Q0 terminal to obtain an 8-bit parallel signal. Can be done.

Therefore, in the AND circuit 14, when the select signal SEL becomes inactive within the period in which the capture timing determination signal (output signal TP1 of the Q3 terminal) is output by the capture timing determination means (counter 13). It functions as a "received data determination means" for determining parallel data as received data. When the select signal SEL reaches the H level, the input to the CLR terminal of the counter 13 becomes the L level and the operation stops, so that the output signal TP1 of the Q3 terminal becomes the L level. Therefore, the period during which the output signal TP2 of the AND circuit 14 is at the H level is short (see FIG. 3), but the latch operation from the Q0 terminal to the Q7 terminal by the latch 12 operates at the rising edge detection timing to the CK terminal. There is no problem because it does.

Next, a case where the serial data signal cannot be normally received will be described with reference to FIG.

Since noise was added to the serial clock signal SCK and this noise was mistakenly recognized as the clock pulse T5, the 5th pulse was originally the clock pulse T6, the 6th pulse was the clock pulse T7, and the 7th pulse was the clock pulse. The 8th and 8th clock pulses will be counted as T9. Note that noise is often a signal with a very narrow width as shown in FIG. 4, but even if it is a signal with a narrow width, it is normal when the circuit operates based on the rising edge like a clock signal. It is mistaken for a signal.

As described above, when the false detection of the clock pulse due to noise occurs, the output terminals QA to QH of the shift register 11 mistakenly say "01011001" at the timing when the select signal SEL reaches the inactive H level. If data is output and the latch 12 captures the data into the output terminals Q0 to Q7, a communication error occurs, the device operation is executed by an erroneous parallel signal, and there is a risk that the reliability of the device itself is impaired.

Since the clock-synchronized serial data receiving circuit 1 according to the present embodiment includes the counter 13 as the acquisition timing determination means and the AND circuit 14 as the received data determination means, the erroneous data is latched 12 It is possible to prevent the data from being taken into the output terminals Q0 to Q7. That is, since the seventh pulse is normally counted as the clock pulse T8, the output signal TP1 at the Q3 terminal of the counter 13 reaches the H level by detecting the rising edge of the clock pulse T8, and then the clock pulse T9. Since it returns to the L level by detecting the rising edge of, even if the select signal SEL rises to the H level after that, the output signal TP2 of the AND circuit 14 does not become the H level, and the CK terminal of the latch 12 changes at the L level. Therefore, erroneous data is not latched in the output terminals Q0 to Q7 of the latch 12.

As described above, no matter when noise is added to the serial clock signal SCK while the select signal SEL is at the L level, there is a risk of causing an error such that the noise is erroneously detected as a clock pulse. In the clock synchronous serial data receiving circuit 1 of the above, it is possible to prevent the erroneous data from being latched in the output terminals Q0 to Q7 of the latch 12 regardless of the timing at which the erroneous detection of the clock pulse occurs. While the select signal SEL is at the L level, noise may be added to the serial data signal SD, and an error may occur in the data content itself. However, since it is extremely unlikely that noise with an extremely short time width will occur at the same timing as the rising edge of the clock pulse of the serial clock signal SCK, it is considered that there is no problem in practical use.

As described above, according to the clock synchronous serial data receiving circuit 1 according to the present embodiment, when the clock signal is erroneously recognized due to the influence of noise, the transmission error is easily detected and the data is ignored. Therefore, it is possible to prevent the device operation from being executed due to the error data and avoid the risk of impairing the reliability of the device itself.

The clock-synchronized serial data receiving circuit 1 alone according to the present embodiment can only support parallel signal output having a predetermined reference bit number. However, if a plurality of clock-synchronized serial data receiving circuits 1 are functionally connected, it is possible to cope with a number of bits that is a natural number multiple of the reference number of bits. A bus system 2 for functionally connecting a plurality of clock-synchronized serial data receiving circuits 1 will be described with reference to FIG.

The master-side device 301 is a source of clock-synchronized serial data, and a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR are supplied to the slave-side device 401 via a wire harness or the like. .. A bus system 2 is provided on the input side of the slave side device 401 that receives these signals. Further, the bus system 2 shown in the present embodiment has a structure in which up to four clock-synchronized serial data receiving circuits 1 can be functionally connected, and a modularized clock-synchronized serial data receiving circuit 1 can be mounted first. A socket 21, a second socket 22, a third socket 23, and a fourth socket 24 are provided.

When installing a plurality of clock-synchronized serial data receiving circuits 1, it is necessary to install them in order from the first socket 21. Further, the number of sockets to which the clock synchronous serial data receiving circuit 1 is attached is not particularly limited, and M sockets should be provided for cascade connection of M stages (M is a natural number of 2 or more). It's fine. In the bus system 2 shown in FIG. 5, a modularized clock synchronous serial data receiving circuit 1 is attached only to the first socket 21 and the second socket 22, and the third socket 23 and the fourth socket 24 remain empty. It was decided to use. In this case, it is not necessary to mount a dummy module or the like on the empty third and fourth sockets 23 and 24, and only the two clock synchronous serial data receiving circuits 1 mounted on the first and second sockets 21 and 22 are sufficient. It can function as a receiving port for serial data.

The serial data signal line L1 that receives the serial data signal from the master device 301 is connected only to the serial data signal input terminal in the first clock synchronous serial data receiving circuit 1A mounted on the first socket 21 which is the first stage.

On the other hand, the serial clock signal line L2 that receives the serial clock signal SCK from the master side device 301 is the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted on the first to fourth sockets 12 to 24. Connect to each serial clock signal input terminal. The select signal line L3 that receives the select signal SEL from the master side device 301 is the input of each select signal of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted on the first to fourth sockets 12 to 24. Connect to the terminal. The clear signal line L4 that receives the clear signal CLR from the master side device 301 is the clear signal input of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted on the first to fourth sockets 12 to 24. Connect to the terminal. That is, the serial clock signal SCK, the select signal SEL, and the clear signal CLR are supplied to the first to fourth clock synchronous serial data receiving circuits 1A to 1D at the same timing.

The serial data signal output terminal QH for the next stage in the first clock synchronous serial data receiving circuit 1A of the first stage is in the second clock synchronous serial data receiving circuit 1B of the second stage by the serial data signal line L51 for the second stage. It is connected to the serial data signal input terminal, and the serial data signal for the next stage is supplied from the first clock synchronous serial data receiving circuit 1A to the second clock synchronous serial data receiving circuit 1B. Since the serial data signal for the next stage is a serial data signal obtained by shifting the serial data signal SD from the master device 301 by 8 bits, the first bit of the serial data signal SD is the first bit of the rising edge detection of the eighth clock pulse. 2 Clock synchronous serial data reception circuit 1B is supplied to the serial data signal input terminal, and the output of the shift register 11 in the 2nd clock synchronous serial data reception circuit 1B is detected by detecting the rising edge of the 9th clock pulse. The first bit of the serial data signal SD is registered in the terminal QA.

That is, while the select signal SEL is at the L level, 16-bit serial data is transmitted by the serial data signal SD, and 16-bit data is captured by the 16 clock pulses of the serial clock signal SCK. The bits to the 8th bit are output from the output signal line L6B of the 2nd clock synchronous serial data receiving circuit 1B, and the 9th to 16th bits are output from the output signal line L6A of the 1st clock synchronous serial data receiving circuit 1A. Therefore, when the first clock synchronous serial data receiving circuit 1A and the second clock synchronous serial data receiving circuit 1B are cascaded, the serial data having twice the reference bit number (8) and the bit number (16) is supported. Can be made to.

Similarly, if the third clock synchronous serial data receiving circuit 1C is set in the third socket 23, the serial data for the next stage in the second clock synchronous serial data receiving circuit 1B is provided by the serial data signal line L52 for the third stage. The signal output terminal QH and the serial data signal input terminal in the 3rd clock synchronous serial data receiving circuit 1C are connected, and the 1st to 8th bits are from the output signal line L6C of the 3rd clock synchronous serial data receiving circuit 1C. The 9th to 16th bits are output from the output signal line L6B of the 2nd clock synchronous serial data receiving circuit 1B, and the 17th to 24th bits are output of the 1st clock synchronous serial data receiving circuit 1A. Since it is output from the signal line L6A, if the first to third clock synchronous serial data receiving circuits 1A to 1C are connected in cascade, it corresponds to the serial data of the number of bits (24) that is three times the number of reference bits (8). be able to.

Further, if the 4th clock synchronous serial data receiving circuit 1C is set in the 4th socket 24, the serial data signal for the next stage in the 3rd clock synchronous serial data receiving circuit 1C is transmitted by the serial data signal line L53 for the 4th stage. The output terminal QH and the serial data signal input terminal in the 4th clock synchronous serial data receiving circuit 1D are connected, and the 1st to 8th bits are output from the output signal line L6D of the 2nd clock synchronous serial data receiving circuit 1D. The 9th to 16th bits are output from the output signal line L6C of the 3rd clock synchronous serial data receiving circuit 1C, and the 17th to 24th bits are output signals of the 2nd clock synchronous serial data receiving circuit 1B. Since the 25th to 32nd bits are output from the line L6B and the 25th to 32nd bits are output from the output signal line L6A of the 1st clock synchronous serial data receiving circuit 1A, the 1st to 4th clock synchronous serial data receiving circuits 1A to 1D By cascade connection, it is possible to correspond to serial data transfer with a number of bits (32) that is four times the reference number of bits (8).

That is, when M clock-synchronized serial data receiving circuits 1 are cascaded, the next-stage serial data signal output terminal QH in the n-th stage (1 ≦ n <M) clock-synchronized serial data receiving circuit 1 By connecting to the serial data signal input terminal in the clock synchronous serial data receiving circuit 1 of the n + 1th stage, it is possible to correspond to the serial data transfer of the reference bit number × M. According to such a bus system 2, even if the number of driven devices (for example, decorative lamps) connected to the slave side device 401 increases, it can be easily dealt with by increasing the number of bits of serial data. Therefore, there is no need to change the design to increase the signal from the device 301 on the master side, the time and effort for designing is reduced, and there is no need to change the process in the assembly work.

Although the embodiment of the clock synchronous serial data receiving circuit and the bus system according to the present invention has been described above with reference to the accompanying drawings, the present invention is not limited to this embodiment and is described in the scope of claims. As long as the configuration of the above is not changed, it may be carried out by diverting known and existing equivalent technical means.

1 Clock synchronous serial data reception circuit 11 Shift register 12 Latch 13 Counter 14 And circuit 15a Or circuit 15b Knot circuit

Claims (2)

It has at least three signal input terminals, a serial data signal, a serial clock signal, and a select signal, and while the select signal is active, the serial data signal is captured at the change timing of the serial clock signal. In a clock-synchronized serial data receiving circuit with a modular structure that shifts each time bit data is received and converts it into parallel data with a reference number of bits.
The number of the serial clock signals detected while the select signal is active is counted, and when the counted value becomes a natural number multiple of the reference bit number, an acquisition timing determination signal is output and the counted value is output. When becomes a natural number times +1 of the reference bit number, the capture timing determination means for stopping the capture timing determination signal and the capture timing determination means.
A reception data determination means that determines the parallel data as reception data only when the select signal becomes inactive within the period in which the acquisition timing determination signal is output by the acquisition timing determination means.
A clock-synchronized serial data receiving circuit characterized by comprising. The clock-synchronized serial data receiving circuit according to claim 1, wherein the serial data signal for the next stage in which the serial data signal is shifted by the reference bit number can be output .

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