JPS59176812A - Serial data input device - Google Patents

Abstract

PURPOSE:To avoid the transfer of wrong data by using a means to detect the transfer of wrong data due to the external noises, etc. produced during the transfer of data and a means to invalidate the wrong data. CONSTITUTION:If a defective clock is supplied together with a nondefective clock 12 during the transfer of data due to the external noises, etc., the number of clocks exceeds nine. Outputs A and D of a counter 2 are simultaneously set at logical 1 at all times when a one-shot multivibrator 1 is active. In this case, the output of an NAND circuit 4 is set at logical 0. Therefore a reset signal 16 is set at 0. The counter 12 is reset to its initial state with the signal 16, and no counter end signal is delivered from an AND circuit 6 since the output D of the counter 2 is logical 0 when the operation of the vibrator 1 is over. Thus the input is prevented for the wrong data.

Description

[Detailed Description of the Invention] What is this invention? Regarding real data input devices, in particular, if erroneous data transfer occurs due to external noise, etc., this serial data input device uses a counter that counts the number of serially transferred data to detect the malfunction and invalidate the transferred data. be.

When transmitting serial data in a digital data processing device, etc., the number of transferred data is counted, and once the length of one data is counted, the serial data is converted to parallel data by a serial/parallel exchanger and the data is input. . In this case, malfunctions may occur due to external noise or the like during data transfer. Conventional serial data input devices have a drawback in that they do not have sufficient countermeasures against such external noise.

This invention has been made in view of the above points, and is a serial data input device that detects malfunctions caused by external noise etc. using a counter that counts the number of data and prevents incorrect data from being input. The purpose is to provide equipment. This invention will be explained below using the drawings.

FIG. 1 is a block diagram showing the configuration of a serial data input device according to an embodiment of the present invention. In the same figure, 1
is one shot multi pie break, 2 is counter, 3
is a serial/parallel converter, 4 is a NAND circuit, 6 is an AND circuit, 7 is an INV circuit, and 11 is a counter clear signal, which is normally a logical ``1'' and outputs a logical ``0'' when 8-bit data is received. Output. 12 is a clock, 13 is serial data, 14 is a count end signal, and 15 is parallel data. The counter clear signal 11 is a signal that is output after the serial data 13 is normally transferred and read as parallel data 15, and initializes the counter 2. Clock 12 and serial data 13 are transfer signals input from the outside. The count end signal 14 is output at the end of the transfer of the serial data]3. The parallel data 15 is data obtained by converting the input serial data 13 into parallel data by the serial-to-parallel converter 3. The one-shot multi-by-break 1 operates at the rising edge of the clock 12, and its operating time is set to be longer than the clock cycle. Therefore, if normal or lock is input, it is always in the operating state. The counter 2 is a counter that is counted by a clock 12 and has outputs A, B, C, and D, and outputs a count end signal 14 when it counts the number of one data length. The serial-to-parallel converter 3 inputs serial data using a clock 12 and outputs parallel data 15.

FIG. 2 is a timing chart when data is transferred normally. FIG. 3 is a timing chart for invalidating transferred data when a malfunction occurs during data transfer due to external noise or the like.

The operation of the serial data input device shown in FIG. 1 will be explained based on the timing charts of FIGS. 2 and 3.

As shown in Fig. 2, when clock 12 is input, the output of one-shot multivibrator 1 becomes logical "1" at the rising edge, while each terminal of counter 2 is still logical "O11". Therefore, the output of the NAND circuit 4 becomes logical ゛1°°, so that the output of the AND circuit 5 becomes
opens, the reset signal 16 changes from "0" to "1'" and the reset is released. When the lock 12 and the serial data 13 are output normally, eight clocks 12 are output and the output of the counter 2 becomes logical "1".

Serial data 13 is input to the serial/parallel converter 3 by eight clocks 12 and is converted into parallel IyAy data 15. One-shot multi-bye break 1 is always in operation when clocks are input sequentially, and when the operation of one-shot multi-bye break 1 by the 8th clock is completed, that is, at the falling edge 1a of the pulse, the output of INV circuit 7 is activated. is logical°“1′
", and the output of the counter 2 is logical "1", so the output of the AND circuit 6 becomes logical "l'" and outputs the count end signal 14, and at the rising edge 74a, the parallel data 15 is prepared. After the parallel data 15 is read, the counter clear signal 11 causes the output of the AND circuit 5 to be logical 0°, that is, a reset signal 16 is output, and the counter 2 is initialized.

Next, as shown in FIG. 3, if an abnormal clock 12a is input due to external noise or the like during data transfer, the number of clocks becomes nine or more. In this case, when the one-shot multivibrator 1 is in operation, the outputs A and D of the counter 2 always become logical "1" at the same time (Fig.
a, see 2cf). At this time, the output of the NAND circuit 4 becomes logical "0", and the output of the AND circuit 5 also becomes "0'". This means that the reset signal 16 becomes 0°. As a result, the color controller 2 receives the reset signal 1.
6 returns to the initial state (see FIG. 3, 16a), and when the operation of the one-shot multivibrator 1 is completed, the output of the counter 2 is logical "O"", so the counter end signal from the AND circuit 6 is not output. .This way, erroneous transfer data will be ignored and will not be input.

As explained above, the serial data input device according to the present invention is provided with means for detecting this erroneous transfer when data is transferred incorrectly due to external noise, etc., and ignores the data. This has the excellent effect of preventing erroneous data from being transferred.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a serial data input device according to an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the serial data input device shown in FIG. It is a diagram. In the figure, 1 is a one-rayot multi-by-break, 2 is a counter, 3 is a serial Φ parallel converter, and 4 is a NANDA.
ND circuit 6 is an AND circuit, and 7 is an INV circuit.

Claims (1)

[Claims] In an input device for serially transferred data, if erroneous data transfer is performed due to external noise etc. during data transfer, a means is provided to detect this, and a means is further provided to invalidate the transferred data. A serial data input device characterized by: