JPS5866445A - Signal collating circuit - Google Patents

Abstract

PURPOSE:To realize the simplification and flexibility of a signal collating circuit, by setting the clock period of a shift register at the value corresponding to the frequency necessary to regard as an effective signal and using the output signal to a logical arithmetic output of plural shift registers. CONSTITUTION:The value of a receiving signal 10 is shifted successively from an output 31 to an output 34 of a shift register on the basis of a clock signal 40. The period of the signal 40 is set at the value corresponding to an input frequency necessary to regard the signal 10 as an effective signal. The 2nd stage output 32 and an output 35 of a NOT input AND element 22 are led to a reset input. Then outputs 31-34 are all reset when both the signal 10 and the 2nd stage output 32 are set at 0. On the other hand, an OR is secured by an OR element 23 between the output 32 and the 4th stage output 34. Then a ''1'' signal is delivered as an output signal 20 of a signal collating circuit when the output of either stage is set at ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit suitable for receiving digital signals and removing the effects of temporary erroneous signals caused by abnormalities in a transmitting device or a transmission path.

In digital signal transmission/reception circuits, temporary erroneous signals due to noise etc. are generated in the transmitting device or the transmission path, and if this erroneous signal is input directly to the control device etc., the entire system will be affected. This results in extremely low reliability.

One way to eliminate the influence of this erroneous signal is to use a signal verification circuit that receives a digital signal multiple times and only considers the value to be a normal value if the same value r is received for a certain number of consecutive times. may be provided.

FIG. 1 shows an example conventionally used as a signal matching circuit. 11 to 14 constitute shift registers that send values in synchronization with the clock signal 30.

The number of digits in the shift register is determined by how many times the same value must be received consecutively to be considered a valid value. The clock signal 30 is configured such that one pulse is input to each receiving signal, and each time a new receiving signal is received, the previous value is shifted to the previous register. Eventually, the received values will be stored in the shift register in chronological order in chronological order. Outputs 1 to 4 of the shift register are led to a multi-input AND element 15 and a multi-input NOT AND element 16, respectively. A set signal 5 and a reset signal 6 are outputted to the input terminal 17. The output 20 of the flip-flop 17 becomes the output of the signal matching circuit.

If the value of the received signal 10 is "1" continuously, the outputs 1 to 4 of the shift registers 11 to 14 will all be "1", and the output 5 of the multi-input AND element 15 will be "1",
To center the flip-flop 17, the output signal 20
becomes "1". Similarly, the value of the received signal is
0”, the output 6 of the negative input AND element 16 is “1”
As a result, the output signal 20 becomes "0" to reset the flip-flop 17. Received signal 10 temporarily becomes “1”
If the received value becomes "0" and the values of the outputs of the shift registers 11 to 14 do not match, it is regarded as an erroneous signal, and the output signal 20 is held at the previous normal value by the flip-flop 17.

As described above, it is possible to construct a signal matching circuit that deals with the effects of erroneous signals. Many circuit components such as elements 15 and 16 and flip-flop 17 are required, which makes the signal matching circuit complicated, and this signal matching is especially difficult for signals such as 16-bit and 32-bit signals, which are often used in digital signals. If it were to be applied to a circuit, it would require a large amount of hardware as a whole. In addition, if you want to change the number of times necessary to consider it as a valid signal in the circuit created by - [4, the number of digits of shift registers 11 to 14, multi-input AND element 15.1
It is necessary to change the number of inputs (6), which makes the changes extremely complicated, and has the drawback of low flexibility as a signal verification circuit.

An object of the present invention is to provide a signal matching circuit that is configured with a simple circuit and has flexibility.

According to the present invention, the clock cycle of the shift register is set not in accordance with all received signals, but in accordance with the number of times necessary to be considered as a valid signal, and in which the received signal is shifted in accordance with this clock cycle, and under certain conditions. The present invention aims to simplify and make the signal matching circuit more flexible by focusing on completely resetting the shift registers when the error occurs, and using the output signal as a logic operation output of a plurality of shift register outputs.

An embodiment of the present invention will be described below with reference to FIG. The shift register 21 has four digits and outputs the value of the received signal 10 to the shift register output 31 according to the clock signal 40.
34 one after another. clock signal 40
The period of is determined according to the number of inputs required to make the received signal 10 a valid signal. For example, if the same signal is considered valid if it is input four times in a row, the clock signal 40 should be such that one pulse of the signal is input while three reception signals 10 are input. The second stage output 32 of the shift register and the output 35 of the negative input AND element 22 of the received signal 10 are connected to the reset input of the 7ft V register 21, and the received signal 10 and the second stage output 32 of the shift register are connected to the reset input of the 7ft V register 21.
When both of n1 and n1 become "0", all outputs 31 to 34 of the 7-foot register are reset so that all n1 become "0". On the other hand, the second stage output 3 of the shift register 21
2 and the fourth stage output 34 are logically summed by the OR element 23, and when the output of any stage becomes "1", a "1" signal is output as the output signal 20 of the signal matching circuit.

Next, Figure 3 shows the time-series signal value changes of the circuit in Figure 2.
This will be explained using FIG. Fig. 3 shows the case where the received signal 10 changes normally, and shows the case where the received signal 10 is rarely "0" at time 11, but becomes "1" continuously after t2, and This shows the operation in two cases when the value of "1" at the time of t2 becomes town continuously after t2□. In either case, the clock signal 40 is defined so that it is regarded as a valid signal when it takes the same value four or more times in a row.

Also, in this figure, the outputs 31 to 3 of the shift register 21
4 is assumed to change at the positive edge of clock signal 40. First, when the received signal 10 changes from "0" to "1" from tl to t2, the reset input 35 of the shift register 21 becomes "0", the reset is released, and the first positive edge of the clock signal 40 Some t3
and the first stage output 31.t6 which is the second positive edge
At the time point, the second stage output 32rlJ signal is shifted n. When the second stage output 32 becomes "1", the output signal 20 also becomes "1".
” However, three received signals 10 are included between the two positive edges of the clock signal 400, from t to t, and this received signal 10 consists of four consecutive signals from t2 to t and -1. Shift register 2 unless [11]
Since the second stage output 32 of 1 does not become ``1'', it is determined whether it is a valid signal or not. Furthermore, when the received signal 10 continues to take the value "1", the third stage output 33 and fourth stage output 34 of the shift register 21 also become "1", and all "1" signals are set in the shift register 21. Ru. On the other hand, "1" is being received continuously until t21, and this is t.
If it becomes "0" at time 22, the first stage output 31 of the shift register 21 becomes "0" at the time of the first positive edge (t23) of the black 2 signal 40, and then At the time of the second positive edge (t26), the second stage output 32 becomes "0". Then, since the negative input AND element 22's input power becomes "0", the reset power 35 becomes "1", and all the outputs 31 to 34 of the shift register 21 become "0", so the output 20 of the verification result also becomes " 0”. At this time as well, it is t for the shift register 21 to be reset.
Since the four signals from 2□ to t25 do not become "0" continuously, it is determined whether the signals are valid or not.

Next, FIG. 4 shows an example in which no erroneous output occurs in response to an abnormal signal. In FIG. 4, the clock signal 40 is also considered valid when four or more received signals 10 take the same value consecutively.
is designed so that one pulse is output for three input signals. Now the received signal 10 contains 3 signals (from t42 to 144
) If the error signal "1" is input and returns to normal after t45, the first stage output 31 of the shift register 21 at t43
is once set to "1", but when the received signal 10 becomes "0" at time t45, the negative input AND element 22
The reset signal 35 becomes “1” because the zero force becomes “0”.
As a result, the shift register 21 is reset and all outputs become "0", so the output 20 of the matching result remains "0", and the influence of the erroneous signal at t441 is removed from t42. On the other hand, if we look at the case where the signal was "1" continuously until time t□, but an incorrect "0" signal was received from t,2 to '54, the first positive signal of the clock signal 40 is When the direction edge appears, the first stage output 31 of the shift register 21
is "0". When the second stage output 32 becomes "0" at the next positive edge t56, the received signal 10 has returned to the normal value "1", so the clip-flop 21 is The reset signal 35 remains at "0" and is not reset. Also, during t66 to t58 and t6□ to t64, the second stage output 32 and fourth stage output 34 are respectively "0", but when both are joint, they do not become "0", so the matching result is output through the OR element 23. 20 holds the normal value "1".

According to this circuit, the shift register 21 always has four digits regardless of the number of circuits necessary to consider it as a valid signal, and also has three inputs including the negative input AND element 22 and the OR element 23. A signal matching circuit can be configured with the elements, and the circuit is considerably simpler than the conventional example, and a matching circuit can be easily configured even for a large number of parallel signals such as 16 to 32 bits. Furthermore, by changing the period of the clock signal 40, the number of times necessary to consider it as a valid signal can be easily changed.

It is also possible to change this number of times depending on the status of the receiving device, so the signal matching circuit has the flexibility of keeping the number of times small during normal times and increasing the number of times only in special cases. is possible.

Advantageous Effects of Invention According to the present invention, it is possible to provide a signal matching circuit with a signal matching function using a simple circuit with a small number of circuit components, and also to be able to flexibly change setting values necessary for the signal matching function.

[Brief explanation of the drawing]

Fig. 1 shows a conventional signal matching circuit, Fig. 2 shows an embodiment of the signal matching circuit of the present invention, Fig. 3 shows the normal time-series operation of the circuit shown in Fig. 2, and Fig. 4 shows an abnormality as well. FIG. 3 is a diagram showing a time-series operation when receiving a signal.

Claims (1)

[Claims] 1. The received signal is input to a signal matching circuit that increases the reliability of the signal by determining that it is a legitimate received signal only when the digital signal is received multiple times and the same value is received consecutively for a certain number of times or more. The receiver is composed of a shift register that shifts according to a clock signal, a gate element that generates a reset signal r for the shift register from the output of the shift register and the received signal, and a gate element that obtains the output of the signal matching circuit from the output of a different digit of the shift register. Timely signal matching circuit.