SU1332315A2 - Device for computing functions - Google Patents

Abstract

The invention relates to computing and can be used in computing devices that perform the calculation of function A and control this function with hardware. The purpose of the invention is to check the correctness of the calculation of the function A. The device consists of a register of 1 argument, an input of 2 arguments of the device, a block of 3 elements EXCLUSIVE OR, a block of 4 calculation of a function, a register of 5 results, a block of 6 multiplication, a register of 7 control code, a circuit 8 comparisons, AND element 9, AND block 10 and synchronization block 13, which contains a control input, first, second and third flip-flops, a pulse generator, an AND element and a pulse distributor. The device, unlike the prototype, verifies the correctness of the calculation of the function Z A. The device calculates the result of the A-functions A and A. At the time the product of the code produces a signal with a comparative control signal, the correctness is high (L number of the function A. 2 nl. N

Description

one

The invention relates to a visual technology, can be used to create digital computers that perform calculated function A, which control this function by hardware, and is an improvement of the known device according to the main author. No. 520595.

The purpose of the invention is to control the correctness of the calculation of function A.

Figure 1 shows a block diagram of a device for calculating function A; figure 2 - diagram of the synchronization unit.

The composition of the device

for

calculating function A enters argument register 1, information input of device argument, unit 3 elements EXCLUSIVE OR, unit 4 calculating function A result register 5, multiplication unit, control code register 7, comparison circuit 8, And element unit 10 of elements AND, information output 1 devices, error signal output 12 and synchronization unit 13, which contains the control input of the device, first, second and third triggers 15-17, pulse generator 18, element 19, pulse distributor 20, first, second, third and fourth outputs 21 24

Functional Calculation Unit 4 calculates the function ZA (where X is the value of the argument represented by an n-bit binary code 1. If we calculate ZA, where X is the inverse value of X, then it can be used to check the correctness of the calculation of Z A. Indeed, taking into account that X 2 -1 - X it can be shown that Z A

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Z. Since A is constant, it can be used as a control value. If the calculated value Z Z coincides with the value of the reference value A, then the calculation of function A is performed correctly and the calculation unit of function A does not contain any faults, otherwise the device does not work correctly. This circumstance is the basis for checking the correctness of the 10

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VIA function A in the proposed device.

A device for calculating function A operates as follows.

In the initial state in the control code register is written the value

.1 A. On the signal to start the operation

calculating the function A, arriving at the control input 14 in block 13, the first trigger 15 is set to one, and the second 16 and third 17 triggers are reset. Zero signals from the outputs of the second trigger 16 and the third trigger 17 are received respectively on the third 23 and fourth 24 outputs of the block 13 and pass on, respectively, to the second input of the 3 element block EXCLUSIVE OR and to the second input of the AND 9 element. Zero signal from the output of the AND 9 element arrives at the second ekhodnogo block 10 elements And, and thus prohibits the issuance of information on the information output 1 of the device. The zero signal at the second input of the block 3 elements EXCLUSIVE OR provides the transmission of information from its first input to the output without change. Simultaneously, a single signal from the output of the first trigger 15 is fed to the first input element And 19 of block 13 and allows the transmission through it of pulses from the generator 18 pulses 35 to the input of the distributor 20 pulses, which is sequential in time; generates a pulse on the first, second, third and fourth outputs, respectively. The pulse from the first output of the distributor 20 pulses is fed to the first 21 output of the block 13 and further to the input of the register 1 argument. This signal provides rewriting of the code of the argument X, which is the input of the argument 2 of the device to the register 1 of the argument.

The contents of the argument register 1. comes to the first input of the block 3 elements EXCLUSIVE OR and further

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without changing to the input of block 4, the computation of function A to compute y

functions a. The result of the calculation is fed to the information input of the result register 5.

The pulse from the second output of the distributor 20 pulses is fed to the second output 22 of the block 13 and then to the input of the record of the result register 5,

3

thereby ensuring that the calculated value of A is written to it.

P1 pulse from the third output of the pulse distributor 20 is fed to the single input of the second trigger 16 and thus sets it to the single state. The single signal from the output of the second trigger 16 goes to the third output 23 of the block 13 and then to the second input of the block 3 EXCLUSIVE OR. A single signal at the second input of block 3 of the EXCLUSIVE OR element provides a transmission to the input of block 4 of the calculation of function A of the inverse value of the argument gen (X) for the calculation of function A. The result of the calculation is fed to the first input of the multiplication unit 6, the second input of which from the result register 5 receives the previously calculated value.

As a result of the multiplication operation, the value that is fed to the first input of the comparison circuit 8 will be calculated at the output of the multiplication unit 6. The second input of the comparison circuit with the control code register 7 receives a control value. As a result, the comparison between A A and control A is performed, the values. At the output of the comparison circuit 8, a signal is generated that takes a single value if the compared values coincide and takes a zero value if they are unequal. This signal is fed to the first input of the element I9,

A single pulse from the fourth output of the signal distributor 20 is supplied to the single input of the third trigger 17 and to the reset input of the first trigger 15. As a result, the third trigger 17 is set to the single position, and the first trigger 15 to the zero position. The zero signal from the output of the first trigger 15 is fed to the first input element And 19, thereby prohibiting the arrival of pulses at the input of the distributor 20 pulses. At the same time a single signal from the output of the third trigger 17 is fed to the fourth output 24 of block 13 and further to the second input of the element 9, allowing the passage through the last signal from the output of the circuit 8

If at the output of the comparison circuit 8 there is a single signal, then it goes through the AND 9 element to the output

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Claims (1)

error signal, signaling about the right. the execution of operation A, and. at the same time it arrives at the first input of the block 10 of the And elements, thereby permitting the output of the correct value A to the information output of the device from the register 5 of the result. If at the output of the comparison circuit 8 Q there is a zero signal, then it goes through the element 9 to the output 12 of the error signal and the first input of the block 10 elements I. At the same time, the contents of the result register 5 will not be output to the information output 11 of the device, so as during the operation of the device an error occurred. Invention Formula A device for calculating function A according to auth. № 520595, about tl and 20 chayush ;. with the fact that control of the correctness of the calculation of function A, the argument register is entered into it, the block of elements is EXCLUDED- 25 ALS OR, result register, multiplication unit, control code register, comparison circuit, element block. AND, AND element and synchronization block, the information input of the device argument is connected to the information input of the argument register, the course of which is connected to the first input -o .. house block elements EXCLUSIVE OR, the output of which is connected to the input of the block 3g ka calculate the function A, the output of which is connected to the information input of the result register and the first input of the multiplication unit, the output of which is connected to the first input of the matching circuit, the output of which is connected to the first input of the element And the output of which is connected to the output of the device error signal and the first input of the element block And whose output is connected to 45 informational output of the device, the output of the control code register is connected to the second input of the comparison circuit, the output of the result register is connected to the second inputs of the smart block 50 and the I block, the start input of the device is connected to the same input of the synchronization block, the first and second outputs of the block synchronization is connected respectively to the input55 of the record of the registers of the argument and the result, the third and fourth outputs of the synchronization block are connected respectively to the second inputs of the block of the EXCLUSIVE OR elements and the element And, / J n I C) UZ.Z