SU1423984A1 - Relay-type interpolator - Google Patents

Abstract

The invention relates to the field of computer technology and automation, and improves the accuracy, speed and reduce hardware costs. The interpolator contains a controlled pulse generator 1, a counter 2, registers 3,6, a node 4. Binary multiplication, a counter 5 and a torus 7. The inputs 10,12 and 14-17 are supplied with the values of the larger increment, the control code and signs of the coordinate orientation . The step increments along the leading coordinate are formed in each interpolation beat and their number corresponds to the value of the larger increment. Step increments in the slave coordinate are formed at the output of node 4 in accordance with the value of the control code in register 3. 2 Cp. f-ly, 6 ill. (L

Description

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The invention relates to automation and computing and can be used in output graphics devices and in computer numerical control systems.

The purpose of the invention is to improve the accuracy of speed and reduce hardware costs.

FIG. 1 shows a functional diagram of a linear interpolator; in fig. 2 and 3 are functional diagrams of the switch and controlled pulse generator; Figures 4-6 illustrate the control code calculation algorithm, timing diagrams, and an example of the interpolation of the straight segment, respectively.

The interpolator (FIG. 1) contains a controlled pulse generator 1, a counter 2, a register 3, a binary multiplication node 4, a counter 5, a register 6 and a switch 7. The interpolator has an initial setup input 8, a start input 9, a larger input 10 increments, entry 11 of the entry, entry 12 of the control code, entry 13 of the entry, inputs 14-17 of the coordinate orientation, outputs 18–21 step coordinate increments and exit .2 of the sign End of interpolation.

Switch 7 (Fig. 2) contains two multiplexer 23 and elements And 24 - 27.

The controlled pulse generator 1 (Fig. 3) contains a pulse generator 28, two flip-flops 29, 30 and two elements 31, 32. The interpolator works as follows.

Since in the interpolator, step increments in the leading coordinate are formed in each interpolation cycle, their number is equal to the value of the larger increment (BP), Step increments in the driven coordinate are formed at the output of node 4. In this case, the value of the control code in register 3 must be so that the number of pulses corresponding to the value of the smaller increment (MP) is formed at the output of node 4 for the number of clock cycles equal to the BP.

When using a digital integrator with sequential transfer (counter 5 and node 4), the number of pulses B due to the i-th bit of the control code during the time of the power supply is with the ratio

B.- EQi2rJj

 2 J4.4. where L ILL is the integer selection operator

parts, P.

In order for the number of clock cycles equal to the power supply unit, at the output of the integrator to form MP pulses, the ratio must be satisfied

ten

21 a b,

ir 1

0

where a. - the value of the digit in the i-th digit

control code. Thus, the task of determining 5 of the control code is reduced to the definition of a,, a,,. ,, af, by known values of BP and MP using the above ratios. The values are B; and they equals 0 the value of the MP.

In the linear interpolator, the segment is set by the direct BP value, the value of the control code, and the signs defining the orientation 5 and the vector location relative to the coordinate axes.

Interpol tor works in the following way.

At input 8 of the interpolator, an impulse comes from the external device, which sets generator 1 to the initial position. At the output of generator 1, no pulses are generated. B, register 6, according to the active signal level at input 5 and 13, the value of the signs is recorded. The correspondence between active signal levels, features and their corresponding inputs is as follows.

Sign Active Log 0 level

 1 14 15

Zn X 1 16 Zn dY 1. 17 The register 3 from an external device records the value of the control code, which is fed to the input 12 of the interpolator. The register is written to the zero level supplied to the input 11 of the interpolator.

The counter 2 records the value of the power supply unit input to the input 10 of the interpolator. The recording of the PSU is carried out by the zero level of the signal applied to the input 9 of the interpolator. On the leading edge of the specified signal, the generator 1 is started, and at its output. a sequence is formed

pulses of a given frequency. This sequence of pulses arrives at the counting input of counter 5, and at the output of binary multiplier 4, a sequence of pulses is formed corresponding to the MP (along the driven coordinate). Switch 7 performs, depending on the value of the attributes recorded in register 6, re-switching the frequency streams coming from generator 1 and binary multiplier 4 to one of the outputs + X, -X, + Y, -Y (18-21).

With the arrival of each pulse from generator 1, the contents of counter 2 are reduced by one. When the generator 1 produces a number of pulses equal to the PSU, a transfer signal is generated at the output of the counter 2, leading to the installation of the generator 1 to its initial state, in which the pulses are not output to the generator 1. When the generator 1 pulses are output, a level 1 is generated at the output 22, signaling that the interpolator generates step increments. After the output of the BP pulses, at the output 22, a signal O is generated, signaling that the interpolator is ready to receive new initial data.

The calculation of the control code can be carried out according to the algorithm (Fig. 4) by a microprocessor or microcomputer. Part of the flowchart of the algorithm to the bar

,

line serves to determine the number of them

,

pulses of B-due to the i-ro bit of the control code during the BP time by the formula

AT

GBP + 2

Jti-H 1 2f The above formula is implemented by a successive shift of the BP (division by 2) and addition 1 with an odd value of the shifted operand.

The lower part of the flowchart of the algorithm serves to determine the value of the digits (O or 1) in the i-M bit of the control code by balancing the MP code with weights B.

The time diagram of the work (Fig.5) of the interpolator is given for,. For these increments, the value of the control code is 1010, where the one on the right corresponds to the highest bit. In the timing diagram, the shaded pulses taken from the first and third outputs of counter 5 are sampled by the binary multiplication unit 4 and added together. Active

0

„

the front of these pulses is the leading edge. From the output of node 4 binary multiplication, the pulses taken from the first and third outputs of counter 5 are fed to the input of the switch. From the time diagrams it follows that the first information input of the switch 7 pulses come in each clock cycle. To the second information input of the switch 7, the pulses come from the output of the binary multiplier formed by the node 4 and the counter 5, with the pulses being formed not every clock cycle. Thus, on the second, sixth, eighth, and tenth cycles, pulses are not formed (the latter is reflected in the time line by a dashed line).

A segment of a vertical straight line formed under the influence of step increments corresponding to the initial increments, is shown in FIG. 6

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Claims (3)

25 claims ,, „ one . A linear interpolator containing a controlled pulse generator, a binary multiplier node, the first counter and two registers, the outputs of the first register and counter are connected to the first and second inputs of the binary multiplier node, the start input of the controlled pulse generator is connected to the start input of the interpolator, This is due to the fact that, in order to increase accuracy, speed and reduce hardware costs, a second counter and a switch are introduced into it, the outputs of which are interpolator outputs of stepping coordinate increments a, the information inputs of the second counter, the first and second registers are the inputs for setting the larger increment of the control code and the signs of the coordinate orientation of the interpolator, respectively; the recording inputs of the first and second registers are the first and second recording inputs of the interpolator, the trigger input of which is connected to the input records of the second counter and with the reset input of the first counter, the output of the clock sequence of the controlled pulse generator is connected with the counting inputs of the first and second counters and with the first nformatsionnym kom-- mutator input, a second data input and control inputs of which soedine30 35 40 45 50 55 With the output of the binary multiplier node and the outputs of the second register, respectively, the transfer output of the second counter and the input of the initial setup of the interpolator are connected to the first and second stops of the controlled pulse generator, the output of which the stop sign is the interpolator interpolation end. 2. The interpolator according to claim Ij is based on the fact that the switchboard contains two multiplexers and four I elements, whose outputs form the switch output, the first inputs of all And elements and the first and second address inputs of the first and second multiplexers are connected to the corresponding the control inputs of the switch, the first information input of which is connected to the second, third and fourth information inputs of the first multiplexer and the first, third and fourth information inputs of the JBToporo multiplexer, the second information input switch is connected by ip. the first input of the first multiplex | ja and with the second input of the second multiplex | sheksor, the output of the first multiplex is connected to the second inputs of the first and the second elements And, the output of the second multiplexer is connected to the second inputs of the third and fourth elements I. 3. The interpolator according to claim 1, which is based on the fact that the controlled pulse generator contains the first AND element, the output of which is the output of the clock sequence controlled by the pulse generator, two triggers, the pulse generator whose output is connected to the first input of the first element And with the synchronization input of the second trigger, the output of which is the output of the stop sign of the controlled pulse generator and connected to the second input of the first And element, the second And element, the first and second inputs of which are the first and torym inputs ostano- ra controllable pulse generator vhots, start and input logic unit which soedine.ny a synchronization input and a data input of the first flip-flop, whose output is connected to the data input of second flip-flop inverse reset input connected to the output of the second element And with the inverse reset input of the first trigger. LO 32 yy // M S / TffftaA4 5.8 22 e / RZ U23984 If UHfr SouuMffPO f HOiffumf / v} 1 (and / (l joaSo rr / i / Mffre / 3ftafl f / oa PLAYAAJALLAAYAYAYAM J - fftino Sfo / ra Lilgu SjltfAO / : I I 1 I t I f t  J „L. 1 .lJJ :. 7 PG s 9 7 to 9 .lJJ..UJJJ 7 3 and S at 79 9 ,, - ff / J J l  t Fig 6