SU1406586A1 - Generator of l-sequences - Google Patents

Abstract

The invention relates to computing and can be used in systems for test diagnostics of discrete objects. The purpose of the invention is to expand the class of tasks by increasing the period of the generated sequence. The generator contains setting 1 and clock 2 inputs, counter 3, generator 4 input effects and block 5 of the accelerated division of polynomials. The goal is achieved by introducing counter 3 and generator 4 input actions. 7 il.

Description

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The invention relates to a computing environment and can be used in test diagnostics systems for discrete objects.

The purpose of the invention is to expand the class of tasks by increasing the period of the generated sequence.

Figure 1 presents the scheme of the generator; 2a, b are examples of the implementation of the generator of input actions; FIG. 3 is an example of the implementation of an accelerated division of polynomials; Fig.4.5 shows the response of an accelerated division of polynomials into input sets; FIGS. 6, 7 — consecutive connections of the triggers of the block of FIG. 3.

The generator (Fig. 1) contains installation 1 and clock 2 inputs, modulo counter 3, generator 4 input actions and block 5 accelerated division of polynomials, which contains multiplication nodes 6, addition nodes 7 and division 8, N of registers 9, where N is degree of the generating polynomial f (x) .. ..a.x +. . .a, x + ao, aa e eGF (L).

45

40

. The accelerated division of polynomials divides by the polynomial F (x), which is the determinant of the matrix T - XE, where E is the identity matrix.

Figures 2a and 2b show two options for constructing an input generator. The discharge outputs of counters 10 modulo L are the outputs of the input actions generator, the clock input of which is connected to the counting input of the counter 10, and each bth pulse arriving at the counting input of the i-counter of 10-,, (K-1), appearing at its output, enters the counting input of (i + 1) -ro counter 10 ;. The structure 55 of the generator of input actions, shown in Fig.26, is similar to the structure of the generator as a whole (Fig.1);

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The nodes of addition, multiplication, and division are combinational circuits that are based on the corresponding truth tables, the latter in turn are uniquely determined by the rules of addition, multiplication, and division in the Galois field of L elements. The value by which Q is multiplied in the ith node of the multiplication of each group of multiplication nodes 6 is determined by the corresponding coefficient a. generating polynomial. Node 8 divides by - a in field 5 GF (L). When log. On its inputs, the accelerated division of polynomials operates in accordance with the equation

Q (t-H) q (t). TS 0 where Q (t + 1) Cqi (t-H) ... q, (t + 1).;.

- qN (t + i);

Q (t) qi (t) ... q, (t) ... q (t); qj (t) and q- (t + 1) - the contents of the i-th register 9. respectively in moments

time t and (t + 1); T is a square matrix of order N, of the form

11 - counter modulo 8 l -1; 12 is the generator of input actions; 13 is the unit of accelerated division of polynomials, the degree of which constitutes a polynomial is K. The outputs of the registers of unit 13 of the accelerated division of polynomials 14; () arrive at the nodes 7 addition. The generator 12 input effects, in turn, may also have a structure similar to that shown in Fig.26, etc.

Before the start of operation by the signal at the input T, all sequential elements, with the exception of the registers of the accelerated division of polynomials, are set to the zero state. The registers 9 of the block of accelerated division of polynomials are set to one of the allowed states (forbidden

o or 1, therefore on fig. 3 are shown. Node 8 implements 10

15

20

25

are the states L, (L + 1), ...,

..., v) of any of the registers 9v, -9 fj).

FIG. 3 shows the scheme of the block 5 of the accelerated division of polynomials for the case,, f (x) x + x2 + 1. All multiplication nodes multiply by not

The value for 1 is also not shown. The registers 9, ..., N, whose bit size is generally equal, are output to triggers, since. In the device in question, transformations are performed in one cycle, which in a conventional device for dividing polynomials, corresponding to the equations:

rq, (t + 1) d (t) ® qjCt) ® q | t);

U (t + 1) qi (t);

U5 ((t),

performed per clock cycle. Equations, the unit of accelerated division of polynomials, shown in Fig. 3, have the following form:

rqi (t + 1) d5 (t) @ di (t) € tj5 (t) + q (t) ® qi (t); lq (t + 1) dj (t)) +); , q5 (t + 1)) ®q j (t) © q.j (t).

Consider the operation of the generator on the example of the cases considered in Figures 2a and 3. Each counter 10 in this situation degenerates into a trigger, and therefore, in fact, the generator of input actions can be considered as a three-bit binary counter. Counter 3 counts by module.

Let the initial state of the flip-flops 9, -9h equal to 7 (111). Before proceeding directly to the description of the operation of the device, consider the reaction of the accelerated dividing unit of the polynomials shown in Fig. 3 to different input sets d, d, d j (Fig.4.5),

Column 1 in FIG. 4 corresponds to the situation when O 0 const. Columns A and B correspond to the usual device for dividing polynomials (see the first of the above systems of equations): A is the input sequence (1) d (2) ... d (t) ... didjdjd, d,; d. .., d (t) ELO.P; H is the state of the device shift register (). The successive states of the triggers of the device shown in FIG. 3 are circled. Column C shows an acceleration block transition diagram.

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ten

15

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divisions of polynomials for the situation under consideration (codes О О О О ... 1 1 1 are marked respectively О ... 7). Columns 2-4 in FIG. 4 and columns 1-4 in FIG. 3 correspond to the cases when the sets are d d dj const and are equal to 010, 11 O, 001, 101, 011,111,000, respectively.

Fig. 6 shows the successive states of the triggers of the device shown in Fig. 3, when O, 1, 2, ..., 7 codes arrive at its inputs from the counter outputs on the triggers 10, 10-1; Line A - State

0

five

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0

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counters neither

10, 10,

ten

q.q q flip-flops

3

 one

at 9 ,

consisted of 3

of

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which at a given fixed value of the set dfd-j dj Triggers cannot exit; C - consecutive states of the triggers (q, q, 2q3) 9,, 9,, 9h for a given value of the input set d-fd-id ,.

Thus, the first clock cycles at the input of the accelerated division of polynomials are the code О О О, and the triggers of the device shown in Fig. 3 pass through all the states from 7 to 2 (the 1st column in Fig. 6). The seventh clock pulse appearing at the output of the counter 3 switches the counters 10, 10.10 l | the generator of input effects in state 1 (at the inputs of the accelerated division of polynomials - code 1 О 0) and the next 7 cycles, the triggers 9, 9, j, 9 will be in the state О 1 0 (2) (2nd the column in Fig.6). The next 7 clocks, counters 10 ,, 10 ,, will be in state 2, and triggers 9, 9, 9 will go through all the states from 2 to 0 in succession (the 3rd column in Fig. 6). All of the above switching triggers 91.9 g, 9h are shown in FIG. 7 as follows: 7-22-22-0. The sequence of further switchings is also reflected in Fig. 7, from which it can be seen that the period of the sequence being formed, taken from the outputs of one of the triggers (generally from one of the registers 9), has a period M (L -1) () b (2з- 1) () -23 7-7-8 392.

Claims (1)

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